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path: root/drivers/gpu/drm/radeon/cik.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/cik.c')
-rw-r--r--drivers/gpu/drm/radeon/cik.c27
1 files changed, 18 insertions, 9 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index adbdb6503b05..9cd2bc989ac7 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -77,6 +77,8 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev);
77static void cik_program_aspm(struct radeon_device *rdev); 77static void cik_program_aspm(struct radeon_device *rdev);
78static void cik_init_pg(struct radeon_device *rdev); 78static void cik_init_pg(struct radeon_device *rdev);
79static void cik_init_cg(struct radeon_device *rdev); 79static void cik_init_cg(struct radeon_device *rdev);
80static void cik_fini_pg(struct radeon_device *rdev);
81static void cik_fini_cg(struct radeon_device *rdev);
80static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev, 82static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
81 bool enable); 83 bool enable);
82 84
@@ -1692,6 +1694,7 @@ static int cik_init_microcode(struct radeon_device *rdev)
1692 fw_name); 1694 fw_name);
1693 release_firmware(rdev->smc_fw); 1695 release_firmware(rdev->smc_fw);
1694 rdev->smc_fw = NULL; 1696 rdev->smc_fw = NULL;
1697 err = 0;
1695 } else if (rdev->smc_fw->size != smc_req_size) { 1698 } else if (rdev->smc_fw->size != smc_req_size) {
1696 printk(KERN_ERR 1699 printk(KERN_ERR
1697 "cik_smc: Bogus length %zu in firmware \"%s\"\n", 1700 "cik_smc: Bogus length %zu in firmware \"%s\"\n",
@@ -2845,10 +2848,8 @@ static void cik_gpu_init(struct radeon_device *rdev)
2845 rdev->config.cik.tile_config |= (3 << 0); 2848 rdev->config.cik.tile_config |= (3 << 0);
2846 break; 2849 break;
2847 } 2850 }
2848 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 2851 rdev->config.cik.tile_config |=
2849 rdev->config.cik.tile_config |= 1 << 4; 2852 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2850 else
2851 rdev->config.cik.tile_config |= 0 << 4;
2852 rdev->config.cik.tile_config |= 2853 rdev->config.cik.tile_config |=
2853 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 2854 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
2854 rdev->config.cik.tile_config |= 2855 rdev->config.cik.tile_config |=
@@ -3182,6 +3183,7 @@ int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3182 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3183 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3183 if (r) { 3184 if (r) {
3184 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3185 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3186 radeon_scratch_free(rdev, scratch);
3185 return r; 3187 return r;
3186 } 3188 }
3187 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 3189 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
@@ -3198,6 +3200,8 @@ int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3198 r = radeon_fence_wait(ib.fence, false); 3200 r = radeon_fence_wait(ib.fence, false);
3199 if (r) { 3201 if (r) {
3200 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3202 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3203 radeon_scratch_free(rdev, scratch);
3204 radeon_ib_free(rdev, &ib);
3201 return r; 3205 return r;
3202 } 3206 }
3203 for (i = 0; i < rdev->usec_timeout; i++) { 3207 for (i = 0; i < rdev->usec_timeout; i++) {
@@ -4187,6 +4191,10 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
4187 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 4191 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4188 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 4192 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4189 4193
4194 /* disable CG/PG */
4195 cik_fini_pg(rdev);
4196 cik_fini_cg(rdev);
4197
4190 /* stop the rlc */ 4198 /* stop the rlc */
4191 cik_rlc_stop(rdev); 4199 cik_rlc_stop(rdev);
4192 4200
@@ -4456,8 +4464,8 @@ static int cik_mc_init(struct radeon_device *rdev)
4456 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 4464 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
4457 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 4465 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
4458 /* size in MB on si */ 4466 /* size in MB on si */
4459 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 4467 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
4460 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 4468 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
4461 rdev->mc.visible_vram_size = rdev->mc.aper_size; 4469 rdev->mc.visible_vram_size = rdev->mc.aper_size;
4462 si_vram_gtt_location(rdev, &rdev->mc); 4470 si_vram_gtt_location(rdev, &rdev->mc);
4463 radeon_update_bandwidth_info(rdev); 4471 radeon_update_bandwidth_info(rdev);
@@ -4735,12 +4743,13 @@ static void cik_vm_decode_fault(struct radeon_device *rdev,
4735 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; 4743 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
4736 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT; 4744 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
4737 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT; 4745 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
4738 char *block = (char *)&mc_client; 4746 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
4747 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
4739 4748
4740 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", 4749 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
4741 protections, vmid, addr, 4750 protections, vmid, addr,
4742 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read", 4751 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
4743 block, mc_id); 4752 block, mc_client, mc_id);
4744} 4753}
4745 4754
4746/** 4755/**