diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/ci_smc.c')
-rw-r--r-- | drivers/gpu/drm/radeon/ci_smc.c | 39 |
1 files changed, 26 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/ci_smc.c b/drivers/gpu/drm/radeon/ci_smc.c index 53b43dd3cf1e..252e10a41cf5 100644 --- a/drivers/gpu/drm/radeon/ci_smc.c +++ b/drivers/gpu/drm/radeon/ci_smc.c | |||
@@ -47,10 +47,11 @@ int ci_copy_bytes_to_smc(struct radeon_device *rdev, | |||
47 | u32 smc_start_address, | 47 | u32 smc_start_address, |
48 | const u8 *src, u32 byte_count, u32 limit) | 48 | const u8 *src, u32 byte_count, u32 limit) |
49 | { | 49 | { |
50 | unsigned long flags; | ||
50 | u32 data, original_data; | 51 | u32 data, original_data; |
51 | u32 addr; | 52 | u32 addr; |
52 | u32 extra_shift; | 53 | u32 extra_shift; |
53 | int ret; | 54 | int ret = 0; |
54 | 55 | ||
55 | if (smc_start_address & 3) | 56 | if (smc_start_address & 3) |
56 | return -EINVAL; | 57 | return -EINVAL; |
@@ -59,13 +60,14 @@ int ci_copy_bytes_to_smc(struct radeon_device *rdev, | |||
59 | 60 | ||
60 | addr = smc_start_address; | 61 | addr = smc_start_address; |
61 | 62 | ||
63 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); | ||
62 | while (byte_count >= 4) { | 64 | while (byte_count >= 4) { |
63 | /* SMC address space is BE */ | 65 | /* SMC address space is BE */ |
64 | data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; | 66 | data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; |
65 | 67 | ||
66 | ret = ci_set_smc_sram_address(rdev, addr, limit); | 68 | ret = ci_set_smc_sram_address(rdev, addr, limit); |
67 | if (ret) | 69 | if (ret) |
68 | return ret; | 70 | goto done; |
69 | 71 | ||
70 | WREG32(SMC_IND_DATA_0, data); | 72 | WREG32(SMC_IND_DATA_0, data); |
71 | 73 | ||
@@ -80,7 +82,7 @@ int ci_copy_bytes_to_smc(struct radeon_device *rdev, | |||
80 | 82 | ||
81 | ret = ci_set_smc_sram_address(rdev, addr, limit); | 83 | ret = ci_set_smc_sram_address(rdev, addr, limit); |
82 | if (ret) | 84 | if (ret) |
83 | return ret; | 85 | goto done; |
84 | 86 | ||
85 | original_data = RREG32(SMC_IND_DATA_0); | 87 | original_data = RREG32(SMC_IND_DATA_0); |
86 | 88 | ||
@@ -97,11 +99,15 @@ int ci_copy_bytes_to_smc(struct radeon_device *rdev, | |||
97 | 99 | ||
98 | ret = ci_set_smc_sram_address(rdev, addr, limit); | 100 | ret = ci_set_smc_sram_address(rdev, addr, limit); |
99 | if (ret) | 101 | if (ret) |
100 | return ret; | 102 | goto done; |
101 | 103 | ||
102 | WREG32(SMC_IND_DATA_0, data); | 104 | WREG32(SMC_IND_DATA_0, data); |
103 | } | 105 | } |
104 | return 0; | 106 | |
107 | done: | ||
108 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); | ||
109 | |||
110 | return ret; | ||
105 | } | 111 | } |
106 | 112 | ||
107 | void ci_start_smc(struct radeon_device *rdev) | 113 | void ci_start_smc(struct radeon_device *rdev) |
@@ -197,6 +203,7 @@ PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev) | |||
197 | 203 | ||
198 | int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) | 204 | int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) |
199 | { | 205 | { |
206 | unsigned long flags; | ||
200 | u32 ucode_start_address; | 207 | u32 ucode_start_address; |
201 | u32 ucode_size; | 208 | u32 ucode_size; |
202 | const u8 *src; | 209 | const u8 *src; |
@@ -219,6 +226,7 @@ int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) | |||
219 | return -EINVAL; | 226 | return -EINVAL; |
220 | 227 | ||
221 | src = (const u8 *)rdev->smc_fw->data; | 228 | src = (const u8 *)rdev->smc_fw->data; |
229 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); | ||
222 | WREG32(SMC_IND_INDEX_0, ucode_start_address); | 230 | WREG32(SMC_IND_INDEX_0, ucode_start_address); |
223 | WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); | 231 | WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); |
224 | while (ucode_size >= 4) { | 232 | while (ucode_size >= 4) { |
@@ -231,6 +239,7 @@ int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) | |||
231 | ucode_size -= 4; | 239 | ucode_size -= 4; |
232 | } | 240 | } |
233 | WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); | 241 | WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); |
242 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); | ||
234 | 243 | ||
235 | return 0; | 244 | return 0; |
236 | } | 245 | } |
@@ -238,25 +247,29 @@ int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) | |||
238 | int ci_read_smc_sram_dword(struct radeon_device *rdev, | 247 | int ci_read_smc_sram_dword(struct radeon_device *rdev, |
239 | u32 smc_address, u32 *value, u32 limit) | 248 | u32 smc_address, u32 *value, u32 limit) |
240 | { | 249 | { |
250 | unsigned long flags; | ||
241 | int ret; | 251 | int ret; |
242 | 252 | ||
253 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); | ||
243 | ret = ci_set_smc_sram_address(rdev, smc_address, limit); | 254 | ret = ci_set_smc_sram_address(rdev, smc_address, limit); |
244 | if (ret) | 255 | if (ret == 0) |
245 | return ret; | 256 | *value = RREG32(SMC_IND_DATA_0); |
257 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); | ||
246 | 258 | ||
247 | *value = RREG32(SMC_IND_DATA_0); | 259 | return ret; |
248 | return 0; | ||
249 | } | 260 | } |
250 | 261 | ||
251 | int ci_write_smc_sram_dword(struct radeon_device *rdev, | 262 | int ci_write_smc_sram_dword(struct radeon_device *rdev, |
252 | u32 smc_address, u32 value, u32 limit) | 263 | u32 smc_address, u32 value, u32 limit) |
253 | { | 264 | { |
265 | unsigned long flags; | ||
254 | int ret; | 266 | int ret; |
255 | 267 | ||
268 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); | ||
256 | ret = ci_set_smc_sram_address(rdev, smc_address, limit); | 269 | ret = ci_set_smc_sram_address(rdev, smc_address, limit); |
257 | if (ret) | 270 | if (ret == 0) |
258 | return ret; | 271 | WREG32(SMC_IND_DATA_0, value); |
272 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); | ||
259 | 273 | ||
260 | WREG32(SMC_IND_DATA_0, value); | 274 | return ret; |
261 | return 0; | ||
262 | } | 275 | } |