diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/atombios_encoders.c')
-rw-r--r-- | drivers/gpu/drm/radeon/atombios_encoders.c | 89 |
1 files changed, 45 insertions, 44 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index f1f06ca9f1f5..b88c4608731b 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c | |||
@@ -57,22 +57,6 @@ static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) | |||
57 | } | 57 | } |
58 | } | 58 | } |
59 | 59 | ||
60 | static struct drm_connector * | ||
61 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder) | ||
62 | { | ||
63 | struct drm_device *dev = encoder->dev; | ||
64 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | ||
65 | struct drm_connector *connector; | ||
66 | struct radeon_connector *radeon_connector; | ||
67 | |||
68 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | ||
69 | radeon_connector = to_radeon_connector(connector); | ||
70 | if (radeon_encoder->devices & radeon_connector->devices) | ||
71 | return connector; | ||
72 | } | ||
73 | return NULL; | ||
74 | } | ||
75 | |||
76 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, | 60 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
77 | struct drm_display_mode *mode, | 61 | struct drm_display_mode *mode, |
78 | struct drm_display_mode *adjusted_mode) | 62 | struct drm_display_mode *adjusted_mode) |
@@ -253,7 +237,7 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action) | |||
253 | /* R4xx, R5xx */ | 237 | /* R4xx, R5xx */ |
254 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; | 238 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; |
255 | 239 | ||
256 | if (radeon_encoder->pixel_clock > 165000) | 240 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
257 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; | 241 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
258 | 242 | ||
259 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; | 243 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; |
@@ -265,7 +249,7 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action) | |||
265 | /* DFP1, CRT1, TV1 depending on the type of port */ | 249 | /* DFP1, CRT1, TV1 depending on the type of port */ |
266 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; | 250 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; |
267 | 251 | ||
268 | if (radeon_encoder->pixel_clock > 165000) | 252 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
269 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; | 253 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; |
270 | break; | 254 | break; |
271 | case 3: | 255 | case 3: |
@@ -349,7 +333,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) | |||
349 | } else { | 333 | } else { |
350 | if (dig->linkb) | 334 | if (dig->linkb) |
351 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | 335 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
352 | if (radeon_encoder->pixel_clock > 165000) | 336 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
353 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; | 337 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
354 | /*if (pScrn->rgbBits == 8) */ | 338 | /*if (pScrn->rgbBits == 8) */ |
355 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; | 339 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
@@ -388,7 +372,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) | |||
388 | } else { | 372 | } else { |
389 | if (dig->linkb) | 373 | if (dig->linkb) |
390 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | 374 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
391 | if (radeon_encoder->pixel_clock > 165000) | 375 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
392 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; | 376 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
393 | } | 377 | } |
394 | break; | 378 | break; |
@@ -432,7 +416,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
432 | switch (connector->connector_type) { | 416 | switch (connector->connector_type) { |
433 | case DRM_MODE_CONNECTOR_DVII: | 417 | case DRM_MODE_CONNECTOR_DVII: |
434 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ | 418 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
435 | if (drm_detect_monitor_audio(radeon_connector->edid) && | 419 | if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
436 | radeon_audio) | 420 | radeon_audio) |
437 | return ATOM_ENCODER_MODE_HDMI; | 421 | return ATOM_ENCODER_MODE_HDMI; |
438 | else if (radeon_connector->use_digital) | 422 | else if (radeon_connector->use_digital) |
@@ -443,7 +427,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
443 | case DRM_MODE_CONNECTOR_DVID: | 427 | case DRM_MODE_CONNECTOR_DVID: |
444 | case DRM_MODE_CONNECTOR_HDMIA: | 428 | case DRM_MODE_CONNECTOR_HDMIA: |
445 | default: | 429 | default: |
446 | if (drm_detect_monitor_audio(radeon_connector->edid) && | 430 | if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
447 | radeon_audio) | 431 | radeon_audio) |
448 | return ATOM_ENCODER_MODE_HDMI; | 432 | return ATOM_ENCODER_MODE_HDMI; |
449 | else | 433 | else |
@@ -457,7 +441,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
457 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | 441 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
458 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) | 442 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) |
459 | return ATOM_ENCODER_MODE_DP; | 443 | return ATOM_ENCODER_MODE_DP; |
460 | else if (drm_detect_monitor_audio(radeon_connector->edid) && | 444 | else if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
461 | radeon_audio) | 445 | radeon_audio) |
462 | return ATOM_ENCODER_MODE_HDMI; | 446 | return ATOM_ENCODER_MODE_HDMI; |
463 | else | 447 | else |
@@ -587,7 +571,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo | |||
587 | 571 | ||
588 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) | 572 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) |
589 | args.v1.ucLaneNum = dp_lane_count; | 573 | args.v1.ucLaneNum = dp_lane_count; |
590 | else if (radeon_encoder->pixel_clock > 165000) | 574 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
591 | args.v1.ucLaneNum = 8; | 575 | args.v1.ucLaneNum = 8; |
592 | else | 576 | else |
593 | args.v1.ucLaneNum = 4; | 577 | args.v1.ucLaneNum = 4; |
@@ -622,7 +606,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo | |||
622 | 606 | ||
623 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) | 607 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) |
624 | args.v3.ucLaneNum = dp_lane_count; | 608 | args.v3.ucLaneNum = dp_lane_count; |
625 | else if (radeon_encoder->pixel_clock > 165000) | 609 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
626 | args.v3.ucLaneNum = 8; | 610 | args.v3.ucLaneNum = 8; |
627 | else | 611 | else |
628 | args.v3.ucLaneNum = 4; | 612 | args.v3.ucLaneNum = 4; |
@@ -662,7 +646,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo | |||
662 | 646 | ||
663 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) | 647 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) |
664 | args.v4.ucLaneNum = dp_lane_count; | 648 | args.v4.ucLaneNum = dp_lane_count; |
665 | else if (radeon_encoder->pixel_clock > 165000) | 649 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
666 | args.v4.ucLaneNum = 8; | 650 | args.v4.ucLaneNum = 8; |
667 | else | 651 | else |
668 | args.v4.ucLaneNum = 4; | 652 | args.v4.ucLaneNum = 4; |
@@ -806,7 +790,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
806 | if (is_dp) | 790 | if (is_dp) |
807 | args.v1.usPixelClock = | 791 | args.v1.usPixelClock = |
808 | cpu_to_le16(dp_clock / 10); | 792 | cpu_to_le16(dp_clock / 10); |
809 | else if (radeon_encoder->pixel_clock > 165000) | 793 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
810 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); | 794 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
811 | else | 795 | else |
812 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | 796 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
@@ -821,7 +805,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
821 | 805 | ||
822 | if ((rdev->flags & RADEON_IS_IGP) && | 806 | if ((rdev->flags & RADEON_IS_IGP) && |
823 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { | 807 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { |
824 | if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { | 808 | if (is_dp || |
809 | !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { | ||
825 | if (igp_lane_info & 0x1) | 810 | if (igp_lane_info & 0x1) |
826 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; | 811 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
827 | else if (igp_lane_info & 0x2) | 812 | else if (igp_lane_info & 0x2) |
@@ -848,7 +833,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
848 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | 833 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
849 | if (dig->coherent_mode) | 834 | if (dig->coherent_mode) |
850 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | 835 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
851 | if (radeon_encoder->pixel_clock > 165000) | 836 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
852 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; | 837 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; |
853 | } | 838 | } |
854 | break; | 839 | break; |
@@ -863,7 +848,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
863 | if (is_dp) | 848 | if (is_dp) |
864 | args.v2.usPixelClock = | 849 | args.v2.usPixelClock = |
865 | cpu_to_le16(dp_clock / 10); | 850 | cpu_to_le16(dp_clock / 10); |
866 | else if (radeon_encoder->pixel_clock > 165000) | 851 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
867 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); | 852 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
868 | else | 853 | else |
869 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | 854 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
@@ -891,7 +876,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
891 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | 876 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
892 | if (dig->coherent_mode) | 877 | if (dig->coherent_mode) |
893 | args.v2.acConfig.fCoherentMode = 1; | 878 | args.v2.acConfig.fCoherentMode = 1; |
894 | if (radeon_encoder->pixel_clock > 165000) | 879 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
895 | args.v2.acConfig.fDualLinkConnector = 1; | 880 | args.v2.acConfig.fDualLinkConnector = 1; |
896 | } | 881 | } |
897 | break; | 882 | break; |
@@ -906,7 +891,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
906 | if (is_dp) | 891 | if (is_dp) |
907 | args.v3.usPixelClock = | 892 | args.v3.usPixelClock = |
908 | cpu_to_le16(dp_clock / 10); | 893 | cpu_to_le16(dp_clock / 10); |
909 | else if (radeon_encoder->pixel_clock > 165000) | 894 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
910 | args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); | 895 | args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
911 | else | 896 | else |
912 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | 897 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
@@ -914,7 +899,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
914 | 899 | ||
915 | if (is_dp) | 900 | if (is_dp) |
916 | args.v3.ucLaneNum = dp_lane_count; | 901 | args.v3.ucLaneNum = dp_lane_count; |
917 | else if (radeon_encoder->pixel_clock > 165000) | 902 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
918 | args.v3.ucLaneNum = 8; | 903 | args.v3.ucLaneNum = 8; |
919 | else | 904 | else |
920 | args.v3.ucLaneNum = 4; | 905 | args.v3.ucLaneNum = 4; |
@@ -951,7 +936,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
951 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | 936 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
952 | if (dig->coherent_mode) | 937 | if (dig->coherent_mode) |
953 | args.v3.acConfig.fCoherentMode = 1; | 938 | args.v3.acConfig.fCoherentMode = 1; |
954 | if (radeon_encoder->pixel_clock > 165000) | 939 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
955 | args.v3.acConfig.fDualLinkConnector = 1; | 940 | args.v3.acConfig.fDualLinkConnector = 1; |
956 | } | 941 | } |
957 | break; | 942 | break; |
@@ -966,7 +951,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
966 | if (is_dp) | 951 | if (is_dp) |
967 | args.v4.usPixelClock = | 952 | args.v4.usPixelClock = |
968 | cpu_to_le16(dp_clock / 10); | 953 | cpu_to_le16(dp_clock / 10); |
969 | else if (radeon_encoder->pixel_clock > 165000) | 954 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
970 | args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); | 955 | args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
971 | else | 956 | else |
972 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | 957 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
@@ -974,7 +959,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
974 | 959 | ||
975 | if (is_dp) | 960 | if (is_dp) |
976 | args.v4.ucLaneNum = dp_lane_count; | 961 | args.v4.ucLaneNum = dp_lane_count; |
977 | else if (radeon_encoder->pixel_clock > 165000) | 962 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
978 | args.v4.ucLaneNum = 8; | 963 | args.v4.ucLaneNum = 8; |
979 | else | 964 | else |
980 | args.v4.ucLaneNum = 4; | 965 | args.v4.ucLaneNum = 4; |
@@ -1014,7 +999,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
1014 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | 999 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1015 | if (dig->coherent_mode) | 1000 | if (dig->coherent_mode) |
1016 | args.v4.acConfig.fCoherentMode = 1; | 1001 | args.v4.acConfig.fCoherentMode = 1; |
1017 | if (radeon_encoder->pixel_clock > 165000) | 1002 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1018 | args.v4.acConfig.fDualLinkConnector = 1; | 1003 | args.v4.acConfig.fDualLinkConnector = 1; |
1019 | } | 1004 | } |
1020 | break; | 1005 | break; |
@@ -1137,7 +1122,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, | |||
1137 | if (dp_clock == 270000) | 1122 | if (dp_clock == 270000) |
1138 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | 1123 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
1139 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; | 1124 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; |
1140 | } else if (radeon_encoder->pixel_clock > 165000) | 1125 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1141 | args.v1.sDigEncoder.ucLaneNum = 8; | 1126 | args.v1.sDigEncoder.ucLaneNum = 8; |
1142 | else | 1127 | else |
1143 | args.v1.sDigEncoder.ucLaneNum = 4; | 1128 | args.v1.sDigEncoder.ucLaneNum = 4; |
@@ -1156,7 +1141,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, | |||
1156 | else if (dp_clock == 540000) | 1141 | else if (dp_clock == 540000) |
1157 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; | 1142 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; |
1158 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; | 1143 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; |
1159 | } else if (radeon_encoder->pixel_clock > 165000) | 1144 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1160 | args.v3.sExtEncoder.ucLaneNum = 8; | 1145 | args.v3.sExtEncoder.ucLaneNum = 8; |
1161 | else | 1146 | else |
1162 | args.v3.sExtEncoder.ucLaneNum = 4; | 1147 | args.v3.sExtEncoder.ucLaneNum = 4; |
@@ -1341,7 +1326,8 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |||
1341 | switch (mode) { | 1326 | switch (mode) { |
1342 | case DRM_MODE_DPMS_ON: | 1327 | case DRM_MODE_DPMS_ON: |
1343 | /* some early dce3.2 boards have a bug in their transmitter control table */ | 1328 | /* some early dce3.2 boards have a bug in their transmitter control table */ |
1344 | if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) | 1329 | if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) || |
1330 | ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) | ||
1345 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | 1331 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1346 | else | 1332 | else |
1347 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); | 1333 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
@@ -1351,8 +1337,6 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |||
1351 | ATOM_TRANSMITTER_ACTION_POWER_ON); | 1337 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
1352 | radeon_dig_connector->edp_on = true; | 1338 | radeon_dig_connector->edp_on = true; |
1353 | } | 1339 | } |
1354 | if (ASIC_IS_DCE4(rdev)) | ||
1355 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); | ||
1356 | radeon_dp_link_train(encoder, connector); | 1340 | radeon_dp_link_train(encoder, connector); |
1357 | if (ASIC_IS_DCE4(rdev)) | 1341 | if (ASIC_IS_DCE4(rdev)) |
1358 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); | 1342 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); |
@@ -1363,7 +1347,10 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |||
1363 | case DRM_MODE_DPMS_STANDBY: | 1347 | case DRM_MODE_DPMS_STANDBY: |
1364 | case DRM_MODE_DPMS_SUSPEND: | 1348 | case DRM_MODE_DPMS_SUSPEND: |
1365 | case DRM_MODE_DPMS_OFF: | 1349 | case DRM_MODE_DPMS_OFF: |
1366 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); | 1350 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) |
1351 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | ||
1352 | else | ||
1353 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); | ||
1367 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { | 1354 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1368 | if (ASIC_IS_DCE4(rdev)) | 1355 | if (ASIC_IS_DCE4(rdev)) |
1369 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); | 1356 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
@@ -1810,7 +1797,21 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |||
1810 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | 1797 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1811 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | 1798 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1812 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | 1799 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1813 | if (ASIC_IS_DCE4(rdev)) { | 1800 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
1801 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | ||
1802 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | ||
1803 | |||
1804 | if (!connector) | ||
1805 | dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; | ||
1806 | else | ||
1807 | dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); | ||
1808 | |||
1809 | /* setup and enable the encoder */ | ||
1810 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); | ||
1811 | atombios_dig_encoder_setup(encoder, | ||
1812 | ATOM_ENCODER_CMD_SETUP_PANEL_MODE, | ||
1813 | dig->panel_mode); | ||
1814 | } else if (ASIC_IS_DCE4(rdev)) { | ||
1814 | /* disable the transmitter */ | 1815 | /* disable the transmitter */ |
1815 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | 1816 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1816 | /* setup and enable the encoder */ | 1817 | /* setup and enable the encoder */ |