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path: root/drivers/gpu/drm/radeon/atombios_crtc.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/atombios_crtc.c')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c30
1 files changed, 28 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 3cd3234ba0af..529a3a704731 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -531,6 +531,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
531 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 531 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
532 else 532 else
533 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 533 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
534
535 if (rdev->family < CHIP_RV770)
536 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
534 } else { 537 } else {
535 pll->flags |= RADEON_PLL_LEGACY; 538 pll->flags |= RADEON_PLL_LEGACY;
536 539
@@ -559,7 +562,6 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
559 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 562 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
560 if (ss_enabled) { 563 if (ss_enabled) {
561 if (ss->refdiv) { 564 if (ss->refdiv) {
562 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
563 pll->flags |= RADEON_PLL_USE_REF_DIV; 565 pll->flags |= RADEON_PLL_USE_REF_DIV;
564 pll->reference_div = ss->refdiv; 566 pll->reference_div = ss->refdiv;
565 if (ASIC_IS_AVIVO(rdev)) 567 if (ASIC_IS_AVIVO(rdev))
@@ -957,7 +959,11 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
957 /* adjust pixel clock as needed */ 959 /* adjust pixel clock as needed */
958 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); 960 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
959 961
960 if (ASIC_IS_AVIVO(rdev)) 962 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
963 /* TV seems to prefer the legacy algo on some boards */
964 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
965 &ref_div, &post_div);
966 else if (ASIC_IS_AVIVO(rdev))
961 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 967 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
962 &ref_div, &post_div); 968 &ref_div, &post_div);
963 else 969 else
@@ -1005,6 +1011,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1005 uint64_t fb_location; 1011 uint64_t fb_location;
1006 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1012 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1007 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1013 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1014 u32 tmp;
1008 int r; 1015 int r;
1009 1016
1010 /* no fb bound */ 1017 /* no fb bound */
@@ -1133,6 +1140,15 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1133 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1140 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1134 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 1141 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1135 1142
1143 /* pageflip setup */
1144 /* make sure flip is at vb rather than hb */
1145 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1146 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1147 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1148
1149 /* set pageflip to happen anywhere in vblank interval */
1150 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1151
1136 if (!atomic && fb && fb != crtc->fb) { 1152 if (!atomic && fb && fb != crtc->fb) {
1137 radeon_fb = to_radeon_framebuffer(fb); 1153 radeon_fb = to_radeon_framebuffer(fb);
1138 rbo = gem_to_radeon_bo(radeon_fb->obj); 1154 rbo = gem_to_radeon_bo(radeon_fb->obj);
@@ -1163,6 +1179,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1163 uint64_t fb_location; 1179 uint64_t fb_location;
1164 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1180 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1165 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1181 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1182 u32 tmp;
1166 int r; 1183 int r;
1167 1184
1168 /* no fb bound */ 1185 /* no fb bound */
@@ -1290,6 +1307,15 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1290 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1307 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1291 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 1308 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1292 1309
1310 /* pageflip setup */
1311 /* make sure flip is at vb rather than hb */
1312 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1313 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1314 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1315
1316 /* set pageflip to happen anywhere in vblank interval */
1317 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1318
1293 if (!atomic && fb && fb != crtc->fb) { 1319 if (!atomic && fb && fb != crtc->fb) {
1294 radeon_fb = to_radeon_framebuffer(fb); 1320 radeon_fb = to_radeon_framebuffer(fb);
1295 rbo = gem_to_radeon_bo(radeon_fb->obj); 1321 rbo = gem_to_radeon_bo(radeon_fb->obj);