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-rw-r--r--drivers/gpu/drm/nouveau/Makefile4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_acpi.c1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c155
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h7
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c67
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_channel.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_connector.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_debugfs.c5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dma.c5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dp.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h46
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_encoder.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c55
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_grctx.c1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c610
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c124
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_sgdma.c19
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c20
-rw-r--r--drivers/gpu/drm/nouveau/nv04_crtc.c6
-rw-r--r--drivers/gpu/drm/nouveau/nv04_fbcon.c6
-rw-r--r--drivers/gpu/drm/nouveau/nv40_fifo.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c21
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c26
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.h1
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fb.c32
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fbcon.c15
-rw-r--r--drivers/gpu/drm/nouveau/nv50_gpio.c76
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c29
-rw-r--r--drivers/gpu/drm/nouveau/nv50_grctx.c32
-rw-r--r--drivers/gpu/drm/nouveau/nv50_instmem.c16
-rw-r--r--drivers/gpu/drm/nouveau/nv50_sor.c25
33 files changed, 1115 insertions, 315 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 32db806f3b5a..453df3f6053f 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -12,7 +12,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
12 nouveau_dp.o nouveau_grctx.o \ 12 nouveau_dp.o nouveau_grctx.o \
13 nv04_timer.o \ 13 nv04_timer.o \
14 nv04_mc.o nv40_mc.o nv50_mc.o \ 14 nv04_mc.o nv40_mc.o nv50_mc.o \
15 nv04_fb.o nv10_fb.o nv40_fb.o \ 15 nv04_fb.o nv10_fb.o nv40_fb.o nv50_fb.o \
16 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \ 16 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \
17 nv04_graph.o nv10_graph.o nv20_graph.o \ 17 nv04_graph.o nv10_graph.o nv20_graph.o \
18 nv40_graph.o nv50_graph.o \ 18 nv40_graph.o nv50_graph.o \
@@ -22,7 +22,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
22 nv50_cursor.o nv50_display.o nv50_fbcon.o \ 22 nv50_cursor.o nv50_display.o nv50_fbcon.o \
23 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ 23 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \
24 nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ 24 nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \
25 nv17_gpio.o 25 nv17_gpio.o nv50_gpio.o
26 26
27nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o 27nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o
28nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o 28nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 0e0730a53137..e13f6af0037a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -1,5 +1,6 @@
1#include <linux/pci.h> 1#include <linux/pci.h>
2#include <linux/acpi.h> 2#include <linux/acpi.h>
3#include <linux/slab.h>
3#include <acpi/acpi_drivers.h> 4#include <acpi/acpi_drivers.h>
4#include <acpi/acpi_bus.h> 5#include <acpi/acpi_bus.h>
5 6
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 75bceee76044..abc382a9918b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -2573,48 +2573,34 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2573 * each GPIO according to various values listed in each entry 2573 * each GPIO according to various values listed in each entry
2574 */ 2574 */
2575 2575
2576 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; 2576 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2577 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 2577 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
2578 const uint8_t *gpio_table = &bios->data[bios->dcb.gpio_table_ptr];
2579 const uint8_t *gpio_entry;
2580 int i; 2578 int i;
2581 2579
2582 if (!iexec->execute) 2580 if (dev_priv->card_type != NV_50) {
2583 return 1; 2581 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
2584 2582 return -ENODEV;
2585 if (bios->dcb.version != 0x40) {
2586 NV_ERROR(bios->dev, "DCB table not version 4.0\n");
2587 return 0;
2588 } 2583 }
2589 2584
2590 if (!bios->dcb.gpio_table_ptr) { 2585 if (!iexec->execute)
2591 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n"); 2586 return 1;
2592 return 0;
2593 }
2594 2587
2595 gpio_entry = gpio_table + gpio_table[1]; 2588 for (i = 0; i < bios->dcb.gpio.entries; i++) {
2596 for (i = 0; i < gpio_table[2]; i++, gpio_entry += gpio_table[3]) { 2589 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
2597 uint32_t entry = ROM32(gpio_entry[0]), r, s, v; 2590 uint32_t r, s, v;
2598 int line = (entry & 0x0000001f);
2599 2591
2600 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, entry); 2592 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
2601 2593
2602 if ((entry & 0x0000ff00) == 0x0000ff00) 2594 nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default);
2603 continue;
2604 2595
2605 r = nv50_gpio_reg[line >> 3]; 2596 /* The NVIDIA binary driver doesn't appear to actually do
2606 s = (line & 0x07) << 2; 2597 * any of this, my VBIOS does however.
2607 v = bios_rd32(bios, r) & ~(0x00000003 << s); 2598 */
2608 if (entry & 0x01000000) 2599 /* Not a clue, needs de-magicing */
2609 v |= (((entry & 0x60000000) >> 29) ^ 2) << s; 2600 r = nv50_gpio_ctl[gpio->line >> 4];
2610 else 2601 s = (gpio->line & 0x0f);
2611 v |= (((entry & 0x18000000) >> 27) ^ 2) << s;
2612 bios_wr32(bios, r, v);
2613
2614 r = nv50_gpio_ctl[line >> 4];
2615 s = (line & 0x0f);
2616 v = bios_rd32(bios, r) & ~(0x00010001 << s); 2602 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2617 switch ((entry & 0x06000000) >> 25) { 2603 switch ((gpio->entry & 0x06000000) >> 25) {
2618 case 1: 2604 case 1:
2619 v |= (0x00000001 << s); 2605 v |= (0x00000001 << s);
2620 break; 2606 break;
@@ -3198,7 +3184,6 @@ static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int
3198 struct nvbios *bios = &dev_priv->vbios; 3184 struct nvbios *bios = &dev_priv->vbios;
3199 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3185 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3200 uint16_t scriptptr = 0, clktable; 3186 uint16_t scriptptr = 0, clktable;
3201 uint8_t clktableptr = 0;
3202 3187
3203 /* 3188 /*
3204 * For now we assume version 3.0 table - g80 support will need some 3189 * For now we assume version 3.0 table - g80 support will need some
@@ -3217,26 +3202,29 @@ static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int
3217 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3202 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3218 break; 3203 break;
3219 case LVDS_RESET: 3204 case LVDS_RESET:
3205 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3206 if (dcbent->or == 4)
3207 clktable += 8;
3208
3220 if (dcbent->lvdsconf.use_straps_for_mode) { 3209 if (dcbent->lvdsconf.use_straps_for_mode) {
3221 if (bios->fp.dual_link) 3210 if (bios->fp.dual_link)
3222 clktableptr += 2; 3211 clktable += 4;
3223 if (bios->fp.BITbit1) 3212 if (bios->fp.if_is_24bit)
3224 clktableptr++; 3213 clktable += 2;
3225 } else { 3214 } else {
3226 /* using EDID */ 3215 /* using EDID */
3227 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 3216 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
3228 int fallbackcmpval = (dcbent->or == 4) ? 4 : 1;
3229 3217
3230 if (bios->fp.dual_link) { 3218 if (bios->fp.dual_link) {
3231 clktableptr += 2; 3219 clktable += 4;
3232 fallbackcmpval *= 2; 3220 cmpval_24bit <<= 1;
3233 } 3221 }
3234 if (fallbackcmpval & fallback) 3222
3235 clktableptr++; 3223 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3224 clktable += 2;
3236 } 3225 }
3237 3226
3238 /* adding outputset * 8 may not be correct */ 3227 clktable = ROM16(bios->data[clktable]);
3239 clktable = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
3240 if (!clktable) { 3228 if (!clktable) {
3241 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3229 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3242 return -ENOENT; 3230 return -ENOENT;
@@ -3638,37 +3626,40 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
3638 *if_is_24bit = bios->data[lvdsofs] & 16; 3626 *if_is_24bit = bios->data[lvdsofs] & 16;
3639 break; 3627 break;
3640 case 0x30: 3628 case 0x30:
3641 /* 3629 case 0x40:
3642 * My money would be on there being a 24 bit interface bit in
3643 * this table, but I have no example of a laptop bios with a
3644 * 24 bit panel to confirm that. Hence we shout loudly if any
3645 * bit other than bit 0 is set (I've not even seen bit 1)
3646 */
3647 if (bios->data[lvdsofs] > 1)
3648 NV_ERROR(dev,
3649 "You have a very unusual laptop display; please report it\n");
3650 /* 3630 /*
3651 * No sign of the "power off for reset" or "reset for panel 3631 * No sign of the "power off for reset" or "reset for panel
3652 * on" bits, but it's safer to assume we should 3632 * on" bits, but it's safer to assume we should
3653 */ 3633 */
3654 bios->fp.power_off_for_reset = true; 3634 bios->fp.power_off_for_reset = true;
3655 bios->fp.reset_after_pclk_change = true; 3635 bios->fp.reset_after_pclk_change = true;
3636
3656 /* 3637 /*
3657 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 3638 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
3658 * over-written, and BITbit1 isn't used 3639 * over-written, and if_is_24bit isn't used
3659 */ 3640 */
3660 bios->fp.dual_link = bios->data[lvdsofs] & 1; 3641 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3661 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
3662 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3663 break;
3664 case 0x40:
3665 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3666 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 3642 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3667 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 3643 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3668 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 3644 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3669 break; 3645 break;
3670 } 3646 }
3671 3647
3648 /* Dell Latitude D620 reports a too-high value for the dual-link
3649 * transition freq, causing us to program the panel incorrectly.
3650 *
3651 * It doesn't appear the VBIOS actually uses its transition freq
3652 * (90000kHz), instead it uses the "Number of LVDS channels" field
3653 * out of the panel ID structure (http://www.spwg.org/).
3654 *
3655 * For the moment, a quirk will do :)
3656 */
3657 if ((dev->pdev->device == 0x01d7) &&
3658 (dev->pdev->subsystem_vendor == 0x1028) &&
3659 (dev->pdev->subsystem_device == 0x01c2)) {
3660 bios->fp.duallink_transition_clk = 80000;
3661 }
3662
3672 /* set dual_link flag for EDID case */ 3663 /* set dual_link flag for EDID case */
3673 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 3664 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3674 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 3665 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
@@ -5077,25 +5068,25 @@ parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5077 gpio->tag = tag; 5068 gpio->tag = tag;
5078 gpio->line = line; 5069 gpio->line = line;
5079 gpio->invert = flags != 4; 5070 gpio->invert = flags != 4;
5071 gpio->entry = ent;
5080} 5072}
5081 5073
5082static void 5074static void
5083parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) 5075parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5084{ 5076{
5077 uint32_t entry = ROM32(bios->data[offset]);
5085 struct dcb_gpio_entry *gpio; 5078 struct dcb_gpio_entry *gpio;
5086 uint32_t ent = ROM32(bios->data[offset]);
5087 uint8_t line = ent & 0x1f,
5088 tag = ent >> 8 & 0xff;
5089 5079
5090 if (tag == 0xff) 5080 if ((entry & 0x0000ff00) == 0x0000ff00)
5091 return; 5081 return;
5092 5082
5093 gpio = new_gpio_entry(bios); 5083 gpio = new_gpio_entry(bios);
5094 5084 gpio->tag = (entry & 0x0000ff00) >> 8;
5095 /* Currently unused, we may need more fields parsed at some 5085 gpio->line = (entry & 0x0000001f) >> 0;
5096 * point. */ 5086 gpio->state_default = (entry & 0x01000000) >> 24;
5097 gpio->tag = tag; 5087 gpio->state[0] = (entry & 0x18000000) >> 27;
5098 gpio->line = line; 5088 gpio->state[1] = (entry & 0x60000000) >> 29;
5089 gpio->entry = entry;
5099} 5090}
5100 5091
5101static void 5092static void
@@ -5211,6 +5202,21 @@ divine_connector_type(struct nvbios *bios, int index)
5211} 5202}
5212 5203
5213static void 5204static void
5205apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5206{
5207 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5208 struct drm_device *dev = bios->dev;
5209
5210 /* Gigabyte NX85T */
5211 if ((dev->pdev->device == 0x0421) &&
5212 (dev->pdev->subsystem_vendor == 0x1458) &&
5213 (dev->pdev->subsystem_device == 0x344c)) {
5214 if (cte->type == DCB_CONNECTOR_HDMI_1)
5215 cte->type = DCB_CONNECTOR_DVI_I;
5216 }
5217}
5218
5219static void
5214parse_dcb_connector_table(struct nvbios *bios) 5220parse_dcb_connector_table(struct nvbios *bios)
5215{ 5221{
5216 struct drm_device *dev = bios->dev; 5222 struct drm_device *dev = bios->dev;
@@ -5238,13 +5244,14 @@ parse_dcb_connector_table(struct nvbios *bios)
5238 entry = conntab + conntab[1]; 5244 entry = conntab + conntab[1];
5239 cte = &ct->entry[0]; 5245 cte = &ct->entry[0];
5240 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) { 5246 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
5247 cte->index = i;
5241 if (conntab[3] == 2) 5248 if (conntab[3] == 2)
5242 cte->entry = ROM16(entry[0]); 5249 cte->entry = ROM16(entry[0]);
5243 else 5250 else
5244 cte->entry = ROM32(entry[0]); 5251 cte->entry = ROM32(entry[0]);
5245 5252
5246 cte->type = (cte->entry & 0x000000ff) >> 0; 5253 cte->type = (cte->entry & 0x000000ff) >> 0;
5247 cte->index = (cte->entry & 0x00000f00) >> 8; 5254 cte->index2 = (cte->entry & 0x00000f00) >> 8;
5248 switch (cte->entry & 0x00033000) { 5255 switch (cte->entry & 0x00033000) {
5249 case 0x00001000: 5256 case 0x00001000:
5250 cte->gpio_tag = 0x07; 5257 cte->gpio_tag = 0x07;
@@ -5266,6 +5273,8 @@ parse_dcb_connector_table(struct nvbios *bios)
5266 if (cte->type == 0xff) 5273 if (cte->type == 0xff)
5267 continue; 5274 continue;
5268 5275
5276 apply_dcb_connector_quirks(bios, i);
5277
5269 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", 5278 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5270 i, cte->entry, cte->type, cte->index, cte->gpio_tag); 5279 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
5271 5280
@@ -5287,10 +5296,16 @@ parse_dcb_connector_table(struct nvbios *bios)
5287 break; 5296 break;
5288 default: 5297 default:
5289 cte->type = divine_connector_type(bios, cte->index); 5298 cte->type = divine_connector_type(bios, cte->index);
5290 NV_WARN(dev, "unknown type, using 0x%02x", cte->type); 5299 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
5291 break; 5300 break;
5292 } 5301 }
5293 5302
5303 if (nouveau_override_conntype) {
5304 int type = divine_connector_type(bios, cte->index);
5305 if (type != cte->type)
5306 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
5307 }
5308
5294 } 5309 }
5295} 5310}
5296 5311
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 9f688aa9a655..c0d7b0a3ece0 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -49,6 +49,9 @@ struct dcb_gpio_entry {
49 enum dcb_gpio_tag tag; 49 enum dcb_gpio_tag tag;
50 int line; 50 int line;
51 bool invert; 51 bool invert;
52 uint32_t entry;
53 uint8_t state_default;
54 uint8_t state[2];
52}; 55};
53 56
54struct dcb_gpio_table { 57struct dcb_gpio_table {
@@ -72,9 +75,10 @@ enum dcb_connector_type {
72}; 75};
73 76
74struct dcb_connector_table_entry { 77struct dcb_connector_table_entry {
78 uint8_t index;
75 uint32_t entry; 79 uint32_t entry;
76 enum dcb_connector_type type; 80 enum dcb_connector_type type;
77 uint8_t index; 81 uint8_t index2;
78 uint8_t gpio_tag; 82 uint8_t gpio_tag;
79}; 83};
80 84
@@ -266,7 +270,6 @@ struct nvbios {
266 bool reset_after_pclk_change; 270 bool reset_after_pclk_change;
267 bool dual_link; 271 bool dual_link;
268 bool link_c_increment; 272 bool link_c_increment;
269 bool BITbit1;
270 bool if_is_24bit; 273 bool if_is_24bit;
271 int duallink_transition_clk; 274 int duallink_transition_clk;
272 uint8_t strapless_is_24bit; 275 uint8_t strapless_is_24bit;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 028719fddf76..957d17629840 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -34,6 +34,7 @@
34#include "nouveau_dma.h" 34#include "nouveau_dma.h"
35 35
36#include <linux/log2.h> 36#include <linux/log2.h>
37#include <linux/slab.h>
37 38
38static void 39static void
39nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 40nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
@@ -71,7 +72,7 @@ nouveau_bo_fixup_align(struct drm_device *dev,
71 * many small buffers. 72 * many small buffers.
72 */ 73 */
73 if (dev_priv->card_type == NV_50) { 74 if (dev_priv->card_type == NV_50) {
74 uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15; 75 uint32_t block_size = dev_priv->vram_size >> 15;
75 int i; 76 int i;
76 77
77 switch (tile_flags) { 78 switch (tile_flags) {
@@ -153,7 +154,7 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
153 154
154 nvbo->placement.fpfn = 0; 155 nvbo->placement.fpfn = 0;
155 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; 156 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
156 nouveau_bo_placement_set(nvbo, flags); 157 nouveau_bo_placement_set(nvbo, flags, 0);
157 158
158 nvbo->channel = chan; 159 nvbo->channel = chan;
159 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, 160 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
@@ -172,26 +173,33 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
172 return 0; 173 return 0;
173} 174}
174 175
176static void
177set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
178{
179 *n = 0;
180
181 if (type & TTM_PL_FLAG_VRAM)
182 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
183 if (type & TTM_PL_FLAG_TT)
184 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
185 if (type & TTM_PL_FLAG_SYSTEM)
186 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
187}
188
175void 189void
176nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype) 190nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
177{ 191{
178 int n = 0; 192 struct ttm_placement *pl = &nvbo->placement;
179 193 uint32_t flags = TTM_PL_MASK_CACHING |
180 if (memtype & TTM_PL_FLAG_VRAM) 194 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
181 nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING; 195
182 if (memtype & TTM_PL_FLAG_TT) 196 pl->placement = nvbo->placements;
183 nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; 197 set_placement_list(nvbo->placements, &pl->num_placement,
184 if (memtype & TTM_PL_FLAG_SYSTEM) 198 type, flags);
185 nvbo->placements[n++] = TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; 199
186 nvbo->placement.placement = nvbo->placements; 200 pl->busy_placement = nvbo->busy_placements;
187 nvbo->placement.busy_placement = nvbo->placements; 201 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
188 nvbo->placement.num_placement = n; 202 type | busy, flags);
189 nvbo->placement.num_busy_placement = n;
190
191 if (nvbo->pin_refcnt) {
192 while (n--)
193 nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT;
194 }
195} 203}
196 204
197int 205int
@@ -199,7 +207,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
199{ 207{
200 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); 208 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
201 struct ttm_buffer_object *bo = &nvbo->bo; 209 struct ttm_buffer_object *bo = &nvbo->bo;
202 int ret, i; 210 int ret;
203 211
204 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { 212 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
205 NV_ERROR(nouveau_bdev(bo->bdev)->dev, 213 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
@@ -215,9 +223,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
215 if (ret) 223 if (ret)
216 goto out; 224 goto out;
217 225
218 nouveau_bo_placement_set(nvbo, memtype); 226 nouveau_bo_placement_set(nvbo, memtype, 0);
219 for (i = 0; i < nvbo->placement.num_placement; i++)
220 nvbo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
221 227
222 ret = ttm_bo_validate(bo, &nvbo->placement, false, false); 228 ret = ttm_bo_validate(bo, &nvbo->placement, false, false);
223 if (ret == 0) { 229 if (ret == 0) {
@@ -244,7 +250,7 @@ nouveau_bo_unpin(struct nouveau_bo *nvbo)
244{ 250{
245 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); 251 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
246 struct ttm_buffer_object *bo = &nvbo->bo; 252 struct ttm_buffer_object *bo = &nvbo->bo;
247 int ret, i; 253 int ret;
248 254
249 if (--nvbo->pin_refcnt) 255 if (--nvbo->pin_refcnt)
250 return 0; 256 return 0;
@@ -253,8 +259,7 @@ nouveau_bo_unpin(struct nouveau_bo *nvbo)
253 if (ret) 259 if (ret)
254 return ret; 260 return ret;
255 261
256 for (i = 0; i < nvbo->placement.num_placement; i++) 262 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
257 nvbo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
258 263
259 ret = ttm_bo_validate(bo, &nvbo->placement, false, false); 264 ret = ttm_bo_validate(bo, &nvbo->placement, false, false);
260 if (ret == 0) { 265 if (ret == 0) {
@@ -395,8 +400,8 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
395 man->io_addr = NULL; 400 man->io_addr = NULL;
396 man->io_offset = drm_get_resource_start(dev, 1); 401 man->io_offset = drm_get_resource_start(dev, 1);
397 man->io_size = drm_get_resource_len(dev, 1); 402 man->io_size = drm_get_resource_len(dev, 1);
398 if (man->io_size > nouveau_mem_fb_amount(dev)) 403 if (man->io_size > dev_priv->vram_size)
399 man->io_size = nouveau_mem_fb_amount(dev); 404 man->io_size = dev_priv->vram_size;
400 405
401 man->gpu_offset = dev_priv->vm_vram_base; 406 man->gpu_offset = dev_priv->vm_vram_base;
402 break; 407 break;
@@ -439,11 +444,11 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
439 444
440 switch (bo->mem.mem_type) { 445 switch (bo->mem.mem_type) {
441 case TTM_PL_VRAM: 446 case TTM_PL_VRAM:
442 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT | 447 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
443 TTM_PL_FLAG_SYSTEM); 448 TTM_PL_FLAG_SYSTEM);
444 break; 449 break;
445 default: 450 default:
446 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM); 451 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
447 break; 452 break;
448 } 453 }
449 454
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 6dfb425cbae9..1fc57ef58295 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -142,7 +142,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
142 GFP_KERNEL); 142 GFP_KERNEL);
143 if (!dev_priv->fifos[channel]) 143 if (!dev_priv->fifos[channel])
144 return -ENOMEM; 144 return -ENOMEM;
145 dev_priv->fifo_alloc_count++;
146 chan = dev_priv->fifos[channel]; 145 chan = dev_priv->fifos[channel];
147 INIT_LIST_HEAD(&chan->nvsw.vbl_wait); 146 INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
148 INIT_LIST_HEAD(&chan->fence.pending); 147 INIT_LIST_HEAD(&chan->fence.pending);
@@ -321,7 +320,6 @@ nouveau_channel_free(struct nouveau_channel *chan)
321 iounmap(chan->user); 320 iounmap(chan->user);
322 321
323 dev_priv->fifos[chan->id] = NULL; 322 dev_priv->fifos[chan->id] = NULL;
324 dev_priv->fifo_alloc_count--;
325 kfree(chan); 323 kfree(chan);
326} 324}
327 325
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 24327f468c4b..14afe1e47e57 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -302,7 +302,7 @@ nouveau_connector_detect(struct drm_connector *connector)
302 302
303detect_analog: 303detect_analog:
304 nv_encoder = find_encoder_by_type(connector, OUTPUT_ANALOG); 304 nv_encoder = find_encoder_by_type(connector, OUTPUT_ANALOG);
305 if (!nv_encoder) 305 if (!nv_encoder && !nouveau_tv_disable)
306 nv_encoder = find_encoder_by_type(connector, OUTPUT_TV); 306 nv_encoder = find_encoder_by_type(connector, OUTPUT_TV);
307 if (nv_encoder) { 307 if (nv_encoder) {
308 struct drm_encoder *encoder = to_drm_encoder(nv_encoder); 308 struct drm_encoder *encoder = to_drm_encoder(nv_encoder);
diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c
index 8ff9ef5d4b47..a251886a0ce6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c
+++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c
@@ -137,10 +137,9 @@ nouveau_debugfs_memory_info(struct seq_file *m, void *data)
137{ 137{
138 struct drm_info_node *node = (struct drm_info_node *) m->private; 138 struct drm_info_node *node = (struct drm_info_node *) m->private;
139 struct drm_minor *minor = node->minor; 139 struct drm_minor *minor = node->minor;
140 struct drm_device *dev = minor->dev; 140 struct drm_nouveau_private *dev_priv = minor->dev->dev_private;
141 141
142 seq_printf(m, "VRAM total: %dKiB\n", 142 seq_printf(m, "VRAM total: %dKiB\n", (int)(dev_priv->vram_size >> 10));
143 (int)(nouveau_mem_fb_amount(dev) >> 10));
144 return 0; 143 return 0;
145} 144}
146 145
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
index c8482a108a78..65c441a1999f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -190,6 +190,11 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
190 nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8); 190 nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
191 191
192 chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max; 192 chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
193
194 DRM_MEMORYBARRIER();
195 /* Flush writes. */
196 nouveau_bo_rd32(pb, 0);
197
193 nvchan_wr32(chan, 0x8c, chan->dma.ib_put); 198 nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
194 chan->dma.ib_free--; 199 chan->dma.ib_free--;
195} 200}
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index f954ad93e81f..deeb21c6865c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -483,7 +483,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
483 ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT); 483 ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT);
484 ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT); 484 ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT);
485 485
486 for (;;) { 486 for (i = 0; i < 16; i++) {
487 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000); 487 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000);
488 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl); 488 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl);
489 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000); 489 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000);
@@ -502,6 +502,12 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
502 break; 502 break;
503 } 503 }
504 504
505 if (i == 16) {
506 NV_ERROR(dev, "auxch DEFER too many times, bailing\n");
507 ret = -EREMOTEIO;
508 goto out;
509 }
510
505 if (cmd & 1) { 511 if (cmd & 1) {
506 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) { 512 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
507 ret = -EREMOTEIO; 513 ret = -EREMOTEIO;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index 30cc09e8a709..1de974acbc65 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -83,6 +83,14 @@ MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
83int nouveau_nofbaccel = 0; 83int nouveau_nofbaccel = 0;
84module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400); 84module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
85 85
86MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
87int nouveau_override_conntype = 0;
88module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
89
90MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
91int nouveau_tv_disable = 0;
92module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
93
86MODULE_PARM_DESC(tv_norm, "Default TV norm.\n" 94MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
87 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n" 95 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
88 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n" 96 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
@@ -154,9 +162,11 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
154 if (pm_state.event == PM_EVENT_PRETHAW) 162 if (pm_state.event == PM_EVENT_PRETHAW)
155 return 0; 163 return 0;
156 164
165 NV_INFO(dev, "Disabling fbcon acceleration...\n");
157 fbdev_flags = dev_priv->fbdev_info->flags; 166 fbdev_flags = dev_priv->fbdev_info->flags;
158 dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED; 167 dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
159 168
169 NV_INFO(dev, "Unpinning framebuffer(s)...\n");
160 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 170 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
161 struct nouveau_framebuffer *nouveau_fb; 171 struct nouveau_framebuffer *nouveau_fb;
162 172
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 4b9aaf2a8d0f..ace630aa89e1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -76,6 +76,7 @@ struct nouveau_bo {
76 struct ttm_buffer_object bo; 76 struct ttm_buffer_object bo;
77 struct ttm_placement placement; 77 struct ttm_placement placement;
78 u32 placements[3]; 78 u32 placements[3];
79 u32 busy_placements[3];
79 struct ttm_bo_kmap_obj kmap; 80 struct ttm_bo_kmap_obj kmap;
80 struct list_head head; 81 struct list_head head;
81 82
@@ -519,6 +520,7 @@ struct drm_nouveau_private {
519 520
520 struct workqueue_struct *wq; 521 struct workqueue_struct *wq;
521 struct work_struct irq_work; 522 struct work_struct irq_work;
523 struct work_struct hpd_work;
522 524
523 struct list_head vbl_waiting; 525 struct list_head vbl_waiting;
524 526
@@ -533,7 +535,6 @@ struct drm_nouveau_private {
533 535
534 struct fb_info *fbdev_info; 536 struct fb_info *fbdev_info;
535 537
536 int fifo_alloc_count;
537 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 538 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
538 539
539 struct nouveau_engine engine; 540 struct nouveau_engine engine;
@@ -553,12 +554,6 @@ struct drm_nouveau_private {
553 uint32_t ramro_offset; 554 uint32_t ramro_offset;
554 uint32_t ramro_size; 555 uint32_t ramro_size;
555 556
556 /* base physical addresses */
557 uint64_t fb_phys;
558 uint64_t fb_available_size;
559 uint64_t fb_mappable_pages;
560 uint64_t fb_aper_free;
561
562 struct { 557 struct {
563 enum { 558 enum {
564 NOUVEAU_GART_NONE = 0, 559 NOUVEAU_GART_NONE = 0,
@@ -572,10 +567,6 @@ struct drm_nouveau_private {
572 struct nouveau_gpuobj *sg_ctxdma; 567 struct nouveau_gpuobj *sg_ctxdma;
573 struct page *sg_dummy_page; 568 struct page *sg_dummy_page;
574 dma_addr_t sg_dummy_bus; 569 dma_addr_t sg_dummy_bus;
575
576 /* nottm hack */
577 struct drm_ttm_backend *sg_be;
578 unsigned long sg_handle;
579 } gart_info; 570 } gart_info;
580 571
581 /* nv10-nv40 tiling regions */ 572 /* nv10-nv40 tiling regions */
@@ -584,6 +575,16 @@ struct drm_nouveau_private {
584 spinlock_t lock; 575 spinlock_t lock;
585 } tile; 576 } tile;
586 577
578 /* VRAM/fb configuration */
579 uint64_t vram_size;
580 uint64_t vram_sys_base;
581
582 uint64_t fb_phys;
583 uint64_t fb_available_size;
584 uint64_t fb_mappable_pages;
585 uint64_t fb_aper_free;
586 int fb_mtrr;
587
587 /* G8x/G9x virtual address space */ 588 /* G8x/G9x virtual address space */
588 uint64_t vm_gart_base; 589 uint64_t vm_gart_base;
589 uint64_t vm_gart_size; 590 uint64_t vm_gart_size;
@@ -592,10 +593,6 @@ struct drm_nouveau_private {
592 uint64_t vm_end; 593 uint64_t vm_end;
593 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 594 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
594 int vm_vram_pt_nr; 595 int vm_vram_pt_nr;
595 uint64_t vram_sys_base;
596
597 /* the mtrr covering the FB */
598 int fb_mtrr;
599 596
600 struct mem_block *ramin_heap; 597 struct mem_block *ramin_heap;
601 598
@@ -614,11 +611,7 @@ struct drm_nouveau_private {
614 uint32_t dac_users[4]; 611 uint32_t dac_users[4];
615 612
616 struct nouveau_suspend_resume { 613 struct nouveau_suspend_resume {
617 uint32_t fifo_mode;
618 uint32_t graph_ctx_control;
619 uint32_t graph_state;
620 uint32_t *ramin_copy; 614 uint32_t *ramin_copy;
621 uint64_t ramin_size;
622 } susres; 615 } susres;
623 616
624 struct backlight_device *backlight; 617 struct backlight_device *backlight;
@@ -681,6 +674,7 @@ extern int nouveau_uscript_tmds;
681extern int nouveau_vram_pushbuf; 674extern int nouveau_vram_pushbuf;
682extern int nouveau_vram_notify; 675extern int nouveau_vram_notify;
683extern int nouveau_fbpercrtc; 676extern int nouveau_fbpercrtc;
677extern int nouveau_tv_disable;
684extern char *nouveau_tv_norm; 678extern char *nouveau_tv_norm;
685extern int nouveau_reg_debug; 679extern int nouveau_reg_debug;
686extern char *nouveau_vbios; 680extern char *nouveau_vbios;
@@ -688,6 +682,7 @@ extern int nouveau_ctxfw;
688extern int nouveau_ignorelid; 682extern int nouveau_ignorelid;
689extern int nouveau_nofbaccel; 683extern int nouveau_nofbaccel;
690extern int nouveau_noaccel; 684extern int nouveau_noaccel;
685extern int nouveau_override_conntype;
691 686
692extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 687extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
693extern int nouveau_pci_resume(struct pci_dev *pdev); 688extern int nouveau_pci_resume(struct pci_dev *pdev);
@@ -715,7 +710,7 @@ extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
715 struct drm_file *, int tail); 710 struct drm_file *, int tail);
716extern void nouveau_mem_takedown(struct mem_block **heap); 711extern void nouveau_mem_takedown(struct mem_block **heap);
717extern void nouveau_mem_free_block(struct mem_block *); 712extern void nouveau_mem_free_block(struct mem_block *);
718extern uint64_t nouveau_mem_fb_amount(struct drm_device *); 713extern int nouveau_mem_detect(struct drm_device *dev);
719extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); 714extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
720extern int nouveau_mem_init(struct drm_device *); 715extern int nouveau_mem_init(struct drm_device *);
721extern int nouveau_mem_init_agp(struct drm_device *); 716extern int nouveau_mem_init_agp(struct drm_device *);
@@ -926,6 +921,10 @@ extern void nv40_fb_takedown(struct drm_device *);
926extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 921extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
927 uint32_t, uint32_t); 922 uint32_t, uint32_t);
928 923
924/* nv50_fb.c */
925extern int nv50_fb_init(struct drm_device *);
926extern void nv50_fb_takedown(struct drm_device *);
927
929/* nv04_fifo.c */ 928/* nv04_fifo.c */
930extern int nv04_fifo_init(struct drm_device *); 929extern int nv04_fifo_init(struct drm_device *);
931extern void nv04_fifo_disable(struct drm_device *); 930extern void nv04_fifo_disable(struct drm_device *);
@@ -1118,7 +1117,8 @@ extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1118extern int nouveau_bo_unpin(struct nouveau_bo *); 1117extern int nouveau_bo_unpin(struct nouveau_bo *);
1119extern int nouveau_bo_map(struct nouveau_bo *); 1118extern int nouveau_bo_map(struct nouveau_bo *);
1120extern void nouveau_bo_unmap(struct nouveau_bo *); 1119extern void nouveau_bo_unmap(struct nouveau_bo *);
1121extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype); 1120extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1121 uint32_t busy);
1122extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1122extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1123extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1123extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1124extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1124extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
@@ -1162,6 +1162,10 @@ extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1162int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1162int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1163int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1163int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1164 1164
1165/* nv50_gpio.c */
1166int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1167int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1168
1165#ifndef ioread32_native 1169#ifndef ioread32_native
1166#ifdef __BIG_ENDIAN 1170#ifdef __BIG_ENDIAN
1167#define ioread16_native ioread16be 1171#define ioread16_native ioread16be
diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index bc4a24029ed1..9f28b94e479b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -47,6 +47,7 @@ struct nouveau_encoder {
47 47
48 union { 48 union {
49 struct { 49 struct {
50 int mc_unknown;
50 int dpcd_version; 51 int dpcd_version;
51 int link_nr; 52 int link_nr;
52 int link_bw; 53 int link_bw;
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 68cedd9194fe..8e7dc1d4912a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -30,7 +30,6 @@
30#include <linux/string.h> 30#include <linux/string.h>
31#include <linux/mm.h> 31#include <linux/mm.h>
32#include <linux/tty.h> 32#include <linux/tty.h>
33#include <linux/slab.h>
34#include <linux/sysrq.h> 33#include <linux/sysrq.h>
35#include <linux/delay.h> 34#include <linux/delay.h>
36#include <linux/fb.h> 35#include <linux/fb.h>
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 0d22f66f1c79..1bc0b38a5167 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -180,40 +180,35 @@ nouveau_gem_set_domain(struct drm_gem_object *gem, uint32_t read_domains,
180{ 180{
181 struct nouveau_bo *nvbo = gem->driver_private; 181 struct nouveau_bo *nvbo = gem->driver_private;
182 struct ttm_buffer_object *bo = &nvbo->bo; 182 struct ttm_buffer_object *bo = &nvbo->bo;
183 uint64_t flags; 183 uint32_t domains = valid_domains &
184 (write_domains ? write_domains : read_domains);
185 uint32_t pref_flags = 0, valid_flags = 0;
184 186
185 if (!valid_domains || (!read_domains && !write_domains)) 187 if (!domains)
186 return -EINVAL; 188 return -EINVAL;
187 189
188 if (write_domains) { 190 if (valid_domains & NOUVEAU_GEM_DOMAIN_VRAM)
189 if ((valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) && 191 valid_flags |= TTM_PL_FLAG_VRAM;
190 (write_domains & NOUVEAU_GEM_DOMAIN_VRAM)) 192
191 flags = TTM_PL_FLAG_VRAM; 193 if (valid_domains & NOUVEAU_GEM_DOMAIN_GART)
192 else 194 valid_flags |= TTM_PL_FLAG_TT;
193 if ((valid_domains & NOUVEAU_GEM_DOMAIN_GART) && 195
194 (write_domains & NOUVEAU_GEM_DOMAIN_GART)) 196 if ((domains & NOUVEAU_GEM_DOMAIN_VRAM) &&
195 flags = TTM_PL_FLAG_TT; 197 bo->mem.mem_type == TTM_PL_VRAM)
196 else 198 pref_flags |= TTM_PL_FLAG_VRAM;
197 return -EINVAL; 199
198 } else { 200 else if ((domains & NOUVEAU_GEM_DOMAIN_GART) &&
199 if ((valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) && 201 bo->mem.mem_type == TTM_PL_TT)
200 (read_domains & NOUVEAU_GEM_DOMAIN_VRAM) && 202 pref_flags |= TTM_PL_FLAG_TT;
201 bo->mem.mem_type == TTM_PL_VRAM) 203
202 flags = TTM_PL_FLAG_VRAM; 204 else if (domains & NOUVEAU_GEM_DOMAIN_VRAM)
203 else 205 pref_flags |= TTM_PL_FLAG_VRAM;
204 if ((valid_domains & NOUVEAU_GEM_DOMAIN_GART) && 206
205 (read_domains & NOUVEAU_GEM_DOMAIN_GART) && 207 else
206 bo->mem.mem_type == TTM_PL_TT) 208 pref_flags |= TTM_PL_FLAG_TT;
207 flags = TTM_PL_FLAG_TT; 209
208 else 210 nouveau_bo_placement_set(nvbo, pref_flags, valid_flags);
209 if ((valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) &&
210 (read_domains & NOUVEAU_GEM_DOMAIN_VRAM))
211 flags = TTM_PL_FLAG_VRAM;
212 else
213 flags = TTM_PL_FLAG_TT;
214 }
215 211
216 nouveau_bo_placement_set(nvbo, flags);
217 return 0; 212 return 0;
218} 213}
219 214
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.c b/drivers/gpu/drm/nouveau/nouveau_grctx.c
index c7ebec696747..32f0e495464c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_grctx.c
+++ b/drivers/gpu/drm/nouveau/nouveau_grctx.c
@@ -23,6 +23,7 @@
23 */ 23 */
24 24
25#include <linux/firmware.h> 25#include <linux/firmware.h>
26#include <linux/slab.h>
26 27
27#include "drmP.h" 28#include "drmP.h"
28#include "nouveau_drv.h" 29#include "nouveau_drv.h"
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 95220ddebb45..13e73cee4c44 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -51,6 +51,7 @@ nouveau_irq_preinstall(struct drm_device *dev)
51 51
52 if (dev_priv->card_type == NV_50) { 52 if (dev_priv->card_type == NV_50) {
53 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh); 53 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
54 INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
54 INIT_LIST_HEAD(&dev_priv->vbl_waiting); 55 INIT_LIST_HEAD(&dev_priv->vbl_waiting);
55 } 56 }
56} 57}
@@ -311,6 +312,31 @@ nouveau_print_bitfield_names_(uint32_t value,
311#define nouveau_print_bitfield_names(val, namelist) \ 312#define nouveau_print_bitfield_names(val, namelist) \
312 nouveau_print_bitfield_names_((val), (namelist), ARRAY_SIZE(namelist)) 313 nouveau_print_bitfield_names_((val), (namelist), ARRAY_SIZE(namelist))
313 314
315struct nouveau_enum_names {
316 uint32_t value;
317 const char *name;
318};
319
320static void
321nouveau_print_enum_names_(uint32_t value,
322 const struct nouveau_enum_names *namelist,
323 const int namelist_len)
324{
325 /*
326 * Caller must have already printed the KERN_* log level for us.
327 * Also the caller is responsible for adding the newline.
328 */
329 int i;
330 for (i = 0; i < namelist_len; ++i) {
331 if (value == namelist[i].value) {
332 printk("%s", namelist[i].name);
333 return;
334 }
335 }
336 printk("unknown value 0x%08x", value);
337}
338#define nouveau_print_enum_names(val, namelist) \
339 nouveau_print_enum_names_((val), (namelist), ARRAY_SIZE(namelist))
314 340
315static int 341static int
316nouveau_graph_chid_from_grctx(struct drm_device *dev) 342nouveau_graph_chid_from_grctx(struct drm_device *dev)
@@ -427,14 +453,16 @@ nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
427 struct drm_nouveau_private *dev_priv = dev->dev_private; 453 struct drm_nouveau_private *dev_priv = dev->dev_private;
428 uint32_t nsource = trap->nsource, nstatus = trap->nstatus; 454 uint32_t nsource = trap->nsource, nstatus = trap->nstatus;
429 455
430 NV_INFO(dev, "%s - nSource:", id); 456 if (dev_priv->card_type < NV_50) {
431 nouveau_print_bitfield_names(nsource, nsource_names); 457 NV_INFO(dev, "%s - nSource:", id);
432 printk(", nStatus:"); 458 nouveau_print_bitfield_names(nsource, nsource_names);
433 if (dev_priv->card_type < NV_10) 459 printk(", nStatus:");
434 nouveau_print_bitfield_names(nstatus, nstatus_names); 460 if (dev_priv->card_type < NV_10)
435 else 461 nouveau_print_bitfield_names(nstatus, nstatus_names);
436 nouveau_print_bitfield_names(nstatus, nstatus_names_nv10); 462 else
437 printk("\n"); 463 nouveau_print_bitfield_names(nstatus, nstatus_names_nv10);
464 printk("\n");
465 }
438 466
439 NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x " 467 NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x "
440 "Data 0x%08x:0x%08x\n", 468 "Data 0x%08x:0x%08x\n",
@@ -578,27 +606,502 @@ nouveau_pgraph_irq_handler(struct drm_device *dev)
578} 606}
579 607
580static void 608static void
609nv50_pfb_vm_trap(struct drm_device *dev, int display, const char *name)
610{
611 struct drm_nouveau_private *dev_priv = dev->dev_private;
612 uint32_t trap[6];
613 int i, ch;
614 uint32_t idx = nv_rd32(dev, 0x100c90);
615 if (idx & 0x80000000) {
616 idx &= 0xffffff;
617 if (display) {
618 for (i = 0; i < 6; i++) {
619 nv_wr32(dev, 0x100c90, idx | i << 24);
620 trap[i] = nv_rd32(dev, 0x100c94);
621 }
622 for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
623 struct nouveau_channel *chan = dev_priv->fifos[ch];
624
625 if (!chan || !chan->ramin)
626 continue;
627
628 if (trap[1] == chan->ramin->instance >> 12)
629 break;
630 }
631 NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x %08x channel %d\n",
632 name, (trap[5]&0x100?"read":"write"),
633 trap[5]&0xff, trap[4]&0xffff,
634 trap[3]&0xffff, trap[0], trap[2], ch);
635 }
636 nv_wr32(dev, 0x100c90, idx | 0x80000000);
637 } else if (display) {
638 NV_INFO(dev, "%s - no VM fault?\n", name);
639 }
640}
641
642static struct nouveau_enum_names nv50_mp_exec_error_names[] =
643{
644 { 3, "STACK_UNDERFLOW" },
645 { 4, "QUADON_ACTIVE" },
646 { 8, "TIMEOUT" },
647 { 0x10, "INVALID_OPCODE" },
648 { 0x40, "BREAKPOINT" },
649};
650
651static void
652nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
653{
654 struct drm_nouveau_private *dev_priv = dev->dev_private;
655 uint32_t units = nv_rd32(dev, 0x1540);
656 uint32_t addr, mp10, status, pc, oplow, ophigh;
657 int i;
658 int mps = 0;
659 for (i = 0; i < 4; i++) {
660 if (!(units & 1 << (i+24)))
661 continue;
662 if (dev_priv->chipset < 0xa0)
663 addr = 0x408200 + (tpid << 12) + (i << 7);
664 else
665 addr = 0x408100 + (tpid << 11) + (i << 7);
666 mp10 = nv_rd32(dev, addr + 0x10);
667 status = nv_rd32(dev, addr + 0x14);
668 if (!status)
669 continue;
670 if (display) {
671 nv_rd32(dev, addr + 0x20);
672 pc = nv_rd32(dev, addr + 0x24);
673 oplow = nv_rd32(dev, addr + 0x70);
674 ophigh= nv_rd32(dev, addr + 0x74);
675 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
676 "TP %d MP %d: ", tpid, i);
677 nouveau_print_enum_names(status,
678 nv50_mp_exec_error_names);
679 printk(" at %06x warp %d, opcode %08x %08x\n",
680 pc&0xffffff, pc >> 24,
681 oplow, ophigh);
682 }
683 nv_wr32(dev, addr + 0x10, mp10);
684 nv_wr32(dev, addr + 0x14, 0);
685 mps++;
686 }
687 if (!mps && display)
688 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
689 "No MPs claiming errors?\n", tpid);
690}
691
692static void
693nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
694 uint32_t ustatus_new, int display, const char *name)
695{
696 struct drm_nouveau_private *dev_priv = dev->dev_private;
697 int tps = 0;
698 uint32_t units = nv_rd32(dev, 0x1540);
699 int i, r;
700 uint32_t ustatus_addr, ustatus;
701 for (i = 0; i < 16; i++) {
702 if (!(units & (1 << i)))
703 continue;
704 if (dev_priv->chipset < 0xa0)
705 ustatus_addr = ustatus_old + (i << 12);
706 else
707 ustatus_addr = ustatus_new + (i << 11);
708 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
709 if (!ustatus)
710 continue;
711 tps++;
712 switch (type) {
713 case 6: /* texture error... unknown for now */
714 nv50_pfb_vm_trap(dev, display, name);
715 if (display) {
716 NV_ERROR(dev, "magic set %d:\n", i);
717 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
718 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
719 nv_rd32(dev, r));
720 }
721 break;
722 case 7: /* MP error */
723 if (ustatus & 0x00010000) {
724 nv50_pgraph_mp_trap(dev, i, display);
725 ustatus &= ~0x00010000;
726 }
727 break;
728 case 8: /* TPDMA error */
729 {
730 uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
731 uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
732 uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
733 uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
734 uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
735 uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
736 uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
737 nv50_pfb_vm_trap(dev, display, name);
738 /* 2d engine destination */
739 if (ustatus & 0x00000010) {
740 if (display) {
741 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
742 i, e14, e10);
743 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
744 i, e0c, e18, e1c, e20, e24);
745 }
746 ustatus &= ~0x00000010;
747 }
748 /* Render target */
749 if (ustatus & 0x00000040) {
750 if (display) {
751 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
752 i, e14, e10);
753 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
754 i, e0c, e18, e1c, e20, e24);
755 }
756 ustatus &= ~0x00000040;
757 }
758 /* CUDA memory: l[], g[] or stack. */
759 if (ustatus & 0x00000080) {
760 if (display) {
761 if (e18 & 0x80000000) {
762 /* g[] read fault? */
763 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
764 i, e14, e10 | ((e18 >> 24) & 0x1f));
765 e18 &= ~0x1f000000;
766 } else if (e18 & 0xc) {
767 /* g[] write fault? */
768 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
769 i, e14, e10 | ((e18 >> 7) & 0x1f));
770 e18 &= ~0x00000f80;
771 } else {
772 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
773 i, e14, e10);
774 }
775 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
776 i, e0c, e18, e1c, e20, e24);
777 }
778 ustatus &= ~0x00000080;
779 }
780 }
781 break;
782 }
783 if (ustatus) {
784 if (display)
785 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
786 }
787 nv_wr32(dev, ustatus_addr, 0xc0000000);
788 }
789
790 if (!tps && display)
791 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
792}
793
794static void
795nv50_pgraph_trap_handler(struct drm_device *dev)
796{
797 struct nouveau_pgraph_trap trap;
798 uint32_t status = nv_rd32(dev, 0x400108);
799 uint32_t ustatus;
800 int display = nouveau_ratelimit();
801
802
803 if (!status && display) {
804 nouveau_graph_trap_info(dev, &trap);
805 nouveau_graph_dump_trap_info(dev, "PGRAPH_TRAP", &trap);
806 NV_INFO(dev, "PGRAPH_TRAP - no units reporting traps?\n");
807 }
808
809 /* DISPATCH: Relays commands to other units and handles NOTIFY,
810 * COND, QUERY. If you get a trap from it, the command is still stuck
811 * in DISPATCH and you need to do something about it. */
812 if (status & 0x001) {
813 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
814 if (!ustatus && display) {
815 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
816 }
817
818 /* Known to be triggered by screwed up NOTIFY and COND... */
819 if (ustatus & 0x00000001) {
820 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_FAULT");
821 nv_wr32(dev, 0x400500, 0);
822 if (nv_rd32(dev, 0x400808) & 0x80000000) {
823 if (display) {
824 if (nouveau_graph_trapped_channel(dev, &trap.channel))
825 trap.channel = -1;
826 trap.class = nv_rd32(dev, 0x400814);
827 trap.mthd = nv_rd32(dev, 0x400808) & 0x1ffc;
828 trap.subc = (nv_rd32(dev, 0x400808) >> 16) & 0x7;
829 trap.data = nv_rd32(dev, 0x40080c);
830 trap.data2 = nv_rd32(dev, 0x400810);
831 nouveau_graph_dump_trap_info(dev,
832 "PGRAPH_TRAP_DISPATCH_FAULT", &trap);
833 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400808: %08x\n", nv_rd32(dev, 0x400808));
834 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400848: %08x\n", nv_rd32(dev, 0x400848));
835 }
836 nv_wr32(dev, 0x400808, 0);
837 } else if (display) {
838 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - No stuck command?\n");
839 }
840 nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
841 nv_wr32(dev, 0x400848, 0);
842 ustatus &= ~0x00000001;
843 }
844 if (ustatus & 0x00000002) {
845 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_QUERY");
846 nv_wr32(dev, 0x400500, 0);
847 if (nv_rd32(dev, 0x40084c) & 0x80000000) {
848 if (display) {
849 if (nouveau_graph_trapped_channel(dev, &trap.channel))
850 trap.channel = -1;
851 trap.class = nv_rd32(dev, 0x400814);
852 trap.mthd = nv_rd32(dev, 0x40084c) & 0x1ffc;
853 trap.subc = (nv_rd32(dev, 0x40084c) >> 16) & 0x7;
854 trap.data = nv_rd32(dev, 0x40085c);
855 trap.data2 = 0;
856 nouveau_graph_dump_trap_info(dev,
857 "PGRAPH_TRAP_DISPATCH_QUERY", &trap);
858 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - 40084c: %08x\n", nv_rd32(dev, 0x40084c));
859 }
860 nv_wr32(dev, 0x40084c, 0);
861 } else if (display) {
862 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - No stuck command?\n");
863 }
864 ustatus &= ~0x00000002;
865 }
866 if (ustatus && display)
867 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - Unhandled ustatus 0x%08x\n", ustatus);
868 nv_wr32(dev, 0x400804, 0xc0000000);
869 nv_wr32(dev, 0x400108, 0x001);
870 status &= ~0x001;
871 }
872
873 /* TRAPs other than dispatch use the "normal" trap regs. */
874 if (status && display) {
875 nouveau_graph_trap_info(dev, &trap);
876 nouveau_graph_dump_trap_info(dev,
877 "PGRAPH_TRAP", &trap);
878 }
879
880 /* M2MF: Memory to memory copy engine. */
881 if (status & 0x002) {
882 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
883 if (!ustatus && display) {
884 NV_INFO(dev, "PGRAPH_TRAP_M2MF - no ustatus?\n");
885 }
886 if (ustatus & 0x00000001) {
887 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_NOTIFY");
888 ustatus &= ~0x00000001;
889 }
890 if (ustatus & 0x00000002) {
891 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_IN");
892 ustatus &= ~0x00000002;
893 }
894 if (ustatus & 0x00000004) {
895 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_OUT");
896 ustatus &= ~0x00000004;
897 }
898 NV_INFO (dev, "PGRAPH_TRAP_M2MF - %08x %08x %08x %08x\n",
899 nv_rd32(dev, 0x406804),
900 nv_rd32(dev, 0x406808),
901 nv_rd32(dev, 0x40680c),
902 nv_rd32(dev, 0x406810));
903 if (ustatus && display)
904 NV_INFO(dev, "PGRAPH_TRAP_M2MF - Unhandled ustatus 0x%08x\n", ustatus);
905 /* No sane way found yet -- just reset the bugger. */
906 nv_wr32(dev, 0x400040, 2);
907 nv_wr32(dev, 0x400040, 0);
908 nv_wr32(dev, 0x406800, 0xc0000000);
909 nv_wr32(dev, 0x400108, 0x002);
910 status &= ~0x002;
911 }
912
913 /* VFETCH: Fetches data from vertex buffers. */
914 if (status & 0x004) {
915 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
916 if (!ustatus && display) {
917 NV_INFO(dev, "PGRAPH_TRAP_VFETCH - no ustatus?\n");
918 }
919 if (ustatus & 0x00000001) {
920 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_VFETCH_FAULT");
921 NV_INFO (dev, "PGRAPH_TRAP_VFETCH_FAULT - %08x %08x %08x %08x\n",
922 nv_rd32(dev, 0x400c00),
923 nv_rd32(dev, 0x400c08),
924 nv_rd32(dev, 0x400c0c),
925 nv_rd32(dev, 0x400c10));
926 ustatus &= ~0x00000001;
927 }
928 if (ustatus && display)
929 NV_INFO(dev, "PGRAPH_TRAP_VFETCH - Unhandled ustatus 0x%08x\n", ustatus);
930 nv_wr32(dev, 0x400c04, 0xc0000000);
931 nv_wr32(dev, 0x400108, 0x004);
932 status &= ~0x004;
933 }
934
935 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
936 if (status & 0x008) {
937 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
938 if (!ustatus && display) {
939 NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - no ustatus?\n");
940 }
941 if (ustatus & 0x00000001) {
942 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_STRMOUT_FAULT");
943 NV_INFO (dev, "PGRAPH_TRAP_STRMOUT_FAULT - %08x %08x %08x %08x\n",
944 nv_rd32(dev, 0x401804),
945 nv_rd32(dev, 0x401808),
946 nv_rd32(dev, 0x40180c),
947 nv_rd32(dev, 0x401810));
948 ustatus &= ~0x00000001;
949 }
950 if (ustatus && display)
951 NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - Unhandled ustatus 0x%08x\n", ustatus);
952 /* No sane way found yet -- just reset the bugger. */
953 nv_wr32(dev, 0x400040, 0x80);
954 nv_wr32(dev, 0x400040, 0);
955 nv_wr32(dev, 0x401800, 0xc0000000);
956 nv_wr32(dev, 0x400108, 0x008);
957 status &= ~0x008;
958 }
959
960 /* CCACHE: Handles code and c[] caches and fills them. */
961 if (status & 0x010) {
962 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
963 if (!ustatus && display) {
964 NV_INFO(dev, "PGRAPH_TRAP_CCACHE - no ustatus?\n");
965 }
966 if (ustatus & 0x00000001) {
967 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_CCACHE_FAULT");
968 NV_INFO (dev, "PGRAPH_TRAP_CCACHE_FAULT - %08x %08x %08x %08x %08x %08x %08x\n",
969 nv_rd32(dev, 0x405800),
970 nv_rd32(dev, 0x405804),
971 nv_rd32(dev, 0x405808),
972 nv_rd32(dev, 0x40580c),
973 nv_rd32(dev, 0x405810),
974 nv_rd32(dev, 0x405814),
975 nv_rd32(dev, 0x40581c));
976 ustatus &= ~0x00000001;
977 }
978 if (ustatus && display)
979 NV_INFO(dev, "PGRAPH_TRAP_CCACHE - Unhandled ustatus 0x%08x\n", ustatus);
980 nv_wr32(dev, 0x405018, 0xc0000000);
981 nv_wr32(dev, 0x400108, 0x010);
982 status &= ~0x010;
983 }
984
985 /* Unknown, not seen yet... 0x402000 is the only trap status reg
986 * remaining, so try to handle it anyway. Perhaps related to that
987 * unknown DMA slot on tesla? */
988 if (status & 0x20) {
989 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_UNKC04");
990 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
991 if (display)
992 NV_INFO(dev, "PGRAPH_TRAP_UNKC04 - Unhandled ustatus 0x%08x\n", ustatus);
993 nv_wr32(dev, 0x402000, 0xc0000000);
994 /* no status modifiction on purpose */
995 }
996
997 /* TEXTURE: CUDA texturing units */
998 if (status & 0x040) {
999 nv50_pgraph_tp_trap (dev, 6, 0x408900, 0x408600, display,
1000 "PGRAPH_TRAP_TEXTURE");
1001 nv_wr32(dev, 0x400108, 0x040);
1002 status &= ~0x040;
1003 }
1004
1005 /* MP: CUDA execution engines. */
1006 if (status & 0x080) {
1007 nv50_pgraph_tp_trap (dev, 7, 0x408314, 0x40831c, display,
1008 "PGRAPH_TRAP_MP");
1009 nv_wr32(dev, 0x400108, 0x080);
1010 status &= ~0x080;
1011 }
1012
1013 /* TPDMA: Handles TP-initiated uncached memory accesses:
1014 * l[], g[], stack, 2d surfaces, render targets. */
1015 if (status & 0x100) {
1016 nv50_pgraph_tp_trap (dev, 8, 0x408e08, 0x408708, display,
1017 "PGRAPH_TRAP_TPDMA");
1018 nv_wr32(dev, 0x400108, 0x100);
1019 status &= ~0x100;
1020 }
1021
1022 if (status) {
1023 if (display)
1024 NV_INFO(dev, "PGRAPH_TRAP - Unknown trap 0x%08x\n",
1025 status);
1026 nv_wr32(dev, 0x400108, status);
1027 }
1028}
1029
1030/* There must be a *lot* of these. Will take some time to gather them up. */
1031static struct nouveau_enum_names nv50_data_error_names[] =
1032{
1033 { 4, "INVALID_VALUE" },
1034 { 5, "INVALID_ENUM" },
1035 { 8, "INVALID_OBJECT" },
1036 { 0xc, "INVALID_BITFIELD" },
1037 { 0x28, "MP_NO_REG_SPACE" },
1038 { 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
1039};
1040
1041static void
581nv50_pgraph_irq_handler(struct drm_device *dev) 1042nv50_pgraph_irq_handler(struct drm_device *dev)
582{ 1043{
1044 struct nouveau_pgraph_trap trap;
1045 int unhandled = 0;
583 uint32_t status; 1046 uint32_t status;
584 1047
585 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) { 1048 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
586 uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE); 1049 /* NOTIFY: You've set a NOTIFY an a command and it's done. */
587
588 if (status & 0x00000001) { 1050 if (status & 0x00000001) {
589 nouveau_pgraph_intr_notify(dev, nsource); 1051 nouveau_graph_trap_info(dev, &trap);
1052 if (nouveau_ratelimit())
1053 nouveau_graph_dump_trap_info(dev,
1054 "PGRAPH_NOTIFY", &trap);
590 status &= ~0x00000001; 1055 status &= ~0x00000001;
591 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001); 1056 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
592 } 1057 }
593 1058
594 if (status & 0x00000010) { 1059 /* COMPUTE_QUERY: Purpose and exact cause unknown, happens
595 nouveau_pgraph_intr_error(dev, nsource | 1060 * when you write 0x200 to 0x50c0 method 0x31c. */
596 NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD); 1061 if (status & 0x00000002) {
1062 nouveau_graph_trap_info(dev, &trap);
1063 if (nouveau_ratelimit())
1064 nouveau_graph_dump_trap_info(dev,
1065 "PGRAPH_COMPUTE_QUERY", &trap);
1066 status &= ~0x00000002;
1067 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000002);
1068 }
597 1069
1070 /* Unknown, never seen: 0x4 */
1071
1072 /* ILLEGAL_MTHD: You used a wrong method for this class. */
1073 if (status & 0x00000010) {
1074 nouveau_graph_trap_info(dev, &trap);
1075 if (nouveau_pgraph_intr_swmthd(dev, &trap))
1076 unhandled = 1;
1077 if (unhandled && nouveau_ratelimit())
1078 nouveau_graph_dump_trap_info(dev,
1079 "PGRAPH_ILLEGAL_MTHD", &trap);
598 status &= ~0x00000010; 1080 status &= ~0x00000010;
599 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010); 1081 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
600 } 1082 }
601 1083
1084 /* ILLEGAL_CLASS: You used a wrong class. */
1085 if (status & 0x00000020) {
1086 nouveau_graph_trap_info(dev, &trap);
1087 if (nouveau_ratelimit())
1088 nouveau_graph_dump_trap_info(dev,
1089 "PGRAPH_ILLEGAL_CLASS", &trap);
1090 status &= ~0x00000020;
1091 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000020);
1092 }
1093
1094 /* DOUBLE_NOTIFY: You tried to set a NOTIFY on another NOTIFY. */
1095 if (status & 0x00000040) {
1096 nouveau_graph_trap_info(dev, &trap);
1097 if (nouveau_ratelimit())
1098 nouveau_graph_dump_trap_info(dev,
1099 "PGRAPH_DOUBLE_NOTIFY", &trap);
1100 status &= ~0x00000040;
1101 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000040);
1102 }
1103
1104 /* CONTEXT_SWITCH: PGRAPH needs us to load a new context */
602 if (status & 0x00001000) { 1105 if (status & 0x00001000) {
603 nv_wr32(dev, 0x400500, 0x00000000); 1106 nv_wr32(dev, 0x400500, 0x00000000);
604 nv_wr32(dev, NV03_PGRAPH_INTR, 1107 nv_wr32(dev, NV03_PGRAPH_INTR,
@@ -613,49 +1116,59 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
613 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; 1116 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
614 } 1117 }
615 1118
616 if (status & 0x00100000) { 1119 /* BUFFER_NOTIFY: Your m2mf transfer finished */
617 nouveau_pgraph_intr_error(dev, nsource | 1120 if (status & 0x00010000) {
618 NV03_PGRAPH_NSOURCE_DATA_ERROR); 1121 nouveau_graph_trap_info(dev, &trap);
1122 if (nouveau_ratelimit())
1123 nouveau_graph_dump_trap_info(dev,
1124 "PGRAPH_BUFFER_NOTIFY", &trap);
1125 status &= ~0x00010000;
1126 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00010000);
1127 }
619 1128
1129 /* DATA_ERROR: Invalid value for this method, or invalid
1130 * state in current PGRAPH context for this operation */
1131 if (status & 0x00100000) {
1132 nouveau_graph_trap_info(dev, &trap);
1133 if (nouveau_ratelimit()) {
1134 nouveau_graph_dump_trap_info(dev,
1135 "PGRAPH_DATA_ERROR", &trap);
1136 NV_INFO (dev, "PGRAPH_DATA_ERROR - ");
1137 nouveau_print_enum_names(nv_rd32(dev, 0x400110),
1138 nv50_data_error_names);
1139 printk("\n");
1140 }
620 status &= ~0x00100000; 1141 status &= ~0x00100000;
621 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000); 1142 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
622 } 1143 }
623 1144
1145 /* TRAP: Something bad happened in the middle of command
1146 * execution. Has a billion types, subtypes, and even
1147 * subsubtypes. */
624 if (status & 0x00200000) { 1148 if (status & 0x00200000) {
625 int r; 1149 nv50_pgraph_trap_handler(dev);
626
627 nouveau_pgraph_intr_error(dev, nsource |
628 NV03_PGRAPH_NSOURCE_PROTECTION_ERROR);
629
630 NV_ERROR(dev, "magic set 1:\n");
631 for (r = 0x408900; r <= 0x408910; r += 4)
632 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
633 nv_rd32(dev, r));
634 nv_wr32(dev, 0x408900,
635 nv_rd32(dev, 0x408904) | 0xc0000000);
636 for (r = 0x408e08; r <= 0x408e24; r += 4)
637 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
638 nv_rd32(dev, r));
639 nv_wr32(dev, 0x408e08,
640 nv_rd32(dev, 0x408e08) | 0xc0000000);
641
642 NV_ERROR(dev, "magic set 2:\n");
643 for (r = 0x409900; r <= 0x409910; r += 4)
644 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
645 nv_rd32(dev, r));
646 nv_wr32(dev, 0x409900,
647 nv_rd32(dev, 0x409904) | 0xc0000000);
648 for (r = 0x409e08; r <= 0x409e24; r += 4)
649 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
650 nv_rd32(dev, r));
651 nv_wr32(dev, 0x409e08,
652 nv_rd32(dev, 0x409e08) | 0xc0000000);
653
654 status &= ~0x00200000; 1150 status &= ~0x00200000;
655 nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource);
656 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000); 1151 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
657 } 1152 }
658 1153
1154 /* Unknown, never seen: 0x00400000 */
1155
1156 /* SINGLE_STEP: Happens on every method if you turned on
1157 * single stepping in 40008c */
1158 if (status & 0x01000000) {
1159 nouveau_graph_trap_info(dev, &trap);
1160 if (nouveau_ratelimit())
1161 nouveau_graph_dump_trap_info(dev,
1162 "PGRAPH_SINGLE_STEP", &trap);
1163 status &= ~0x01000000;
1164 nv_wr32(dev, NV03_PGRAPH_INTR, 0x01000000);
1165 }
1166
1167 /* 0x02000000 happens when you pause a ctxprog...
1168 * but the only way this can happen that I know is by
1169 * poking the relevant MMIO register, and we don't
1170 * do that. */
1171
659 if (status) { 1172 if (status) {
660 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", 1173 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
661 status); 1174 status);
@@ -672,7 +1185,8 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
672 } 1185 }
673 1186
674 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); 1187 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
675 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31)); 1188 if (nv_rd32(dev, 0x400824) & (1 << 31))
1189 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
676} 1190}
677 1191
678static void 1192static void
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 2dc09dbd817d..775a7017af64 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -347,6 +347,20 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
347 return -EBUSY; 347 return -EBUSY;
348 } 348 }
349 349
350 nv_wr32(dev, 0x100c80, 0x00040001);
351 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
352 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
353 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
354 return -EBUSY;
355 }
356
357 nv_wr32(dev, 0x100c80, 0x00060001);
358 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
359 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
360 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
361 return -EBUSY;
362 }
363
350 return 0; 364 return 0;
351} 365}
352 366
@@ -387,6 +401,20 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
387 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { 401 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
388 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); 402 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
389 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); 403 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
404 return;
405 }
406
407 nv_wr32(dev, 0x100c80, 0x00040001);
408 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
409 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
410 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
411 return;
412 }
413
414 nv_wr32(dev, 0x100c80, 0x00060001);
415 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
416 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
417 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
390 } 418 }
391} 419}
392 420
@@ -449,9 +477,30 @@ void nouveau_mem_close(struct drm_device *dev)
449 } 477 }
450} 478}
451 479
452/*XXX won't work on BSD because of pci_read_config_dword */
453static uint32_t 480static uint32_t
454nouveau_mem_fb_amount_igp(struct drm_device *dev) 481nouveau_mem_detect_nv04(struct drm_device *dev)
482{
483 uint32_t boot0 = nv_rd32(dev, NV03_BOOT_0);
484
485 if (boot0 & 0x00000100)
486 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
487
488 switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) {
489 case NV04_BOOT_0_RAM_AMOUNT_32MB:
490 return 32 * 1024 * 1024;
491 case NV04_BOOT_0_RAM_AMOUNT_16MB:
492 return 16 * 1024 * 1024;
493 case NV04_BOOT_0_RAM_AMOUNT_8MB:
494 return 8 * 1024 * 1024;
495 case NV04_BOOT_0_RAM_AMOUNT_4MB:
496 return 4 * 1024 * 1024;
497 }
498
499 return 0;
500}
501
502static uint32_t
503nouveau_mem_detect_nforce(struct drm_device *dev)
455{ 504{
456 struct drm_nouveau_private *dev_priv = dev->dev_private; 505 struct drm_nouveau_private *dev_priv = dev->dev_private;
457 struct pci_dev *bridge; 506 struct pci_dev *bridge;
@@ -463,11 +512,11 @@ nouveau_mem_fb_amount_igp(struct drm_device *dev)
463 return 0; 512 return 0;
464 } 513 }
465 514
466 if (dev_priv->flags&NV_NFORCE) { 515 if (dev_priv->flags & NV_NFORCE) {
467 pci_read_config_dword(bridge, 0x7C, &mem); 516 pci_read_config_dword(bridge, 0x7C, &mem);
468 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; 517 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
469 } else 518 } else
470 if (dev_priv->flags&NV_NFORCE2) { 519 if (dev_priv->flags & NV_NFORCE2) {
471 pci_read_config_dword(bridge, 0x84, &mem); 520 pci_read_config_dword(bridge, 0x84, &mem);
472 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; 521 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
473 } 522 }
@@ -477,50 +526,32 @@ nouveau_mem_fb_amount_igp(struct drm_device *dev)
477} 526}
478 527
479/* returns the amount of FB ram in bytes */ 528/* returns the amount of FB ram in bytes */
480uint64_t nouveau_mem_fb_amount(struct drm_device *dev) 529int
530nouveau_mem_detect(struct drm_device *dev)
481{ 531{
482 struct drm_nouveau_private *dev_priv = dev->dev_private; 532 struct drm_nouveau_private *dev_priv = dev->dev_private;
483 uint32_t boot0; 533
484 534 if (dev_priv->card_type == NV_04) {
485 switch (dev_priv->card_type) { 535 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
486 case NV_04: 536 } else
487 boot0 = nv_rd32(dev, NV03_BOOT_0); 537 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
488 if (boot0 & 0x00000100) 538 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
489 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024; 539 } else {
490 540 dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA);
491 switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) { 541 dev_priv->vram_size &= NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK;
492 case NV04_BOOT_0_RAM_AMOUNT_32MB: 542 if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
493 return 32 * 1024 * 1024; 543 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;
494 case NV04_BOOT_0_RAM_AMOUNT_16MB:
495 return 16 * 1024 * 1024;
496 case NV04_BOOT_0_RAM_AMOUNT_8MB:
497 return 8 * 1024 * 1024;
498 case NV04_BOOT_0_RAM_AMOUNT_4MB:
499 return 4 * 1024 * 1024;
500 }
501 break;
502 case NV_10:
503 case NV_20:
504 case NV_30:
505 case NV_40:
506 case NV_50:
507 default:
508 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
509 return nouveau_mem_fb_amount_igp(dev);
510 } else {
511 uint64_t mem;
512 mem = (nv_rd32(dev, NV04_FIFO_DATA) &
513 NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >>
514 NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT;
515 return mem * 1024 * 1024;
516 }
517 break;
518 } 544 }
519 545
520 NV_ERROR(dev, 546 NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
521 "Unable to detect video ram size. Please report your setup to " 547 if (dev_priv->vram_sys_base) {
522 DRIVER_EMAIL "\n"); 548 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
523 return 0; 549 dev_priv->vram_sys_base);
550 }
551
552 if (dev_priv->vram_size)
553 return 0;
554 return -ENOMEM;
524} 555}
525 556
526#if __OS_HAS_AGP 557#if __OS_HAS_AGP
@@ -631,15 +662,12 @@ nouveau_mem_init(struct drm_device *dev)
631 spin_lock_init(&dev_priv->ttm.bo_list_lock); 662 spin_lock_init(&dev_priv->ttm.bo_list_lock);
632 spin_lock_init(&dev_priv->tile.lock); 663 spin_lock_init(&dev_priv->tile.lock);
633 664
634 dev_priv->fb_available_size = nouveau_mem_fb_amount(dev); 665 dev_priv->fb_available_size = dev_priv->vram_size;
635
636 dev_priv->fb_mappable_pages = dev_priv->fb_available_size; 666 dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
637 if (dev_priv->fb_mappable_pages > drm_get_resource_len(dev, 1)) 667 if (dev_priv->fb_mappable_pages > drm_get_resource_len(dev, 1))
638 dev_priv->fb_mappable_pages = drm_get_resource_len(dev, 1); 668 dev_priv->fb_mappable_pages = drm_get_resource_len(dev, 1);
639 dev_priv->fb_mappable_pages >>= PAGE_SHIFT; 669 dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
640 670
641 NV_INFO(dev, "%d MiB VRAM\n", (int)(dev_priv->fb_available_size >> 20));
642
643 /* remove reserved space at end of vram from available amount */ 671 /* remove reserved space at end of vram from available amount */
644 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; 672 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
645 dev_priv->fb_aper_free = dev_priv->fb_available_size; 673 dev_priv->fb_aper_free = dev_priv->fb_available_size;
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index ed1590577b6c..1d6ee8b55154 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -1,6 +1,7 @@
1#include "drmP.h" 1#include "drmP.h"
2#include "nouveau_drv.h" 2#include "nouveau_drv.h"
3#include <linux/pagemap.h> 3#include <linux/pagemap.h>
4#include <linux/slab.h>
4 5
5#define NV_CTXDMA_PAGE_SHIFT 12 6#define NV_CTXDMA_PAGE_SHIFT 12
6#define NV_CTXDMA_PAGE_SIZE (1 << NV_CTXDMA_PAGE_SHIFT) 7#define NV_CTXDMA_PAGE_SIZE (1 << NV_CTXDMA_PAGE_SHIFT)
@@ -171,6 +172,24 @@ nouveau_sgdma_unbind(struct ttm_backend *be)
171 } 172 }
172 dev_priv->engine.instmem.finish_access(nvbe->dev); 173 dev_priv->engine.instmem.finish_access(nvbe->dev);
173 174
175 if (dev_priv->card_type == NV_50) {
176 nv_wr32(dev, 0x100c80, 0x00050001);
177 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
178 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
179 NV_ERROR(dev, "0x100c80 = 0x%08x\n",
180 nv_rd32(dev, 0x100c80));
181 return -EBUSY;
182 }
183
184 nv_wr32(dev, 0x100c80, 0x00000001);
185 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
186 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
187 NV_ERROR(dev, "0x100c80 = 0x%08x\n",
188 nv_rd32(dev, 0x100c80));
189 return -EBUSY;
190 }
191 }
192
174 nvbe->bound = false; 193 nvbe->bound = false;
175 return 0; 194 return 0;
176} 195}
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index eb8f084d5f53..e1710640a278 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -24,6 +24,7 @@
24 */ 24 */
25 25
26#include <linux/swab.h> 26#include <linux/swab.h>
27#include <linux/slab.h>
27#include "drmP.h" 28#include "drmP.h"
28#include "drm.h" 29#include "drm.h"
29#include "drm_sarea.h" 30#include "drm_sarea.h"
@@ -35,7 +36,6 @@
35#include "nouveau_drm.h" 36#include "nouveau_drm.h"
36#include "nv50_display.h" 37#include "nv50_display.h"
37 38
38static int nouveau_stub_init(struct drm_device *dev) { return 0; }
39static void nouveau_stub_takedown(struct drm_device *dev) {} 39static void nouveau_stub_takedown(struct drm_device *dev) {}
40 40
41static int nouveau_init_engine_ptrs(struct drm_device *dev) 41static int nouveau_init_engine_ptrs(struct drm_device *dev)
@@ -277,8 +277,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
277 engine->timer.init = nv04_timer_init; 277 engine->timer.init = nv04_timer_init;
278 engine->timer.read = nv04_timer_read; 278 engine->timer.read = nv04_timer_read;
279 engine->timer.takedown = nv04_timer_takedown; 279 engine->timer.takedown = nv04_timer_takedown;
280 engine->fb.init = nouveau_stub_init; 280 engine->fb.init = nv50_fb_init;
281 engine->fb.takedown = nouveau_stub_takedown; 281 engine->fb.takedown = nv50_fb_takedown;
282 engine->graph.grclass = nv50_graph_grclass; 282 engine->graph.grclass = nv50_graph_grclass;
283 engine->graph.init = nv50_graph_init; 283 engine->graph.init = nv50_graph_init;
284 engine->graph.takedown = nv50_graph_takedown; 284 engine->graph.takedown = nv50_graph_takedown;
@@ -341,7 +341,7 @@ nouveau_card_init_channel(struct drm_device *dev)
341 341
342 gpuobj = NULL; 342 gpuobj = NULL;
343 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY, 343 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
344 0, nouveau_mem_fb_amount(dev), 344 0, dev_priv->vram_size,
345 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM, 345 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
346 &gpuobj); 346 &gpuobj);
347 if (ret) 347 if (ret)
@@ -427,6 +427,10 @@ nouveau_card_init(struct drm_device *dev)
427 goto out; 427 goto out;
428 } 428 }
429 429
430 ret = nouveau_mem_detect(dev);
431 if (ret)
432 goto out_bios;
433
430 ret = nouveau_gpuobj_early_init(dev); 434 ret = nouveau_gpuobj_early_init(dev);
431 if (ret) 435 if (ret)
432 goto out_bios; 436 goto out_bios;
@@ -502,7 +506,7 @@ nouveau_card_init(struct drm_device *dev)
502 else 506 else
503 ret = nv04_display_create(dev); 507 ret = nv04_display_create(dev);
504 if (ret) 508 if (ret)
505 goto out_irq; 509 goto out_channel;
506 } 510 }
507 511
508 ret = nouveau_backlight_init(dev); 512 ret = nouveau_backlight_init(dev);
@@ -516,6 +520,11 @@ nouveau_card_init(struct drm_device *dev)
516 520
517 return 0; 521 return 0;
518 522
523out_channel:
524 if (dev_priv->channel) {
525 nouveau_channel_free(dev_priv->channel);
526 dev_priv->channel = NULL;
527 }
519out_irq: 528out_irq:
520 drm_irq_uninstall(dev); 529 drm_irq_uninstall(dev);
521out_fifo: 530out_fifo:
@@ -533,6 +542,7 @@ out_mc:
533out_gpuobj: 542out_gpuobj:
534 nouveau_gpuobj_takedown(dev); 543 nouveau_gpuobj_takedown(dev);
535out_mem: 544out_mem:
545 nouveau_sgdma_takedown(dev);
536 nouveau_mem_close(dev); 546 nouveau_mem_close(dev);
537out_instmem: 547out_instmem:
538 engine->instmem.takedown(dev); 548 engine->instmem.takedown(dev);
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index a1d1ebb073d9..eba687f1099e 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -230,9 +230,9 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
230 struct drm_framebuffer *fb = crtc->fb; 230 struct drm_framebuffer *fb = crtc->fb;
231 231
232 /* Calculate our timings */ 232 /* Calculate our timings */
233 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 233 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
234 int horizStart = (mode->crtc_hsync_start >> 3) - 1; 234 int horizStart = (mode->crtc_hsync_start >> 3) + 1;
235 int horizEnd = (mode->crtc_hsync_end >> 3) - 1; 235 int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
236 int horizTotal = (mode->crtc_htotal >> 3) - 5; 236 int horizTotal = (mode->crtc_htotal >> 3) - 5;
237 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 237 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
238 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 238 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c
index 3da90c2c4e63..813b25cec726 100644
--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c
@@ -118,8 +118,8 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
118 return; 118 return;
119 } 119 }
120 120
121 width = ALIGN(image->width, 32); 121 width = ALIGN(image->width, 8);
122 dsize = (width * image->height) >> 5; 122 dsize = ALIGN(width * image->height, 32) >> 5;
123 123
124 if (info->fix.visual == FB_VISUAL_TRUECOLOR || 124 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
125 info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 125 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
@@ -136,8 +136,8 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
136 ((image->dx + image->width) & 0xffff)); 136 ((image->dx + image->width) & 0xffff));
137 OUT_RING(chan, bg); 137 OUT_RING(chan, bg);
138 OUT_RING(chan, fg); 138 OUT_RING(chan, fg);
139 OUT_RING(chan, (image->height << 16) | image->width);
140 OUT_RING(chan, (image->height << 16) | width); 139 OUT_RING(chan, (image->height << 16) | width);
140 OUT_RING(chan, (image->height << 16) | image->width);
141 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); 141 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
142 142
143 while (dsize) { 143 while (dsize) {
diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c
index 6b2ef4a9fce1..500ccfd3a0b8 100644
--- a/drivers/gpu/drm/nouveau/nv40_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv40_fifo.c
@@ -278,7 +278,7 @@ nv40_fifo_init_ramxx(struct drm_device *dev)
278 default: 278 default:
279 nv_wr32(dev, 0x2230, 0); 279 nv_wr32(dev, 0x2230, 0);
280 nv_wr32(dev, NV40_PFIFO_RAMFC, 280 nv_wr32(dev, NV40_PFIFO_RAMFC,
281 ((nouveau_mem_fb_amount(dev) - 512 * 1024 + 281 ((dev_priv->vram_size - 512 * 1024 +
282 dev_priv->ramfc_offset) >> 16) | (3 << 16)); 282 dev_priv->ramfc_offset) >> 16) | (3 << 16));
283 break; 283 break;
284 } 284 }
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 53e8afe1dcd1..0616c96e4b67 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -335,6 +335,27 @@ nv40_graph_init(struct drm_device *dev)
335 nv_wr32(dev, 0x400b38, 0x2ffff800); 335 nv_wr32(dev, 0x400b38, 0x2ffff800);
336 nv_wr32(dev, 0x400b3c, 0x00006000); 336 nv_wr32(dev, 0x400b3c, 0x00006000);
337 337
338 /* Tiling related stuff. */
339 switch (dev_priv->chipset) {
340 case 0x44:
341 case 0x4a:
342 nv_wr32(dev, 0x400bc4, 0x1003d888);
343 nv_wr32(dev, 0x400bbc, 0xb7a7b500);
344 break;
345 case 0x46:
346 nv_wr32(dev, 0x400bc4, 0x0000e024);
347 nv_wr32(dev, 0x400bbc, 0xb7a7b520);
348 break;
349 case 0x4c:
350 case 0x4e:
351 case 0x67:
352 nv_wr32(dev, 0x400bc4, 0x1003d888);
353 nv_wr32(dev, 0x400bbc, 0xb7a7b540);
354 break;
355 default:
356 break;
357 }
358
338 /* Turn all the tiling regions off. */ 359 /* Turn all the tiling regions off. */
339 for (i = 0; i < pfb->num_tiles; i++) 360 for (i = 0; i < pfb->num_tiles; i++)
340 nv40_graph_set_region_tiling(dev, i, 0, 0, 0); 361 nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 61a89f2dc553..649db4c1b690 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -143,7 +143,7 @@ nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
143 } 143 }
144 144
145 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19, 145 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
146 0, nouveau_mem_fb_amount(dev)); 146 0, dev_priv->vram_size);
147 if (ret) { 147 if (ret) {
148 nv50_evo_channel_del(pchan); 148 nv50_evo_channel_del(pchan);
149 return ret; 149 return ret;
@@ -231,7 +231,7 @@ nv50_display_init(struct drm_device *dev)
231 /* This used to be in crtc unblank, but seems out of place there. */ 231 /* This used to be in crtc unblank, but seems out of place there. */
232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0); 232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
233 /* RAM is clamped to 256 MiB. */ 233 /* RAM is clamped to 256 MiB. */
234 ram_amount = nouveau_mem_fb_amount(dev); 234 ram_amount = dev_priv->vram_size;
235 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount); 235 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
236 if (ram_amount > 256*1024*1024) 236 if (ram_amount > 256*1024*1024)
237 ram_amount = 256*1024*1024; 237 ram_amount = 256*1024*1024;
@@ -522,15 +522,17 @@ int nv50_display_create(struct drm_device *dev)
522 } 522 }
523 523
524 for (i = 0 ; i < dcb->connector.entries; i++) { 524 for (i = 0 ; i < dcb->connector.entries; i++) {
525 if (i != 0 && dcb->connector.entry[i].index == 525 if (i != 0 && dcb->connector.entry[i].index2 ==
526 dcb->connector.entry[i - 1].index) 526 dcb->connector.entry[i - 1].index2)
527 continue; 527 continue;
528 nouveau_connector_create(dev, &dcb->connector.entry[i]); 528 nouveau_connector_create(dev, &dcb->connector.entry[i]);
529 } 529 }
530 530
531 ret = nv50_display_init(dev); 531 ret = nv50_display_init(dev);
532 if (ret) 532 if (ret) {
533 nv50_display_destroy(dev);
533 return ret; 534 return ret;
535 }
534 536
535 return 0; 537 return 0;
536} 538}
@@ -885,10 +887,12 @@ nv50_display_error_handler(struct drm_device *dev)
885 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000); 887 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
886} 888}
887 889
888static void 890void
889nv50_display_irq_hotplug(struct drm_device *dev) 891nv50_display_irq_hotplug_bh(struct work_struct *work)
890{ 892{
891 struct drm_nouveau_private *dev_priv = dev->dev_private; 893 struct drm_nouveau_private *dev_priv =
894 container_of(work, struct drm_nouveau_private, hpd_work);
895 struct drm_device *dev = dev_priv->dev;
892 struct drm_connector *connector; 896 struct drm_connector *connector;
893 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; 897 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
894 uint32_t unplug_mask, plug_mask, change_mask; 898 uint32_t unplug_mask, plug_mask, change_mask;
@@ -949,8 +953,10 @@ nv50_display_irq_handler(struct drm_device *dev)
949 struct drm_nouveau_private *dev_priv = dev->dev_private; 953 struct drm_nouveau_private *dev_priv = dev->dev_private;
950 uint32_t delayed = 0; 954 uint32_t delayed = 0;
951 955
952 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) 956 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
953 nv50_display_irq_hotplug(dev); 957 if (!work_pending(&dev_priv->hpd_work))
958 queue_work(dev_priv->wq, &dev_priv->hpd_work);
959 }
954 960
955 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { 961 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
956 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 962 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
diff --git a/drivers/gpu/drm/nouveau/nv50_display.h b/drivers/gpu/drm/nouveau/nv50_display.h
index 3ae8d0725f63..581d405ac014 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.h
+++ b/drivers/gpu/drm/nouveau/nv50_display.h
@@ -37,6 +37,7 @@
37 37
38void nv50_display_irq_handler(struct drm_device *dev); 38void nv50_display_irq_handler(struct drm_device *dev);
39void nv50_display_irq_handler_bh(struct work_struct *work); 39void nv50_display_irq_handler_bh(struct work_struct *work);
40void nv50_display_irq_hotplug_bh(struct work_struct *work);
40int nv50_display_init(struct drm_device *dev); 41int nv50_display_init(struct drm_device *dev);
41int nv50_display_create(struct drm_device *dev); 42int nv50_display_create(struct drm_device *dev);
42int nv50_display_destroy(struct drm_device *dev); 43int nv50_display_destroy(struct drm_device *dev);
diff --git a/drivers/gpu/drm/nouveau/nv50_fb.c b/drivers/gpu/drm/nouveau/nv50_fb.c
new file mode 100644
index 000000000000..a95e6941ba88
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_fb.c
@@ -0,0 +1,32 @@
1#include "drmP.h"
2#include "drm.h"
3#include "nouveau_drv.h"
4#include "nouveau_drm.h"
5
6int
7nv50_fb_init(struct drm_device *dev)
8{
9 /* This is needed to get meaningful information from 100c90
10 * on traps. No idea what these values mean exactly. */
11 struct drm_nouveau_private *dev_priv = dev->dev_private;
12
13 switch (dev_priv->chipset) {
14 case 0x50:
15 nv_wr32(dev, 0x100c90, 0x0707ff);
16 break;
17 case 0xa5:
18 case 0xa8:
19 nv_wr32(dev, 0x100c90, 0x0d0fff);
20 break;
21 default:
22 nv_wr32(dev, 0x100c90, 0x1d07ff);
23 break;
24 }
25
26 return 0;
27}
28
29void
30nv50_fb_takedown(struct drm_device *dev)
31{
32}
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c
index 993c7126fbde..a8c70e7e9184 100644
--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
@@ -157,8 +157,11 @@ nv50_fbcon_accel_init(struct fb_info *info)
157 struct drm_nouveau_private *dev_priv = dev->dev_private; 157 struct drm_nouveau_private *dev_priv = dev->dev_private;
158 struct nouveau_channel *chan = dev_priv->channel; 158 struct nouveau_channel *chan = dev_priv->channel;
159 struct nouveau_gpuobj *eng2d = NULL; 159 struct nouveau_gpuobj *eng2d = NULL;
160 uint64_t fb;
160 int ret, format; 161 int ret, format;
161 162
163 fb = info->fix.smem_start - dev_priv->fb_phys + dev_priv->vm_vram_base;
164
162 switch (info->var.bits_per_pixel) { 165 switch (info->var.bits_per_pixel) {
163 case 8: 166 case 8:
164 format = 0xf3; 167 format = 0xf3;
@@ -233,7 +236,7 @@ nv50_fbcon_accel_init(struct fb_info *info)
233 BEGIN_RING(chan, NvSub2D, 0x0808, 3); 236 BEGIN_RING(chan, NvSub2D, 0x0808, 3);
234 OUT_RING(chan, 0); 237 OUT_RING(chan, 0);
235 OUT_RING(chan, 0); 238 OUT_RING(chan, 0);
236 OUT_RING(chan, 0); 239 OUT_RING(chan, 1);
237 BEGIN_RING(chan, NvSub2D, 0x081c, 1); 240 BEGIN_RING(chan, NvSub2D, 0x081c, 1);
238 OUT_RING(chan, 1); 241 OUT_RING(chan, 1);
239 BEGIN_RING(chan, NvSub2D, 0x0840, 4); 242 BEGIN_RING(chan, NvSub2D, 0x0840, 4);
@@ -248,9 +251,8 @@ nv50_fbcon_accel_init(struct fb_info *info)
248 OUT_RING(chan, info->fix.line_length); 251 OUT_RING(chan, info->fix.line_length);
249 OUT_RING(chan, info->var.xres_virtual); 252 OUT_RING(chan, info->var.xres_virtual);
250 OUT_RING(chan, info->var.yres_virtual); 253 OUT_RING(chan, info->var.yres_virtual);
251 OUT_RING(chan, 0); 254 OUT_RING(chan, upper_32_bits(fb));
252 OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys + 255 OUT_RING(chan, lower_32_bits(fb));
253 dev_priv->vm_vram_base);
254 BEGIN_RING(chan, NvSub2D, 0x0230, 2); 256 BEGIN_RING(chan, NvSub2D, 0x0230, 2);
255 OUT_RING(chan, format); 257 OUT_RING(chan, format);
256 OUT_RING(chan, 1); 258 OUT_RING(chan, 1);
@@ -258,9 +260,8 @@ nv50_fbcon_accel_init(struct fb_info *info)
258 OUT_RING(chan, info->fix.line_length); 260 OUT_RING(chan, info->fix.line_length);
259 OUT_RING(chan, info->var.xres_virtual); 261 OUT_RING(chan, info->var.xres_virtual);
260 OUT_RING(chan, info->var.yres_virtual); 262 OUT_RING(chan, info->var.yres_virtual);
261 OUT_RING(chan, 0); 263 OUT_RING(chan, upper_32_bits(fb));
262 OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys + 264 OUT_RING(chan, lower_32_bits(fb));
263 dev_priv->vm_vram_base);
264 265
265 return 0; 266 return 0;
266} 267}
diff --git a/drivers/gpu/drm/nouveau/nv50_gpio.c b/drivers/gpu/drm/nouveau/nv50_gpio.c
new file mode 100644
index 000000000000..c61782b314e7
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_gpio.c
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_hw.h"
28
29static int
30nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift)
31{
32 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
33
34 if (gpio->line > 32)
35 return -EINVAL;
36
37 *reg = nv50_gpio_reg[gpio->line >> 3];
38 *shift = (gpio->line & 7) << 2;
39 return 0;
40}
41
42int
43nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag)
44{
45 struct dcb_gpio_entry *gpio;
46 uint32_t r, s, v;
47
48 gpio = nouveau_bios_gpio_entry(dev, tag);
49 if (!gpio)
50 return -ENOENT;
51
52 if (nv50_gpio_location(gpio, &r, &s))
53 return -EINVAL;
54
55 v = nv_rd32(dev, r) >> (s + 2);
56 return ((v & 1) == (gpio->state[1] & 1));
57}
58
59int
60nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
61{
62 struct dcb_gpio_entry *gpio;
63 uint32_t r, s, v;
64
65 gpio = nouveau_bios_gpio_entry(dev, tag);
66 if (!gpio)
67 return -ENOENT;
68
69 if (nv50_gpio_location(gpio, &r, &s))
70 return -EINVAL;
71
72 v = nv_rd32(dev, r) & ~(0x3 << s);
73 v |= (gpio->state[state] ^ 2) << s;
74 nv_wr32(dev, r, v);
75 return 0;
76}
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 857a09671a39..b203d06f601f 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -56,6 +56,10 @@ nv50_graph_init_intr(struct drm_device *dev)
56static void 56static void
57nv50_graph_init_regs__nv(struct drm_device *dev) 57nv50_graph_init_regs__nv(struct drm_device *dev)
58{ 58{
59 struct drm_nouveau_private *dev_priv = dev->dev_private;
60 uint32_t units = nv_rd32(dev, 0x1540);
61 int i;
62
59 NV_DEBUG(dev, "\n"); 63 NV_DEBUG(dev, "\n");
60 64
61 nv_wr32(dev, 0x400804, 0xc0000000); 65 nv_wr32(dev, 0x400804, 0xc0000000);
@@ -65,6 +69,20 @@ nv50_graph_init_regs__nv(struct drm_device *dev)
65 nv_wr32(dev, 0x405018, 0xc0000000); 69 nv_wr32(dev, 0x405018, 0xc0000000);
66 nv_wr32(dev, 0x402000, 0xc0000000); 70 nv_wr32(dev, 0x402000, 0xc0000000);
67 71
72 for (i = 0; i < 16; i++) {
73 if (units & 1 << i) {
74 if (dev_priv->chipset < 0xa0) {
75 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
76 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
77 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
78 } else {
79 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
80 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
81 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
82 }
83 }
84 }
85
68 nv_wr32(dev, 0x400108, 0xffffffff); 86 nv_wr32(dev, 0x400108, 0xffffffff);
69 87
70 nv_wr32(dev, 0x400824, 0x00004000); 88 nv_wr32(dev, 0x400824, 0x00004000);
@@ -229,10 +247,6 @@ nv50_graph_create_context(struct nouveau_channel *chan)
229 nouveau_grctx_vals_load(dev, ctx); 247 nouveau_grctx_vals_load(dev, ctx);
230 } 248 }
231 nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12); 249 nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12);
232 if ((dev_priv->chipset & 0xf0) == 0xa0)
233 nv_wo32(dev, ctx, 0x00004/4, 0x00000000);
234 else
235 nv_wo32(dev, ctx, 0x0011c/4, 0x00000000);
236 dev_priv->engine.instmem.finish_access(dev); 250 dev_priv->engine.instmem.finish_access(dev);
237 251
238 return 0; 252 return 0;
@@ -396,9 +410,10 @@ struct nouveau_pgraph_object_class nv50_graph_grclass[] = {
396 { 0x5039, false, NULL }, /* m2mf */ 410 { 0x5039, false, NULL }, /* m2mf */
397 { 0x502d, false, NULL }, /* 2d */ 411 { 0x502d, false, NULL }, /* 2d */
398 { 0x50c0, false, NULL }, /* compute */ 412 { 0x50c0, false, NULL }, /* compute */
413 { 0x85c0, false, NULL }, /* compute (nva3, nva5, nva8) */
399 { 0x5097, false, NULL }, /* tesla (nv50) */ 414 { 0x5097, false, NULL }, /* tesla (nv50) */
400 { 0x8297, false, NULL }, /* tesla (nv80/nv90) */ 415 { 0x8297, false, NULL }, /* tesla (nv8x/nv9x) */
401 { 0x8397, false, NULL }, /* tesla (nva0) */ 416 { 0x8397, false, NULL }, /* tesla (nva0, nvaa, nvac) */
402 { 0x8597, false, NULL }, /* tesla (nva8) */ 417 { 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */
403 {} 418 {}
404}; 419};
diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c
index d105fcd42ca0..42a8fb20c1e6 100644
--- a/drivers/gpu/drm/nouveau/nv50_grctx.c
+++ b/drivers/gpu/drm/nouveau/nv50_grctx.c
@@ -55,15 +55,18 @@
55#define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) 55#define CP_FLAG_AUTO_LOAD ((2 * 32) + 5)
56#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 56#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
57#define CP_FLAG_AUTO_LOAD_PENDING 1 57#define CP_FLAG_AUTO_LOAD_PENDING 1
58#define CP_FLAG_NEWCTX ((2 * 32) + 10)
59#define CP_FLAG_NEWCTX_BUSY 0
60#define CP_FLAG_NEWCTX_DONE 1
58#define CP_FLAG_XFER ((2 * 32) + 11) 61#define CP_FLAG_XFER ((2 * 32) + 11)
59#define CP_FLAG_XFER_IDLE 0 62#define CP_FLAG_XFER_IDLE 0
60#define CP_FLAG_XFER_BUSY 1 63#define CP_FLAG_XFER_BUSY 1
61#define CP_FLAG_NEWCTX ((2 * 32) + 12)
62#define CP_FLAG_NEWCTX_BUSY 0
63#define CP_FLAG_NEWCTX_DONE 1
64#define CP_FLAG_ALWAYS ((2 * 32) + 13) 64#define CP_FLAG_ALWAYS ((2 * 32) + 13)
65#define CP_FLAG_ALWAYS_FALSE 0 65#define CP_FLAG_ALWAYS_FALSE 0
66#define CP_FLAG_ALWAYS_TRUE 1 66#define CP_FLAG_ALWAYS_TRUE 1
67#define CP_FLAG_INTR ((2 * 32) + 15)
68#define CP_FLAG_INTR_NOT_PENDING 0
69#define CP_FLAG_INTR_PENDING 1
67 70
68#define CP_CTX 0x00100000 71#define CP_CTX 0x00100000
69#define CP_CTX_COUNT 0x000f0000 72#define CP_CTX_COUNT 0x000f0000
@@ -174,6 +177,7 @@ nv50_grctx_init(struct nouveau_grctx *ctx)
174 case 0x96: 177 case 0x96:
175 case 0x98: 178 case 0x98:
176 case 0xa0: 179 case 0xa0:
180 case 0xa3:
177 case 0xa5: 181 case 0xa5:
178 case 0xa8: 182 case 0xa8:
179 case 0xaa: 183 case 0xaa:
@@ -214,6 +218,8 @@ nv50_grctx_init(struct nouveau_grctx *ctx)
214 cp_name(ctx, cp_setup_save); 218 cp_name(ctx, cp_setup_save);
215 cp_set (ctx, UNK1D, SET); 219 cp_set (ctx, UNK1D, SET);
216 cp_wait(ctx, STATUS, BUSY); 220 cp_wait(ctx, STATUS, BUSY);
221 cp_wait(ctx, INTR, PENDING);
222 cp_bra (ctx, STATUS, BUSY, cp_setup_save);
217 cp_set (ctx, UNK01, SET); 223 cp_set (ctx, UNK01, SET);
218 cp_set (ctx, SWAP_DIRECTION, SAVE); 224 cp_set (ctx, SWAP_DIRECTION, SAVE);
219 225
@@ -269,7 +275,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
269 int offset, base; 275 int offset, base;
270 uint32_t units = nv_rd32 (ctx->dev, 0x1540); 276 uint32_t units = nv_rd32 (ctx->dev, 0x1540);
271 277
272 /* 0800 */ 278 /* 0800: DISPATCH */
273 cp_ctx(ctx, 0x400808, 7); 279 cp_ctx(ctx, 0x400808, 7);
274 gr_def(ctx, 0x400814, 0x00000030); 280 gr_def(ctx, 0x400814, 0x00000030);
275 cp_ctx(ctx, 0x400834, 0x32); 281 cp_ctx(ctx, 0x400834, 0x32);
@@ -300,7 +306,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
300 gr_def(ctx, 0x400b20, 0x0001629d); 306 gr_def(ctx, 0x400b20, 0x0001629d);
301 } 307 }
302 308
303 /* 0C00 */ 309 /* 0C00: VFETCH */
304 cp_ctx(ctx, 0x400c08, 0x2); 310 cp_ctx(ctx, 0x400c08, 0x2);
305 gr_def(ctx, 0x400c08, 0x0000fe0c); 311 gr_def(ctx, 0x400c08, 0x0000fe0c);
306 312
@@ -326,7 +332,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
326 cp_ctx(ctx, 0x401540, 0x5); 332 cp_ctx(ctx, 0x401540, 0x5);
327 gr_def(ctx, 0x401550, 0x00001018); 333 gr_def(ctx, 0x401550, 0x00001018);
328 334
329 /* 1800 */ 335 /* 1800: STREAMOUT */
330 cp_ctx(ctx, 0x401814, 0x1); 336 cp_ctx(ctx, 0x401814, 0x1);
331 gr_def(ctx, 0x401814, 0x000000ff); 337 gr_def(ctx, 0x401814, 0x000000ff);
332 if (dev_priv->chipset == 0x50) { 338 if (dev_priv->chipset == 0x50) {
@@ -359,6 +365,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
359 case 0xac: 365 case 0xac:
360 gr_def(ctx, 0x401c00, 0x042500df); 366 gr_def(ctx, 0x401c00, 0x042500df);
361 break; 367 break;
368 case 0xa3:
362 case 0xa5: 369 case 0xa5:
363 case 0xa8: 370 case 0xa8:
364 gr_def(ctx, 0x401c00, 0x142500df); 371 gr_def(ctx, 0x401c00, 0x142500df);
@@ -413,6 +420,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
413 break; 420 break;
414 case 0x84: 421 case 0x84:
415 case 0xa0: 422 case 0xa0:
423 case 0xa3:
416 case 0xa5: 424 case 0xa5:
417 case 0xa8: 425 case 0xa8:
418 case 0xaa: 426 case 0xaa:
@@ -641,7 +649,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
641 if (dev_priv->chipset == 0x50) 649 if (dev_priv->chipset == 0x50)
642 cp_ctx(ctx, 0x4063e0, 0x1); 650 cp_ctx(ctx, 0x4063e0, 0x1);
643 651
644 /* 6800 */ 652 /* 6800: M2MF */
645 if (dev_priv->chipset < 0x90) { 653 if (dev_priv->chipset < 0x90) {
646 cp_ctx(ctx, 0x406814, 0x2b); 654 cp_ctx(ctx, 0x406814, 0x2b);
647 gr_def(ctx, 0x406818, 0x00000f80); 655 gr_def(ctx, 0x406818, 0x00000f80);
@@ -787,6 +795,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
787 case 0xa5: 795 case 0xa5:
788 gr_def(ctx, offset + 0x1c, 0x310c0000); 796 gr_def(ctx, offset + 0x1c, 0x310c0000);
789 break; 797 break;
798 case 0xa3:
790 case 0xa8: 799 case 0xa8:
791 case 0xaa: 800 case 0xaa:
792 case 0xac: 801 case 0xac:
@@ -854,6 +863,8 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
854 else 863 else
855 gr_def(ctx, offset + 0x8, 0x05010202); 864 gr_def(ctx, offset + 0x8, 0x05010202);
856 gr_def(ctx, offset + 0xc, 0x00030201); 865 gr_def(ctx, offset + 0xc, 0x00030201);
866 if (dev_priv->chipset == 0xa3)
867 cp_ctx(ctx, base + 0x36c, 1);
857 868
858 cp_ctx(ctx, base + 0x400, 2); 869 cp_ctx(ctx, base + 0x400, 2);
859 gr_def(ctx, base + 0x404, 0x00000040); 870 gr_def(ctx, base + 0x404, 0x00000040);
@@ -1154,7 +1165,9 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
1154 nv50_graph_construct_gene_unk8(ctx); 1165 nv50_graph_construct_gene_unk8(ctx);
1155 if (dev_priv->chipset == 0xa0) 1166 if (dev_priv->chipset == 0xa0)
1156 xf_emit(ctx, 0x189, 0); 1167 xf_emit(ctx, 0x189, 0);
1157 else if (dev_priv->chipset < 0xa8) 1168 else if (dev_priv->chipset == 0xa3)
1169 xf_emit(ctx, 0xd5, 0);
1170 else if (dev_priv->chipset == 0xa5)
1158 xf_emit(ctx, 0x99, 0); 1171 xf_emit(ctx, 0x99, 0);
1159 else if (dev_priv->chipset == 0xaa) 1172 else if (dev_priv->chipset == 0xaa)
1160 xf_emit(ctx, 0x65, 0); 1173 xf_emit(ctx, 0x65, 0);
@@ -1192,6 +1205,8 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
1192 ctx->ctxvals_pos = offset + 4; 1205 ctx->ctxvals_pos = offset + 4;
1193 if (dev_priv->chipset == 0xa0) 1206 if (dev_priv->chipset == 0xa0)
1194 xf_emit(ctx, 0xa80, 0); 1207 xf_emit(ctx, 0xa80, 0);
1208 else if (dev_priv->chipset == 0xa3)
1209 xf_emit(ctx, 0xa7c, 0);
1195 else 1210 else
1196 xf_emit(ctx, 0xa7a, 0); 1211 xf_emit(ctx, 0xa7a, 0);
1197 xf_emit(ctx, 1, 0x3fffff); 1212 xf_emit(ctx, 1, 0x3fffff);
@@ -1336,6 +1351,7 @@ nv50_graph_construct_gene_unk1(struct nouveau_grctx *ctx)
1336 xf_emit(ctx, 0x942, 0); 1351 xf_emit(ctx, 0x942, 0);
1337 break; 1352 break;
1338 case 0xa0: 1353 case 0xa0:
1354 case 0xa3:
1339 xf_emit(ctx, 0x2042, 0); 1355 xf_emit(ctx, 0x2042, 0);
1340 break; 1356 break;
1341 case 0xa5: 1357 case 0xa5:
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
index de1f5b0062c5..5f21df31f3aa 100644
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
@@ -63,9 +63,10 @@ nv50_instmem_init(struct drm_device *dev)
63 struct drm_nouveau_private *dev_priv = dev->dev_private; 63 struct drm_nouveau_private *dev_priv = dev->dev_private;
64 struct nouveau_channel *chan; 64 struct nouveau_channel *chan;
65 uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size; 65 uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size;
66 uint32_t save_nv001700;
67 uint64_t v;
66 struct nv50_instmem_priv *priv; 68 struct nv50_instmem_priv *priv;
67 int ret, i; 69 int ret, i;
68 uint32_t v, save_nv001700;
69 70
70 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 71 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
71 if (!priv) 72 if (!priv)
@@ -76,17 +77,12 @@ nv50_instmem_init(struct drm_device *dev)
76 for (i = 0x1700; i <= 0x1710; i += 4) 77 for (i = 0x1700; i <= 0x1710; i += 4)
77 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i); 78 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
78 79
79 if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
80 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;
81 else
82 dev_priv->vram_sys_base = 0;
83
84 /* Reserve the last MiB of VRAM, we should probably try to avoid 80 /* Reserve the last MiB of VRAM, we should probably try to avoid
85 * setting up the below tables over the top of the VBIOS image at 81 * setting up the below tables over the top of the VBIOS image at
86 * some point. 82 * some point.
87 */ 83 */
88 dev_priv->ramin_rsvd_vram = 1 << 20; 84 dev_priv->ramin_rsvd_vram = 1 << 20;
89 c_offset = nouveau_mem_fb_amount(dev) - dev_priv->ramin_rsvd_vram; 85 c_offset = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
90 c_size = 128 << 10; 86 c_size = 128 << 10;
91 c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200; 87 c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200;
92 c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20; 88 c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20;
@@ -106,7 +102,7 @@ nv50_instmem_init(struct drm_device *dev)
106 dev_priv->vm_gart_size = NV50_VM_BLOCK; 102 dev_priv->vm_gart_size = NV50_VM_BLOCK;
107 103
108 dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size; 104 dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size;
109 dev_priv->vm_vram_size = nouveau_mem_fb_amount(dev); 105 dev_priv->vm_vram_size = dev_priv->vram_size;
110 if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM) 106 if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM)
111 dev_priv->vm_vram_size = NV50_VM_MAX_VRAM; 107 dev_priv->vm_vram_size = NV50_VM_MAX_VRAM;
112 dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK); 108 dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK);
@@ -189,8 +185,8 @@ nv50_instmem_init(struct drm_device *dev)
189 185
190 i = 0; 186 i = 0;
191 while (v < dev_priv->vram_sys_base + c_offset + c_size) { 187 while (v < dev_priv->vram_sys_base + c_offset + c_size) {
192 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v); 188 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, lower_32_bits(v));
193 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000); 189 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, upper_32_bits(v));
194 v += 0x1000; 190 v += 0x1000;
195 i += 8; 191 i += 8;
196 } 192 }
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
index c2fff543b06f..0c68698f23df 100644
--- a/drivers/gpu/drm/nouveau/nv50_sor.c
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -211,7 +211,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
211 mode_ctl = 0x0200; 211 mode_ctl = 0x0200;
212 break; 212 break;
213 case OUTPUT_DP: 213 case OUTPUT_DP:
214 mode_ctl |= 0x00050000; 214 mode_ctl |= (nv_encoder->dp.mc_unknown << 16);
215 if (nv_encoder->dcb->sorconf.link & 1) 215 if (nv_encoder->dcb->sorconf.link & 1)
216 mode_ctl |= 0x00000800; 216 mode_ctl |= 0x00000800;
217 else 217 else
@@ -274,6 +274,7 @@ static const struct drm_encoder_funcs nv50_sor_encoder_funcs = {
274int 274int
275nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry) 275nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
276{ 276{
277 struct drm_nouveau_private *dev_priv = dev->dev_private;
277 struct nouveau_encoder *nv_encoder = NULL; 278 struct nouveau_encoder *nv_encoder = NULL;
278 struct drm_encoder *encoder; 279 struct drm_encoder *encoder;
279 bool dum; 280 bool dum;
@@ -319,5 +320,27 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
319 encoder->possible_crtcs = entry->heads; 320 encoder->possible_crtcs = entry->heads;
320 encoder->possible_clones = 0; 321 encoder->possible_clones = 0;
321 322
323 if (nv_encoder->dcb->type == OUTPUT_DP) {
324 uint32_t mc, or = nv_encoder->or;
325
326 if (dev_priv->chipset < 0x90 ||
327 dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
328 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(or));
329 else
330 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(or));
331
332 switch ((mc & 0x00000f00) >> 8) {
333 case 8:
334 case 9:
335 nv_encoder->dp.mc_unknown = (mc & 0x000f0000) >> 16;
336 break;
337 default:
338 break;
339 }
340
341 if (!nv_encoder->dp.mc_unknown)
342 nv_encoder->dp.mc_unknown = 5;
343 }
344
322 return 0; 345 return 0;
323} 346}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 04:16:38 -0500