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-rw-r--r--drivers/gpu/drm/nouveau/Kconfig5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_acpi.c12
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c205
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c245
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_channel.c54
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_connector.c36
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dma.c108
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dma.h10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dp.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c14
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h78
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c59
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.h7
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fence.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c55
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_grctx.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c161
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c215
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_notifier.c13
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_object.c5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_reg.h17
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_sgdma.c7
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c77
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_ttm.c30
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dac.c41
-rw-r--r--drivers/gpu/drm/nouveau/nv04_fbcon.c50
-rw-r--r--drivers/gpu/drm/nouveau/nv04_fifo.c34
-rw-r--r--drivers/gpu/drm/nouveau/nv04_graph.c159
-rw-r--r--drivers/gpu/drm/nouveau/nv04_instmem.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv10_fb.c32
-rw-r--r--drivers/gpu/drm/nouveau/nv10_graph.c28
-rw-r--r--drivers/gpu/drm/nouveau/nv17_tv.c117
-rw-r--r--drivers/gpu/drm/nouveau/nv20_graph.c61
-rw-r--r--drivers/gpu/drm/nouveau/nv40_fb.c53
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c116
-rw-r--r--drivers/gpu/drm/nouveau/nv50_crtc.c33
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c17
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fbcon.c32
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fifo.c17
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c13
-rw-r--r--drivers/gpu/drm/nouveau/nv50_instmem.c58
-rw-r--r--drivers/gpu/drm/nouveau/nv50_sor.c14
43 files changed, 1468 insertions, 838 deletions
diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig
index b1bc1ea182b8..1175429da102 100644
--- a/drivers/gpu/drm/nouveau/Kconfig
+++ b/drivers/gpu/drm/nouveau/Kconfig
@@ -30,12 +30,11 @@ config DRM_NOUVEAU_DEBUG
30 via debugfs. 30 via debugfs.
31 31
32menu "I2C encoder or helper chips" 32menu "I2C encoder or helper chips"
33 depends on DRM && I2C 33 depends on DRM && DRM_KMS_HELPER && I2C
34 34
35config DRM_I2C_CH7006 35config DRM_I2C_CH7006
36 tristate "Chrontel ch7006 TV encoder" 36 tristate "Chrontel ch7006 TV encoder"
37 depends on DRM_NOUVEAU 37 default m if DRM_NOUVEAU
38 default m
39 help 38 help
40 Support for Chrontel ch7006 and similar TV encoders, found 39 Support for Chrontel ch7006 and similar TV encoders, found
41 on some nVidia video cards. 40 on some nVidia video cards.
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 1cf488247a16..48227e744753 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -90,21 +90,21 @@ int nouveau_hybrid_setup(struct drm_device *dev)
90{ 90{
91 int result; 91 int result;
92 92
93 if (nouveau_dsm(dev, NOUVEAU_DSM_ACTIVE, NOUVEAU_DSM_ACTIVE_QUERY, 93 if (nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_STATE,
94 &result)) 94 &result))
95 return -ENODEV; 95 return -ENODEV;
96 96
97 NV_INFO(dev, "_DSM hardware status gave 0x%x\n", result); 97 NV_INFO(dev, "_DSM hardware status gave 0x%x\n", result);
98 98
99 if (result & 0x1) { /* Stamina mode - disable the external GPU */ 99 if (result) { /* Ensure that the external GPU is enabled */
100 nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_SPEED, NULL);
101 nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_SPEED,
102 NULL);
103 } else { /* Stamina mode - disable the external GPU */
100 nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_STAMINA, 104 nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_STAMINA,
101 NULL); 105 NULL);
102 nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_STAMINA, 106 nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_STAMINA,
103 NULL); 107 NULL);
104 } else { /* Ensure that the external GPU is enabled */
105 nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_SPEED, NULL);
106 nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_SPEED,
107 NULL);
108 } 108 }
109 109
110 return 0; 110 return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index ba143972769f..0e9cd1d49130 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -310,63 +310,22 @@ valid_reg(struct nvbios *bios, uint32_t reg)
310 struct drm_device *dev = bios->dev; 310 struct drm_device *dev = bios->dev;
311 311
312 /* C51 has misaligned regs on purpose. Marvellous */ 312 /* C51 has misaligned regs on purpose. Marvellous */
313 if (reg & 0x2 || (reg & 0x1 && dev_priv->VBIOS.pub.chip_version != 0x51)) { 313 if (reg & 0x2 ||
314 NV_ERROR(dev, "========== misaligned reg 0x%08X ==========\n", 314 (reg & 0x1 && dev_priv->VBIOS.pub.chip_version != 0x51))
315 reg); 315 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
316 return 0; 316
317 } 317 /* warn on C51 regs that haven't been verified accessible in tracing */
318 /*
319 * Warn on C51 regs that have not been verified accessible in
320 * mmiotracing
321 */
322 if (reg & 0x1 && dev_priv->VBIOS.pub.chip_version == 0x51 && 318 if (reg & 0x1 && dev_priv->VBIOS.pub.chip_version == 0x51 &&
323 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 319 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
324 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 320 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
325 reg); 321 reg);
326 322
327 /* Trust the init scripts on G80 */ 323 if (reg >= (8*1024*1024)) {
328 if (dev_priv->card_type >= NV_50) 324 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
329 return 1; 325 return 0;
330
331 #define WITHIN(x, y, z) ((x >= y) && (x < y + z))
332 if (WITHIN(reg, NV_PMC_OFFSET, NV_PMC_SIZE))
333 return 1;
334 if (WITHIN(reg, NV_PBUS_OFFSET, NV_PBUS_SIZE))
335 return 1;
336 if (WITHIN(reg, NV_PFIFO_OFFSET, NV_PFIFO_SIZE))
337 return 1;
338 if (dev_priv->VBIOS.pub.chip_version >= 0x30 &&
339 (WITHIN(reg, 0x4000, 0x600) || reg == 0x00004600))
340 return 1;
341 if (dev_priv->VBIOS.pub.chip_version >= 0x40 &&
342 WITHIN(reg, 0xc000, 0x48))
343 return 1;
344 if (dev_priv->VBIOS.pub.chip_version >= 0x17 && reg == 0x0000d204)
345 return 1;
346 if (dev_priv->VBIOS.pub.chip_version >= 0x40) {
347 if (reg == 0x00011014 || reg == 0x00020328)
348 return 1;
349 if (WITHIN(reg, 0x88000, NV_PBUS_SIZE)) /* new PBUS */
350 return 1;
351 } 326 }
352 if (WITHIN(reg, NV_PFB_OFFSET, NV_PFB_SIZE))
353 return 1;
354 if (WITHIN(reg, NV_PEXTDEV_OFFSET, NV_PEXTDEV_SIZE))
355 return 1;
356 if (WITHIN(reg, NV_PCRTC0_OFFSET, NV_PCRTC0_SIZE * 2))
357 return 1;
358 if (WITHIN(reg, NV_PRAMDAC0_OFFSET, NV_PRAMDAC0_SIZE * 2))
359 return 1;
360 if (dev_priv->VBIOS.pub.chip_version >= 0x17 && reg == 0x0070fff0)
361 return 1;
362 if (dev_priv->VBIOS.pub.chip_version == 0x51 &&
363 WITHIN(reg, NV_PRAMIN_OFFSET, NV_PRAMIN_SIZE))
364 return 1;
365 #undef WITHIN
366
367 NV_ERROR(dev, "========== unknown reg 0x%08X ==========\n", reg);
368 327
369 return 0; 328 return 1;
370} 329}
371 330
372static bool 331static bool
@@ -1906,7 +1865,7 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1906 1865
1907 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 1866 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
1908 1867
1909 if (dev_priv->card_type >= NV_50) 1868 if (dev_priv->card_type >= NV_40)
1910 return 1; 1869 return 1;
1911 1870
1912 /* 1871 /*
@@ -3196,16 +3155,25 @@ static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entr
3196 } 3155 }
3197#ifdef __powerpc__ 3156#ifdef __powerpc__
3198 /* Powerbook specific quirks */ 3157 /* Powerbook specific quirks */
3199 if (script == LVDS_RESET && ((dev->pci_device & 0xffff) == 0x0179 || (dev->pci_device & 0xffff) == 0x0329)) 3158 if ((dev->pci_device & 0xffff) == 0x0179 ||
3200 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3159 (dev->pci_device & 0xffff) == 0x0189 ||
3201 if ((dev->pci_device & 0xffff) == 0x0179 || (dev->pci_device & 0xffff) == 0x0189 || (dev->pci_device & 0xffff) == 0x0329) { 3160 (dev->pci_device & 0xffff) == 0x0329) {
3202 if (script == LVDS_PANEL_ON) { 3161 if (script == LVDS_RESET) {
3203 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) | (1 << 31)); 3162 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3204 bios_wr32(bios, NV_PCRTC_GPIO_EXT, bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1); 3163
3205 } 3164 } else if (script == LVDS_PANEL_ON) {
3206 if (script == LVDS_PANEL_OFF) { 3165 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3207 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) & ~(1 << 31)); 3166 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3208 bios_wr32(bios, NV_PCRTC_GPIO_EXT, bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3); 3167 | (1 << 31));
3168 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3169 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3170
3171 } else if (script == LVDS_PANEL_OFF) {
3172 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3173 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3174 & ~(1 << 31));
3175 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3176 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
3209 } 3177 }
3210 } 3178 }
3211#endif 3179#endif
@@ -3797,7 +3765,6 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3797 */ 3765 */
3798 3766
3799 struct drm_nouveau_private *dev_priv = dev->dev_private; 3767 struct drm_nouveau_private *dev_priv = dev->dev_private;
3800 struct init_exec iexec = {true, false};
3801 struct nvbios *bios = &dev_priv->VBIOS; 3768 struct nvbios *bios = &dev_priv->VBIOS;
3802 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 3769 uint8_t *table = &bios->data[bios->display.script_table_ptr];
3803 uint8_t *otable = NULL; 3770 uint8_t *otable = NULL;
@@ -3877,8 +3844,6 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3877 } 3844 }
3878 } 3845 }
3879 3846
3880 bios->display.output = dcbent;
3881
3882 if (pxclk == 0) { 3847 if (pxclk == 0) {
3883 script = ROM16(otable[6]); 3848 script = ROM16(otable[6]);
3884 if (!script) { 3849 if (!script) {
@@ -3887,7 +3852,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3887 } 3852 }
3888 3853
3889 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script); 3854 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
3890 parse_init_table(bios, script, &iexec); 3855 nouveau_bios_run_init_table(dev, script, dcbent);
3891 } else 3856 } else
3892 if (pxclk == -1) { 3857 if (pxclk == -1) {
3893 script = ROM16(otable[8]); 3858 script = ROM16(otable[8]);
@@ -3897,7 +3862,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3897 } 3862 }
3898 3863
3899 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script); 3864 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
3900 parse_init_table(bios, script, &iexec); 3865 nouveau_bios_run_init_table(dev, script, dcbent);
3901 } else 3866 } else
3902 if (pxclk == -2) { 3867 if (pxclk == -2) {
3903 if (table[4] >= 12) 3868 if (table[4] >= 12)
@@ -3910,7 +3875,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3910 } 3875 }
3911 3876
3912 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script); 3877 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
3913 parse_init_table(bios, script, &iexec); 3878 nouveau_bios_run_init_table(dev, script, dcbent);
3914 } else 3879 } else
3915 if (pxclk > 0) { 3880 if (pxclk > 0) {
3916 script = ROM16(otable[table[4] + i*6 + 2]); 3881 script = ROM16(otable[table[4] + i*6 + 2]);
@@ -3922,7 +3887,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3922 } 3887 }
3923 3888
3924 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script); 3889 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
3925 parse_init_table(bios, script, &iexec); 3890 nouveau_bios_run_init_table(dev, script, dcbent);
3926 } else 3891 } else
3927 if (pxclk < 0) { 3892 if (pxclk < 0) {
3928 script = ROM16(otable[table[4] + i*6 + 4]); 3893 script = ROM16(otable[table[4] + i*6 + 4]);
@@ -3934,7 +3899,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3934 } 3899 }
3935 3900
3936 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script); 3901 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
3937 parse_init_table(bios, script, &iexec); 3902 nouveau_bios_run_init_table(dev, script, dcbent);
3938 } 3903 }
3939 3904
3940 return 0; 3905 return 0;
@@ -5434,52 +5399,49 @@ static bool
5434parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb, 5399parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb,
5435 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5400 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5436{ 5401{
5437 if (conn != 0xf0003f00 && conn != 0xf2247f10 && conn != 0xf2204001 && 5402 switch (conn & 0x0000000f) {
5438 conn != 0xf2204301 && conn != 0xf2204311 && conn != 0xf2208001 && 5403 case 0:
5439 conn != 0xf2244001 && conn != 0xf2244301 && conn != 0xf2244311 && 5404 entry->type = OUTPUT_ANALOG;
5440 conn != 0xf4204011 && conn != 0xf4208011 && conn != 0xf4248011 && 5405 break;
5441 conn != 0xf2045ff2 && conn != 0xf2045f14 && conn != 0xf207df14 && 5406 case 1:
5442 conn != 0xf2205004 && conn != 0xf2209004) { 5407 entry->type = OUTPUT_TV;
5443 NV_ERROR(dev, "Unknown DCB 1.5 entry, please report\n"); 5408 break;
5444 5409 case 2:
5445 /* cause output setting to fail for !TV, so message is seen */ 5410 case 3:
5446 if ((conn & 0xf) != 0x1)
5447 dcb->entries = 0;
5448
5449 return false;
5450 }
5451 /* most of the below is a "best guess" atm */
5452 entry->type = conn & 0xf;
5453 if (entry->type == 2)
5454 /* another way of specifying straps based lvds... */
5455 entry->type = OUTPUT_LVDS; 5411 entry->type = OUTPUT_LVDS;
5456 if (entry->type == 4) { /* digital */ 5412 break;
5457 if (conn & 0x10) 5413 case 4:
5458 entry->type = OUTPUT_LVDS; 5414 switch ((conn & 0x000000f0) >> 4) {
5459 else 5415 case 0:
5460 entry->type = OUTPUT_TMDS; 5416 entry->type = OUTPUT_TMDS;
5417 break;
5418 case 1:
5419 entry->type = OUTPUT_LVDS;
5420 break;
5421 default:
5422 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
5423 (conn & 0x000000f0) >> 4);
5424 return false;
5425 }
5426 break;
5427 default:
5428 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5429 return false;
5461 } 5430 }
5462 /* what's in bits 5-13? could be some encoder maker thing, in tv case */ 5431
5463 entry->i2c_index = (conn >> 14) & 0xf; 5432 entry->i2c_index = (conn & 0x0003c000) >> 14;
5464 /* raw heads field is in range 0-1, so move to 1-2 */ 5433 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5465 entry->heads = ((conn >> 18) & 0x7) + 1; 5434 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5466 entry->location = (conn >> 21) & 0xf; 5435 entry->location = (conn & 0x01e00000) >> 21;
5467 /* unused: entry->bus = (conn >> 25) & 0x7; */ 5436 entry->bus = (conn & 0x0e000000) >> 25;
5468 /* set or to be same as heads -- hopefully safe enough */
5469 entry->or = entry->heads;
5470 entry->duallink_possible = false; 5437 entry->duallink_possible = false;
5471 5438
5472 switch (entry->type) { 5439 switch (entry->type) {
5473 case OUTPUT_ANALOG: 5440 case OUTPUT_ANALOG:
5474 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 5441 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5475 break; 5442 break;
5476 case OUTPUT_LVDS: 5443 case OUTPUT_TV:
5477 /* 5444 entry->tvconf.has_component_output = false;
5478 * This is probably buried in conn's unknown bits.
5479 * This will upset EDID-ful models, if they exist
5480 */
5481 entry->lvdsconf.use_straps_for_mode = true;
5482 entry->lvdsconf.use_power_scripts = true;
5483 break; 5445 break;
5484 case OUTPUT_TMDS: 5446 case OUTPUT_TMDS:
5485 /* 5447 /*
@@ -5488,8 +5450,12 @@ parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb,
5488 */ 5450 */
5489 fabricate_vga_output(dcb, entry->i2c_index, entry->heads); 5451 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5490 break; 5452 break;
5491 case OUTPUT_TV: 5453 case OUTPUT_LVDS:
5492 entry->tvconf.has_component_output = false; 5454 if ((conn & 0x00003f00) != 0x10)
5455 entry->lvdsconf.use_straps_for_mode = true;
5456 entry->lvdsconf.use_power_scripts = true;
5457 break;
5458 default:
5493 break; 5459 break;
5494 } 5460 }
5495 5461
@@ -5564,11 +5530,13 @@ void merge_like_dcb_entries(struct drm_device *dev, struct parsed_dcb *dcb)
5564 dcb->entries = newentries; 5530 dcb->entries = newentries;
5565} 5531}
5566 5532
5567static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) 5533static int
5534parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
5568{ 5535{
5536 struct drm_nouveau_private *dev_priv = dev->dev_private;
5569 struct bios_parsed_dcb *bdcb = &bios->bdcb; 5537 struct bios_parsed_dcb *bdcb = &bios->bdcb;
5570 struct parsed_dcb *dcb; 5538 struct parsed_dcb *dcb;
5571 uint16_t dcbptr, i2ctabptr = 0; 5539 uint16_t dcbptr = 0, i2ctabptr = 0;
5572 uint8_t *dcbtable; 5540 uint8_t *dcbtable;
5573 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; 5541 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5574 bool configblock = true; 5542 bool configblock = true;
@@ -5579,16 +5547,18 @@ static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool two
5579 dcb->entries = 0; 5547 dcb->entries = 0;
5580 5548
5581 /* get the offset from 0x36 */ 5549 /* get the offset from 0x36 */
5582 dcbptr = ROM16(bios->data[0x36]); 5550 if (dev_priv->card_type > NV_04) {
5551 dcbptr = ROM16(bios->data[0x36]);
5552 if (dcbptr == 0x0000)
5553 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
5554 }
5583 5555
5556 /* this situation likely means a really old card, pre DCB */
5584 if (dcbptr == 0x0) { 5557 if (dcbptr == 0x0) {
5585 NV_WARN(dev, "No output data (DCB) found in BIOS, " 5558 NV_INFO(dev, "Assuming a CRT output exists\n");
5586 "assuming a CRT output exists\n");
5587 /* this situation likely means a really old card, pre DCB */
5588 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 5559 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5589 5560
5590 if (nv04_tv_identify(dev, 5561 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
5591 bios->legacy.i2c_indices.tv) >= 0)
5592 fabricate_tv_output(dcb, twoHeads); 5562 fabricate_tv_output(dcb, twoHeads);
5593 5563
5594 return 0; 5564 return 0;
@@ -5892,9 +5862,11 @@ nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
5892 struct nvbios *bios = &dev_priv->VBIOS; 5862 struct nvbios *bios = &dev_priv->VBIOS;
5893 struct init_exec iexec = { true, false }; 5863 struct init_exec iexec = { true, false };
5894 5864
5865 mutex_lock(&bios->lock);
5895 bios->display.output = dcbent; 5866 bios->display.output = dcbent;
5896 parse_init_table(bios, table, &iexec); 5867 parse_init_table(bios, table, &iexec);
5897 bios->display.output = NULL; 5868 bios->display.output = NULL;
5869 mutex_unlock(&bios->lock);
5898} 5870}
5899 5871
5900static bool NVInitVBIOS(struct drm_device *dev) 5872static bool NVInitVBIOS(struct drm_device *dev)
@@ -5903,6 +5875,7 @@ static bool NVInitVBIOS(struct drm_device *dev)
5903 struct nvbios *bios = &dev_priv->VBIOS; 5875 struct nvbios *bios = &dev_priv->VBIOS;
5904 5876
5905 memset(bios, 0, sizeof(struct nvbios)); 5877 memset(bios, 0, sizeof(struct nvbios));
5878 mutex_init(&bios->lock);
5906 bios->dev = dev; 5879 bios->dev = dev;
5907 5880
5908 if (!NVShadowVBIOS(dev, bios->data)) 5881 if (!NVShadowVBIOS(dev, bios->data))
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 058e98c76d89..fd94bd6dc264 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -205,6 +205,8 @@ struct nvbios {
205 struct drm_device *dev; 205 struct drm_device *dev;
206 struct nouveau_bios_info pub; 206 struct nouveau_bios_info pub;
207 207
208 struct mutex lock;
209
208 uint8_t data[NV_PROM_SIZE]; 210 uint8_t data[NV_PROM_SIZE];
209 unsigned int length; 211 unsigned int length;
210 bool execute; 212 bool execute;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 0cad6d834eb2..028719fddf76 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -33,10 +33,13 @@
33#include "nouveau_drv.h" 33#include "nouveau_drv.h"
34#include "nouveau_dma.h" 34#include "nouveau_dma.h"
35 35
36#include <linux/log2.h>
37
36static void 38static void
37nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 39nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
38{ 40{
39 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 41 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
42 struct drm_device *dev = dev_priv->dev;
40 struct nouveau_bo *nvbo = nouveau_bo(bo); 43 struct nouveau_bo *nvbo = nouveau_bo(bo);
41 44
42 ttm_bo_kunmap(&nvbo->kmap); 45 ttm_bo_kunmap(&nvbo->kmap);
@@ -44,12 +47,87 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
44 if (unlikely(nvbo->gem)) 47 if (unlikely(nvbo->gem))
45 DRM_ERROR("bo %p still attached to GEM object\n", bo); 48 DRM_ERROR("bo %p still attached to GEM object\n", bo);
46 49
50 if (nvbo->tile)
51 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
52
47 spin_lock(&dev_priv->ttm.bo_list_lock); 53 spin_lock(&dev_priv->ttm.bo_list_lock);
48 list_del(&nvbo->head); 54 list_del(&nvbo->head);
49 spin_unlock(&dev_priv->ttm.bo_list_lock); 55 spin_unlock(&dev_priv->ttm.bo_list_lock);
50 kfree(nvbo); 56 kfree(nvbo);
51} 57}
52 58
59static void
60nouveau_bo_fixup_align(struct drm_device *dev,
61 uint32_t tile_mode, uint32_t tile_flags,
62 int *align, int *size)
63{
64 struct drm_nouveau_private *dev_priv = dev->dev_private;
65
66 /*
67 * Some of the tile_flags have a periodic structure of N*4096 bytes,
68 * align to to that as well as the page size. Align the size to the
69 * appropriate boundaries. This does imply that sizes are rounded up
70 * 3-7 pages, so be aware of this and do not waste memory by allocating
71 * many small buffers.
72 */
73 if (dev_priv->card_type == NV_50) {
74 uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15;
75 int i;
76
77 switch (tile_flags) {
78 case 0x1800:
79 case 0x2800:
80 case 0x4800:
81 case 0x7a00:
82 if (is_power_of_2(block_size)) {
83 for (i = 1; i < 10; i++) {
84 *align = 12 * i * block_size;
85 if (!(*align % 65536))
86 break;
87 }
88 } else {
89 for (i = 1; i < 10; i++) {
90 *align = 8 * i * block_size;
91 if (!(*align % 65536))
92 break;
93 }
94 }
95 *size = roundup(*size, *align);
96 break;
97 default:
98 break;
99 }
100
101 } else {
102 if (tile_mode) {
103 if (dev_priv->chipset >= 0x40) {
104 *align = 65536;
105 *size = roundup(*size, 64 * tile_mode);
106
107 } else if (dev_priv->chipset >= 0x30) {
108 *align = 32768;
109 *size = roundup(*size, 64 * tile_mode);
110
111 } else if (dev_priv->chipset >= 0x20) {
112 *align = 16384;
113 *size = roundup(*size, 64 * tile_mode);
114
115 } else if (dev_priv->chipset >= 0x10) {
116 *align = 16384;
117 *size = roundup(*size, 32 * tile_mode);
118 }
119 }
120 }
121
122 /* ALIGN works only on powers of two. */
123 *size = roundup(*size, PAGE_SIZE);
124
125 if (dev_priv->card_type == NV_50) {
126 *size = roundup(*size, 65536);
127 *align = max(65536, *align);
128 }
129}
130
53int 131int
54nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, 132nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
55 int size, int align, uint32_t flags, uint32_t tile_mode, 133 int size, int align, uint32_t flags, uint32_t tile_mode,
@@ -58,7 +136,7 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
58{ 136{
59 struct drm_nouveau_private *dev_priv = dev->dev_private; 137 struct drm_nouveau_private *dev_priv = dev->dev_private;
60 struct nouveau_bo *nvbo; 138 struct nouveau_bo *nvbo;
61 int ret, n = 0; 139 int ret = 0;
62 140
63 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 141 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
64 if (!nvbo) 142 if (!nvbo)
@@ -70,59 +148,14 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
70 nvbo->tile_mode = tile_mode; 148 nvbo->tile_mode = tile_mode;
71 nvbo->tile_flags = tile_flags; 149 nvbo->tile_flags = tile_flags;
72 150
73 /* 151 nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
74 * Some of the tile_flags have a periodic structure of N*4096 bytes,
75 * align to to that as well as the page size. Overallocate memory to
76 * avoid corruption of other buffer objects.
77 */
78 switch (tile_flags) {
79 case 0x1800:
80 case 0x2800:
81 case 0x4800:
82 case 0x7a00:
83 if (dev_priv->chipset >= 0xA0) {
84 /* This is based on high end cards with 448 bits
85 * memory bus, could be different elsewhere.*/
86 size += 6 * 28672;
87 /* 8 * 28672 is the actual alignment requirement,
88 * but we must also align to page size. */
89 align = 2 * 8 * 28672;
90 } else if (dev_priv->chipset >= 0x90) {
91 size += 3 * 16384;
92 align = 12 * 16834;
93 } else {
94 size += 3 * 8192;
95 /* 12 * 8192 is the actual alignment requirement,
96 * but we must also align to page size. */
97 align = 2 * 12 * 8192;
98 }
99 break;
100 default:
101 break;
102 }
103
104 align >>= PAGE_SHIFT; 152 align >>= PAGE_SHIFT;
105 153
106 size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
107 if (dev_priv->card_type == NV_50) {
108 size = (size + 65535) & ~65535;
109 if (align < (65536 / PAGE_SIZE))
110 align = (65536 / PAGE_SIZE);
111 }
112
113 if (flags & TTM_PL_FLAG_VRAM)
114 nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING;
115 if (flags & TTM_PL_FLAG_TT)
116 nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
117 nvbo->placement.fpfn = 0; 154 nvbo->placement.fpfn = 0;
118 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; 155 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
119 nvbo->placement.placement = nvbo->placements; 156 nouveau_bo_placement_set(nvbo, flags);
120 nvbo->placement.busy_placement = nvbo->placements;
121 nvbo->placement.num_placement = n;
122 nvbo->placement.num_busy_placement = n;
123 157
124 nvbo->channel = chan; 158 nvbo->channel = chan;
125 nouveau_bo_placement_set(nvbo, flags);
126 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, 159 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
127 ttm_bo_type_device, &nvbo->placement, align, 0, 160 ttm_bo_type_device, &nvbo->placement, align, 0,
128 false, NULL, size, nouveau_bo_del_ttm); 161 false, NULL, size, nouveau_bo_del_ttm);
@@ -421,6 +454,7 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
421/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access 454/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
422 * TTM_PL_{VRAM,TT} directly. 455 * TTM_PL_{VRAM,TT} directly.
423 */ 456 */
457
424static int 458static int
425nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, 459nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
426 struct nouveau_bo *nvbo, bool evict, bool no_wait, 460 struct nouveau_bo *nvbo, bool evict, bool no_wait,
@@ -435,6 +469,8 @@ nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
435 469
436 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, 470 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
437 evict, no_wait, new_mem); 471 evict, no_wait, new_mem);
472 if (nvbo->channel && nvbo->channel != chan)
473 ret = nouveau_fence_wait(fence, NULL, false, false);
438 nouveau_fence_unref((void *)&fence); 474 nouveau_fence_unref((void *)&fence);
439 return ret; 475 return ret;
440} 476}
@@ -455,11 +491,12 @@ nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
455} 491}
456 492
457static int 493static int
458nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, int no_wait, 494nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
459 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) 495 int no_wait, struct ttm_mem_reg *new_mem)
460{ 496{
461 struct nouveau_bo *nvbo = nouveau_bo(bo); 497 struct nouveau_bo *nvbo = nouveau_bo(bo);
462 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 498 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
499 struct ttm_mem_reg *old_mem = &bo->mem;
463 struct nouveau_channel *chan; 500 struct nouveau_channel *chan;
464 uint64_t src_offset, dst_offset; 501 uint64_t src_offset, dst_offset;
465 uint32_t page_count; 502 uint32_t page_count;
@@ -547,7 +584,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
547 584
548 placement.fpfn = placement.lpfn = 0; 585 placement.fpfn = placement.lpfn = 0;
549 placement.num_placement = placement.num_busy_placement = 1; 586 placement.num_placement = placement.num_busy_placement = 1;
550 placement.placement = &placement_memtype; 587 placement.placement = placement.busy_placement = &placement_memtype;
551 588
552 tmp_mem = *new_mem; 589 tmp_mem = *new_mem;
553 tmp_mem.mm_node = NULL; 590 tmp_mem.mm_node = NULL;
@@ -559,7 +596,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
559 if (ret) 596 if (ret)
560 goto out; 597 goto out;
561 598
562 ret = nouveau_bo_move_m2mf(bo, true, no_wait, &bo->mem, &tmp_mem); 599 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem);
563 if (ret) 600 if (ret)
564 goto out; 601 goto out;
565 602
@@ -585,7 +622,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
585 622
586 placement.fpfn = placement.lpfn = 0; 623 placement.fpfn = placement.lpfn = 0;
587 placement.num_placement = placement.num_busy_placement = 1; 624 placement.num_placement = placement.num_busy_placement = 1;
588 placement.placement = &placement_memtype; 625 placement.placement = placement.busy_placement = &placement_memtype;
589 626
590 tmp_mem = *new_mem; 627 tmp_mem = *new_mem;
591 tmp_mem.mm_node = NULL; 628 tmp_mem.mm_node = NULL;
@@ -597,7 +634,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
597 if (ret) 634 if (ret)
598 goto out; 635 goto out;
599 636
600 ret = nouveau_bo_move_m2mf(bo, true, no_wait, &bo->mem, new_mem); 637 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
601 if (ret) 638 if (ret)
602 goto out; 639 goto out;
603 640
@@ -612,52 +649,106 @@ out:
612} 649}
613 650
614static int 651static int
615nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, 652nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
616 bool no_wait, struct ttm_mem_reg *new_mem) 653 struct nouveau_tile_reg **new_tile)
617{ 654{
618 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 655 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
619 struct nouveau_bo *nvbo = nouveau_bo(bo);
620 struct drm_device *dev = dev_priv->dev; 656 struct drm_device *dev = dev_priv->dev;
621 struct ttm_mem_reg *old_mem = &bo->mem; 657 struct nouveau_bo *nvbo = nouveau_bo(bo);
658 uint64_t offset;
622 int ret; 659 int ret;
623 660
624 if (dev_priv->card_type == NV_50 && new_mem->mem_type == TTM_PL_VRAM && 661 if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
625 !nvbo->no_vm) { 662 /* Nothing to do. */
626 uint64_t offset = new_mem->mm_node->start << PAGE_SHIFT; 663 *new_tile = NULL;
664 return 0;
665 }
666
667 offset = new_mem->mm_node->start << PAGE_SHIFT;
627 668
669 if (dev_priv->card_type == NV_50) {
628 ret = nv50_mem_vm_bind_linear(dev, 670 ret = nv50_mem_vm_bind_linear(dev,
629 offset + dev_priv->vm_vram_base, 671 offset + dev_priv->vm_vram_base,
630 new_mem->size, nvbo->tile_flags, 672 new_mem->size, nvbo->tile_flags,
631 offset); 673 offset);
632 if (ret) 674 if (ret)
633 return ret; 675 return ret;
676
677 } else if (dev_priv->card_type >= NV_10) {
678 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
679 nvbo->tile_mode);
680 }
681
682 return 0;
683}
684
685static void
686nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
687 struct nouveau_tile_reg *new_tile,
688 struct nouveau_tile_reg **old_tile)
689{
690 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
691 struct drm_device *dev = dev_priv->dev;
692
693 if (dev_priv->card_type >= NV_10 &&
694 dev_priv->card_type < NV_50) {
695 if (*old_tile)
696 nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
697
698 *old_tile = new_tile;
634 } 699 }
700}
701
702static int
703nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
704 bool no_wait, struct ttm_mem_reg *new_mem)
705{
706 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
707 struct nouveau_bo *nvbo = nouveau_bo(bo);
708 struct ttm_mem_reg *old_mem = &bo->mem;
709 struct nouveau_tile_reg *new_tile = NULL;
710 int ret = 0;
711
712 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
713 if (ret)
714 return ret;
635 715
716 /* Software copy if the card isn't up and running yet. */
636 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE || 717 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
637 !dev_priv->channel) 718 !dev_priv->channel) {
638 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 719 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
720 goto out;
721 }
639 722
723 /* Fake bo copy. */
640 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 724 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
641 BUG_ON(bo->mem.mm_node != NULL); 725 BUG_ON(bo->mem.mm_node != NULL);
642 bo->mem = *new_mem; 726 bo->mem = *new_mem;
643 new_mem->mm_node = NULL; 727 new_mem->mm_node = NULL;
644 return 0; 728 goto out;
645 } 729 }
646 730
647 if (new_mem->mem_type == TTM_PL_SYSTEM) { 731 /* Hardware assisted copy. */
648 if (old_mem->mem_type == TTM_PL_SYSTEM) 732 if (new_mem->mem_type == TTM_PL_SYSTEM)
649 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 733 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem);
650 if (nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem)) 734 else if (old_mem->mem_type == TTM_PL_SYSTEM)
651 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 735 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem);
652 } else if (old_mem->mem_type == TTM_PL_SYSTEM) { 736 else
653 if (nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem)) 737 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
654 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
655 } else {
656 if (nouveau_bo_move_m2mf(bo, evict, no_wait, old_mem, new_mem))
657 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
658 }
659 738
660 return 0; 739 if (!ret)
740 goto out;
741
742 /* Fallback to software copy. */
743 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
744
745out:
746 if (ret)
747 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
748 else
749 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
750
751 return ret;
661} 752}
662 753
663static int 754static int
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 9aaa972f8822..2281f99da7fc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -158,6 +158,8 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
158 return ret; 158 return ret;
159 } 159 }
160 160
161 nouveau_dma_pre_init(chan);
162
161 /* Locate channel's user control regs */ 163 /* Locate channel's user control regs */
162 if (dev_priv->card_type < NV_40) 164 if (dev_priv->card_type < NV_40)
163 user = NV03_USER(channel); 165 user = NV03_USER(channel);
@@ -235,47 +237,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
235 return 0; 237 return 0;
236} 238}
237 239
238int
239nouveau_channel_idle(struct nouveau_channel *chan)
240{
241 struct drm_device *dev = chan->dev;
242 struct drm_nouveau_private *dev_priv = dev->dev_private;
243 struct nouveau_engine *engine = &dev_priv->engine;
244 uint32_t caches;
245 int idle;
246
247 if (!chan) {
248 NV_ERROR(dev, "no channel...\n");
249 return 1;
250 }
251
252 caches = nv_rd32(dev, NV03_PFIFO_CACHES);
253 nv_wr32(dev, NV03_PFIFO_CACHES, caches & ~1);
254
255 if (engine->fifo.channel_id(dev) != chan->id) {
256 struct nouveau_gpuobj *ramfc =
257 chan->ramfc ? chan->ramfc->gpuobj : NULL;
258
259 if (!ramfc) {
260 NV_ERROR(dev, "No RAMFC for channel %d\n", chan->id);
261 return 1;
262 }
263
264 engine->instmem.prepare_access(dev, false);
265 if (nv_ro32(dev, ramfc, 0) != nv_ro32(dev, ramfc, 1))
266 idle = 0;
267 else
268 idle = 1;
269 engine->instmem.finish_access(dev);
270 } else {
271 idle = (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET) ==
272 nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
273 }
274
275 nv_wr32(dev, NV03_PFIFO_CACHES, caches);
276 return idle;
277}
278
279/* stops a fifo */ 240/* stops a fifo */
280void 241void
281nouveau_channel_free(struct nouveau_channel *chan) 242nouveau_channel_free(struct nouveau_channel *chan)
@@ -317,12 +278,11 @@ nouveau_channel_free(struct nouveau_channel *chan)
317 /* Ensure the channel is no longer active on the GPU */ 278 /* Ensure the channel is no longer active on the GPU */
318 pfifo->reassign(dev, false); 279 pfifo->reassign(dev, false);
319 280
320 if (pgraph->channel(dev) == chan) { 281 pgraph->fifo_access(dev, false);
321 pgraph->fifo_access(dev, false); 282 if (pgraph->channel(dev) == chan)
322 pgraph->unload_context(dev); 283 pgraph->unload_context(dev);
323 pgraph->fifo_access(dev, true);
324 }
325 pgraph->destroy_context(chan); 284 pgraph->destroy_context(chan);
285 pgraph->fifo_access(dev, true);
326 286
327 if (pfifo->channel_id(dev) == chan->id) { 287 if (pfifo->channel_id(dev) == chan->id) {
328 pfifo->disable(dev); 288 pfifo->disable(dev);
@@ -414,7 +374,9 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
414 init->subchan[0].grclass = 0x0039; 374 init->subchan[0].grclass = 0x0039;
415 else 375 else
416 init->subchan[0].grclass = 0x5039; 376 init->subchan[0].grclass = 0x5039;
417 init->nr_subchan = 1; 377 init->subchan[1].handle = NvSw;
378 init->subchan[1].grclass = NV_SW;
379 init->nr_subchan = 2;
418 380
419 /* Named memory object area */ 381 /* Named memory object area */
420 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem, 382 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 5a10deb8bdbd..d2f63353ea97 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -24,9 +24,12 @@
24 * 24 *
25 */ 25 */
26 26
27#include <acpi/button.h>
28
27#include "drmP.h" 29#include "drmP.h"
28#include "drm_edid.h" 30#include "drm_edid.h"
29#include "drm_crtc_helper.h" 31#include "drm_crtc_helper.h"
32
30#include "nouveau_reg.h" 33#include "nouveau_reg.h"
31#include "nouveau_drv.h" 34#include "nouveau_drv.h"
32#include "nouveau_encoder.h" 35#include "nouveau_encoder.h"
@@ -83,14 +86,17 @@ nouveau_encoder_connector_get(struct nouveau_encoder *encoder)
83static void 86static void
84nouveau_connector_destroy(struct drm_connector *drm_connector) 87nouveau_connector_destroy(struct drm_connector *drm_connector)
85{ 88{
86 struct nouveau_connector *connector = nouveau_connector(drm_connector); 89 struct nouveau_connector *nv_connector =
87 struct drm_device *dev = connector->base.dev; 90 nouveau_connector(drm_connector);
91 struct drm_device *dev;
88 92
89 NV_DEBUG_KMS(dev, "\n"); 93 if (!nv_connector)
90
91 if (!connector)
92 return; 94 return;
93 95
96 dev = nv_connector->base.dev;
97 NV_DEBUG_KMS(dev, "\n");
98
99 kfree(nv_connector->edid);
94 drm_sysfs_connector_remove(drm_connector); 100 drm_sysfs_connector_remove(drm_connector);
95 drm_connector_cleanup(drm_connector); 101 drm_connector_cleanup(drm_connector);
96 kfree(drm_connector); 102 kfree(drm_connector);
@@ -233,10 +239,21 @@ nouveau_connector_detect(struct drm_connector *connector)
233 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 239 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
234 nv_encoder = find_encoder_by_type(connector, OUTPUT_LVDS); 240 nv_encoder = find_encoder_by_type(connector, OUTPUT_LVDS);
235 if (nv_encoder && nv_connector->native_mode) { 241 if (nv_encoder && nv_connector->native_mode) {
242#ifdef CONFIG_ACPI
243 if (!nouveau_ignorelid && !acpi_lid_open())
244 return connector_status_disconnected;
245#endif
236 nouveau_connector_set_encoder(connector, nv_encoder); 246 nouveau_connector_set_encoder(connector, nv_encoder);
237 return connector_status_connected; 247 return connector_status_connected;
238 } 248 }
239 249
250 /* Cleanup the previous EDID block. */
251 if (nv_connector->edid) {
252 drm_mode_connector_update_edid_property(connector, NULL);
253 kfree(nv_connector->edid);
254 nv_connector->edid = NULL;
255 }
256
240 i2c = nouveau_connector_ddc_detect(connector, &nv_encoder); 257 i2c = nouveau_connector_ddc_detect(connector, &nv_encoder);
241 if (i2c) { 258 if (i2c) {
242 nouveau_connector_ddc_prepare(connector, &flags); 259 nouveau_connector_ddc_prepare(connector, &flags);
@@ -247,7 +264,7 @@ nouveau_connector_detect(struct drm_connector *connector)
247 if (!nv_connector->edid) { 264 if (!nv_connector->edid) {
248 NV_ERROR(dev, "DDC responded, but no EDID for %s\n", 265 NV_ERROR(dev, "DDC responded, but no EDID for %s\n",
249 drm_get_connector_name(connector)); 266 drm_get_connector_name(connector));
250 return connector_status_disconnected; 267 goto detect_analog;
251 } 268 }
252 269
253 if (nv_encoder->dcb->type == OUTPUT_DP && 270 if (nv_encoder->dcb->type == OUTPUT_DP &&
@@ -281,6 +298,7 @@ nouveau_connector_detect(struct drm_connector *connector)
281 return connector_status_connected; 298 return connector_status_connected;
282 } 299 }
283 300
301detect_analog:
284 nv_encoder = find_encoder_by_type(connector, OUTPUT_ANALOG); 302 nv_encoder = find_encoder_by_type(connector, OUTPUT_ANALOG);
285 if (!nv_encoder) 303 if (!nv_encoder)
286 nv_encoder = find_encoder_by_type(connector, OUTPUT_TV); 304 nv_encoder = find_encoder_by_type(connector, OUTPUT_TV);
@@ -687,8 +705,12 @@ nouveau_connector_create_lvds(struct drm_device *dev,
687 */ 705 */
688 if (!nv_connector->edid && !nv_connector->native_mode && 706 if (!nv_connector->edid && !nv_connector->native_mode &&
689 !dev_priv->VBIOS.pub.fp_no_ddc) { 707 !dev_priv->VBIOS.pub.fp_no_ddc) {
690 nv_connector->edid = 708 struct edid *edid =
691 (struct edid *)nouveau_bios_embedded_edid(dev); 709 (struct edid *)nouveau_bios_embedded_edid(dev);
710 if (edid) {
711 nv_connector->edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
712 *(nv_connector->edid) = *edid;
713 }
692 } 714 }
693 715
694 if (!nv_connector->edid) 716 if (!nv_connector->edid)
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
index 703553687b20..50d9e67745af 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -29,12 +29,22 @@
29#include "nouveau_drv.h" 29#include "nouveau_drv.h"
30#include "nouveau_dma.h" 30#include "nouveau_dma.h"
31 31
32void
33nouveau_dma_pre_init(struct nouveau_channel *chan)
34{
35 chan->dma.max = (chan->pushbuf_bo->bo.mem.size >> 2) - 2;
36 chan->dma.put = 0;
37 chan->dma.cur = chan->dma.put;
38 chan->dma.free = chan->dma.max - chan->dma.cur;
39}
40
32int 41int
33nouveau_dma_init(struct nouveau_channel *chan) 42nouveau_dma_init(struct nouveau_channel *chan)
34{ 43{
35 struct drm_device *dev = chan->dev; 44 struct drm_device *dev = chan->dev;
36 struct drm_nouveau_private *dev_priv = dev->dev_private; 45 struct drm_nouveau_private *dev_priv = dev->dev_private;
37 struct nouveau_gpuobj *m2mf = NULL; 46 struct nouveau_gpuobj *m2mf = NULL;
47 struct nouveau_gpuobj *nvsw = NULL;
38 int ret, i; 48 int ret, i;
39 49
40 /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */ 50 /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
@@ -47,6 +57,15 @@ nouveau_dma_init(struct nouveau_channel *chan)
47 if (ret) 57 if (ret)
48 return ret; 58 return ret;
49 59
60 /* Create an NV_SW object for various sync purposes */
61 ret = nouveau_gpuobj_sw_new(chan, NV_SW, &nvsw);
62 if (ret)
63 return ret;
64
65 ret = nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL);
66 if (ret)
67 return ret;
68
50 /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */ 69 /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
51 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy); 70 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
52 if (ret) 71 if (ret)
@@ -64,12 +83,6 @@ nouveau_dma_init(struct nouveau_channel *chan)
64 return ret; 83 return ret;
65 } 84 }
66 85
67 /* Initialise DMA vars */
68 chan->dma.max = (chan->pushbuf_bo->bo.mem.size >> 2) - 2;
69 chan->dma.put = 0;
70 chan->dma.cur = chan->dma.put;
71 chan->dma.free = chan->dma.max - chan->dma.cur;
72
73 /* Insert NOPS for NOUVEAU_DMA_SKIPS */ 86 /* Insert NOPS for NOUVEAU_DMA_SKIPS */
74 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 87 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
75 if (ret) 88 if (ret)
@@ -87,6 +100,13 @@ nouveau_dma_init(struct nouveau_channel *chan)
87 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1); 100 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
88 OUT_RING(chan, NvNotify0); 101 OUT_RING(chan, NvNotify0);
89 102
103 /* Initialise NV_SW */
104 ret = RING_SPACE(chan, 2);
105 if (ret)
106 return ret;
107 BEGIN_RING(chan, NvSubSw, 0, 1);
108 OUT_RING(chan, NvSw);
109
90 /* Sit back and pray the channel works.. */ 110 /* Sit back and pray the channel works.. */
91 FIRE_RING(chan); 111 FIRE_RING(chan);
92 112
@@ -106,47 +126,52 @@ OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
106 chan->dma.cur += nr_dwords; 126 chan->dma.cur += nr_dwords;
107} 127}
108 128
109static inline bool 129/* Fetch and adjust GPU GET pointer
110READ_GET(struct nouveau_channel *chan, uint32_t *get) 130 *
131 * Returns:
132 * value >= 0, the adjusted GET pointer
133 * -EINVAL if GET pointer currently outside main push buffer
134 * -EBUSY if timeout exceeded
135 */
136static inline int
137READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
111{ 138{
112 uint32_t val; 139 uint32_t val;
113 140
114 val = nvchan_rd32(chan, chan->user_get); 141 val = nvchan_rd32(chan, chan->user_get);
115 if (val < chan->pushbuf_base || 142
116 val >= chan->pushbuf_base + chan->pushbuf_bo->bo.mem.size) { 143 /* reset counter as long as GET is still advancing, this is
117 /* meaningless to dma_wait() except to know whether the 144 * to avoid misdetecting a GPU lockup if the GPU happens to
118 * GPU has stalled or not 145 * just be processing an operation that takes a long time
119 */ 146 */
120 *get = val; 147 if (val != *prev_get) {
121 return false; 148 *prev_get = val;
149 *timeout = 0;
150 }
151
152 if ((++*timeout & 0xff) == 0) {
153 DRM_UDELAY(1);
154 if (*timeout > 100000)
155 return -EBUSY;
122 } 156 }
123 157
124 *get = (val - chan->pushbuf_base) >> 2; 158 if (val < chan->pushbuf_base ||
125 return true; 159 val > chan->pushbuf_base + (chan->dma.max << 2))
160 return -EINVAL;
161
162 return (val - chan->pushbuf_base) >> 2;
126} 163}
127 164
128int 165int
129nouveau_dma_wait(struct nouveau_channel *chan, int size) 166nouveau_dma_wait(struct nouveau_channel *chan, int size)
130{ 167{
131 uint32_t get, prev_get = 0, cnt = 0; 168 uint32_t prev_get = 0, cnt = 0;
132 bool get_valid; 169 int get;
133 170
134 while (chan->dma.free < size) { 171 while (chan->dma.free < size) {
135 /* reset counter as long as GET is still advancing, this is 172 get = READ_GET(chan, &prev_get, &cnt);
136 * to avoid misdetecting a GPU lockup if the GPU happens to 173 if (unlikely(get == -EBUSY))
137 * just be processing an operation that takes a long time 174 return -EBUSY;
138 */
139 get_valid = READ_GET(chan, &get);
140 if (get != prev_get) {
141 prev_get = get;
142 cnt = 0;
143 }
144
145 if ((++cnt & 0xff) == 0) {
146 DRM_UDELAY(1);
147 if (cnt > 100000)
148 return -EBUSY;
149 }
150 175
151 /* loop until we have a usable GET pointer. the value 176 /* loop until we have a usable GET pointer. the value
152 * we read from the GPU may be outside the main ring if 177 * we read from the GPU may be outside the main ring if
@@ -157,7 +182,7 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size)
157 * from the SKIPS area, so the code below doesn't have to deal 182 * from the SKIPS area, so the code below doesn't have to deal
158 * with some fun corner cases. 183 * with some fun corner cases.
159 */ 184 */
160 if (!get_valid || get < NOUVEAU_DMA_SKIPS) 185 if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
161 continue; 186 continue;
162 187
163 if (get <= chan->dma.cur) { 188 if (get <= chan->dma.cur) {
@@ -183,6 +208,19 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size)
183 * after processing the currently pending commands. 208 * after processing the currently pending commands.
184 */ 209 */
185 OUT_RING(chan, chan->pushbuf_base | 0x20000000); 210 OUT_RING(chan, chan->pushbuf_base | 0x20000000);
211
212 /* wait for GET to depart from the skips area.
213 * prevents writing GET==PUT and causing a race
214 * condition that causes us to think the GPU is
215 * idle when it's not.
216 */
217 do {
218 get = READ_GET(chan, &prev_get, &cnt);
219 if (unlikely(get == -EBUSY))
220 return -EBUSY;
221 if (unlikely(get == -EINVAL))
222 continue;
223 } while (get <= NOUVEAU_DMA_SKIPS);
186 WRITE_PUT(NOUVEAU_DMA_SKIPS); 224 WRITE_PUT(NOUVEAU_DMA_SKIPS);
187 225
188 /* we're now submitting commands at the start of 226 /* we're now submitting commands at the start of
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h
index 04e85d8f757e..dabfd655f93e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.h
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.h
@@ -46,10 +46,11 @@
46/* Hardcoded object assignments to subchannels (subchannel id). */ 46/* Hardcoded object assignments to subchannels (subchannel id). */
47enum { 47enum {
48 NvSubM2MF = 0, 48 NvSubM2MF = 0,
49 NvSub2D = 1, 49 NvSubSw = 1,
50 NvSubCtxSurf2D = 1, 50 NvSub2D = 2,
51 NvSubGdiRect = 2, 51 NvSubCtxSurf2D = 2,
52 NvSubImageBlit = 3 52 NvSubGdiRect = 3,
53 NvSubImageBlit = 4
53}; 54};
54 55
55/* Object handles. */ 56/* Object handles. */
@@ -67,6 +68,7 @@ enum {
67 NvClipRect = 0x8000000b, 68 NvClipRect = 0x8000000b,
68 NvGdiRect = 0x8000000c, 69 NvGdiRect = 0x8000000c,
69 NvImageBlit = 0x8000000d, 70 NvImageBlit = 0x8000000d,
71 NvSw = 0x8000000e,
70 72
71 /* G80+ display objects */ 73 /* G80+ display objects */
72 NvEvoVRAM = 0x01000000, 74 NvEvoVRAM = 0x01000000,
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index 9e2926c48579..f954ad93e81f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -490,7 +490,8 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
490 if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) { 490 if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) {
491 NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n", 491 NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
492 nv_rd32(dev, NV50_AUXCH_CTRL(index))); 492 nv_rd32(dev, NV50_AUXCH_CTRL(index)));
493 return -EBUSY; 493 ret = -EBUSY;
494 goto out;
494 } 495 }
495 496
496 udelay(400); 497 udelay(400);
@@ -502,6 +503,11 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
502 } 503 }
503 504
504 if (cmd & 1) { 505 if (cmd & 1) {
506 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
507 ret = -EREMOTEIO;
508 goto out;
509 }
510
505 for (i = 0; i < 4; i++) { 511 for (i = 0; i < 4; i++) {
506 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i)); 512 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
507 NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]); 513 NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index 06eb993e0883..da3b93b84502 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -56,7 +56,7 @@ int nouveau_vram_pushbuf;
56module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 56module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
57 57
58MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM"); 58MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
59int nouveau_vram_notify; 59int nouveau_vram_notify = 1;
60module_param_named(vram_notify, nouveau_vram_notify, int, 0400); 60module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
61 61
62MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)"); 62MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
@@ -71,6 +71,18 @@ MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
71int nouveau_uscript_tmds = -1; 71int nouveau_uscript_tmds = -1;
72module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400); 72module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
73 73
74MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
75int nouveau_ignorelid = 0;
76module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
77
78MODULE_PARM_DESC(noagp, "Disable all acceleration");
79int nouveau_noaccel = 0;
80module_param_named(noaccel, nouveau_noaccel, int, 0400);
81
82MODULE_PARM_DESC(noagp, "Disable fbcon acceleration");
83int nouveau_nofbaccel = 0;
84module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
85
74MODULE_PARM_DESC(tv_norm, "Default TV norm.\n" 86MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
75 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n" 87 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
76 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n" 88 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 5f8cbb79c499..1c15ef37b71c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -59,11 +59,19 @@ struct nouveau_grctx;
59#define MAX_NUM_DCB_ENTRIES 16 59#define MAX_NUM_DCB_ENTRIES 16
60 60
61#define NOUVEAU_MAX_CHANNEL_NR 128 61#define NOUVEAU_MAX_CHANNEL_NR 128
62#define NOUVEAU_MAX_TILE_NR 15
62 63
63#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
64#define NV50_VM_BLOCK (512*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL)
65#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
66 67
68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
67struct nouveau_bo { 75struct nouveau_bo {
68 struct ttm_buffer_object bo; 76 struct ttm_buffer_object bo;
69 struct ttm_placement placement; 77 struct ttm_placement placement;
@@ -83,6 +91,7 @@ struct nouveau_bo {
83 91
84 uint32_t tile_mode; 92 uint32_t tile_mode;
85 uint32_t tile_flags; 93 uint32_t tile_flags;
94 struct nouveau_tile_reg *tile;
86 95
87 struct drm_gem_object *gem; 96 struct drm_gem_object *gem;
88 struct drm_file *cpu_filp; 97 struct drm_file *cpu_filp;
@@ -277,8 +286,13 @@ struct nouveau_timer_engine {
277}; 286};
278 287
279struct nouveau_fb_engine { 288struct nouveau_fb_engine {
289 int num_tiles;
290
280 int (*init)(struct drm_device *dev); 291 int (*init)(struct drm_device *dev);
281 void (*takedown)(struct drm_device *dev); 292 void (*takedown)(struct drm_device *dev);
293
294 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
295 uint32_t size, uint32_t pitch);
282}; 296};
283 297
284struct nouveau_fifo_engine { 298struct nouveau_fifo_engine {
@@ -292,6 +306,8 @@ struct nouveau_fifo_engine {
292 void (*disable)(struct drm_device *); 306 void (*disable)(struct drm_device *);
293 void (*enable)(struct drm_device *); 307 void (*enable)(struct drm_device *);
294 bool (*reassign)(struct drm_device *, bool enable); 308 bool (*reassign)(struct drm_device *, bool enable);
309 bool (*cache_flush)(struct drm_device *dev);
310 bool (*cache_pull)(struct drm_device *dev, bool enable);
295 311
296 int (*channel_id)(struct drm_device *); 312 int (*channel_id)(struct drm_device *);
297 313
@@ -330,6 +346,9 @@ struct nouveau_pgraph_engine {
330 void (*destroy_context)(struct nouveau_channel *); 346 void (*destroy_context)(struct nouveau_channel *);
331 int (*load_context)(struct nouveau_channel *); 347 int (*load_context)(struct nouveau_channel *);
332 int (*unload_context)(struct drm_device *); 348 int (*unload_context)(struct drm_device *);
349
350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
351 uint32_t size, uint32_t pitch);
333}; 352};
334 353
335struct nouveau_engine { 354struct nouveau_engine {
@@ -490,6 +509,8 @@ struct drm_nouveau_private {
490 void __iomem *ramin; 509 void __iomem *ramin;
491 uint32_t ramin_size; 510 uint32_t ramin_size;
492 511
512 struct nouveau_bo *vga_ram;
513
493 struct workqueue_struct *wq; 514 struct workqueue_struct *wq;
494 struct work_struct irq_work; 515 struct work_struct irq_work;
495 516
@@ -548,6 +569,12 @@ struct drm_nouveau_private {
548 unsigned long sg_handle; 569 unsigned long sg_handle;
549 } gart_info; 570 } gart_info;
550 571
572 /* nv10-nv40 tiling regions */
573 struct {
574 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
575 spinlock_t lock;
576 } tile;
577
551 /* G8x/G9x virtual address space */ 578 /* G8x/G9x virtual address space */
552 uint64_t vm_gart_base; 579 uint64_t vm_gart_base;
553 uint64_t vm_gart_size; 580 uint64_t vm_gart_size;
@@ -556,6 +583,7 @@ struct drm_nouveau_private {
556 uint64_t vm_end; 583 uint64_t vm_end;
557 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 584 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
558 int vm_vram_pt_nr; 585 int vm_vram_pt_nr;
586 uint64_t vram_sys_base;
559 587
560 /* the mtrr covering the FB */ 588 /* the mtrr covering the FB */
561 int fb_mtrr; 589 int fb_mtrr;
@@ -650,6 +678,9 @@ extern char *nouveau_tv_norm;
650extern int nouveau_reg_debug; 678extern int nouveau_reg_debug;
651extern char *nouveau_vbios; 679extern char *nouveau_vbios;
652extern int nouveau_ctxfw; 680extern int nouveau_ctxfw;
681extern int nouveau_ignorelid;
682extern int nouveau_nofbaccel;
683extern int nouveau_noaccel;
653 684
654/* nouveau_state.c */ 685/* nouveau_state.c */
655extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 686extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
@@ -685,6 +716,13 @@ extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
685extern int nouveau_mem_init(struct drm_device *); 716extern int nouveau_mem_init(struct drm_device *);
686extern int nouveau_mem_init_agp(struct drm_device *); 717extern int nouveau_mem_init_agp(struct drm_device *);
687extern void nouveau_mem_close(struct drm_device *); 718extern void nouveau_mem_close(struct drm_device *);
719extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
720 uint32_t addr,
721 uint32_t size,
722 uint32_t pitch);
723extern void nv10_mem_expire_tiling(struct drm_device *dev,
724 struct nouveau_tile_reg *tile,
725 struct nouveau_fence *fence);
688extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 726extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
689 uint32_t size, uint32_t flags, 727 uint32_t size, uint32_t flags,
690 uint64_t phys); 728 uint64_t phys);
@@ -713,7 +751,6 @@ extern int nouveau_channel_alloc(struct drm_device *dev,
713 struct drm_file *file_priv, 751 struct drm_file *file_priv,
714 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 752 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
715extern void nouveau_channel_free(struct nouveau_channel *); 753extern void nouveau_channel_free(struct nouveau_channel *);
716extern int nouveau_channel_idle(struct nouveau_channel *chan);
717 754
718/* nouveau_object.c */ 755/* nouveau_object.c */
719extern int nouveau_gpuobj_early_init(struct drm_device *); 756extern int nouveau_gpuobj_early_init(struct drm_device *);
@@ -756,6 +793,8 @@ extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
756 uint32_t *o_ret); 793 uint32_t *o_ret);
757extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 794extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
758 struct nouveau_gpuobj **); 795 struct nouveau_gpuobj **);
796extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
797 struct nouveau_gpuobj **);
759extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 798extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
760 struct drm_file *); 799 struct drm_file *);
761extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 800extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
@@ -804,6 +843,7 @@ nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
804#endif 843#endif
805 844
806/* nouveau_dma.c */ 845/* nouveau_dma.c */
846extern void nouveau_dma_pre_init(struct nouveau_channel *);
807extern int nouveau_dma_init(struct nouveau_channel *); 847extern int nouveau_dma_init(struct nouveau_channel *);
808extern int nouveau_dma_wait(struct nouveau_channel *, int size); 848extern int nouveau_dma_wait(struct nouveau_channel *, int size);
809 849
@@ -879,16 +919,22 @@ extern void nv04_fb_takedown(struct drm_device *);
879/* nv10_fb.c */ 919/* nv10_fb.c */
880extern int nv10_fb_init(struct drm_device *); 920extern int nv10_fb_init(struct drm_device *);
881extern void nv10_fb_takedown(struct drm_device *); 921extern void nv10_fb_takedown(struct drm_device *);
922extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
923 uint32_t, uint32_t);
882 924
883/* nv40_fb.c */ 925/* nv40_fb.c */
884extern int nv40_fb_init(struct drm_device *); 926extern int nv40_fb_init(struct drm_device *);
885extern void nv40_fb_takedown(struct drm_device *); 927extern void nv40_fb_takedown(struct drm_device *);
928extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
929 uint32_t, uint32_t);
886 930
887/* nv04_fifo.c */ 931/* nv04_fifo.c */
888extern int nv04_fifo_init(struct drm_device *); 932extern int nv04_fifo_init(struct drm_device *);
889extern void nv04_fifo_disable(struct drm_device *); 933extern void nv04_fifo_disable(struct drm_device *);
890extern void nv04_fifo_enable(struct drm_device *); 934extern void nv04_fifo_enable(struct drm_device *);
891extern bool nv04_fifo_reassign(struct drm_device *, bool); 935extern bool nv04_fifo_reassign(struct drm_device *, bool);
936extern bool nv04_fifo_cache_flush(struct drm_device *);
937extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
892extern int nv04_fifo_channel_id(struct drm_device *); 938extern int nv04_fifo_channel_id(struct drm_device *);
893extern int nv04_fifo_create_context(struct nouveau_channel *); 939extern int nv04_fifo_create_context(struct nouveau_channel *);
894extern void nv04_fifo_destroy_context(struct nouveau_channel *); 940extern void nv04_fifo_destroy_context(struct nouveau_channel *);
@@ -941,6 +987,8 @@ extern void nv10_graph_destroy_context(struct nouveau_channel *);
941extern int nv10_graph_load_context(struct nouveau_channel *); 987extern int nv10_graph_load_context(struct nouveau_channel *);
942extern int nv10_graph_unload_context(struct drm_device *); 988extern int nv10_graph_unload_context(struct drm_device *);
943extern void nv10_graph_context_switch(struct drm_device *); 989extern void nv10_graph_context_switch(struct drm_device *);
990extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
991 uint32_t, uint32_t);
944 992
945/* nv20_graph.c */ 993/* nv20_graph.c */
946extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 994extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
@@ -952,6 +1000,8 @@ extern int nv20_graph_unload_context(struct drm_device *);
952extern int nv20_graph_init(struct drm_device *); 1000extern int nv20_graph_init(struct drm_device *);
953extern void nv20_graph_takedown(struct drm_device *); 1001extern void nv20_graph_takedown(struct drm_device *);
954extern int nv30_graph_init(struct drm_device *); 1002extern int nv30_graph_init(struct drm_device *);
1003extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1004 uint32_t, uint32_t);
955 1005
956/* nv40_graph.c */ 1006/* nv40_graph.c */
957extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1007extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
@@ -963,6 +1013,8 @@ extern void nv40_graph_destroy_context(struct nouveau_channel *);
963extern int nv40_graph_load_context(struct nouveau_channel *); 1013extern int nv40_graph_load_context(struct nouveau_channel *);
964extern int nv40_graph_unload_context(struct drm_device *); 1014extern int nv40_graph_unload_context(struct drm_device *);
965extern void nv40_grctx_init(struct nouveau_grctx *); 1015extern void nv40_grctx_init(struct nouveau_grctx *);
1016extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1017 uint32_t, uint32_t);
966 1018
967/* nv50_graph.c */ 1019/* nv50_graph.c */
968extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1020extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
@@ -1030,8 +1082,7 @@ extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1030 1082
1031/* nv04_dac.c */ 1083/* nv04_dac.c */
1032extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry); 1084extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1033extern enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder, 1085extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1034 struct drm_connector *connector);
1035extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1086extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1036extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1087extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1037 1088
@@ -1049,9 +1100,6 @@ extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1049 1100
1050/* nv17_tv.c */ 1101/* nv17_tv.c */
1051extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry); 1102extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1052extern enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
1053 struct drm_connector *connector,
1054 uint32_t pin_mask);
1055 1103
1056/* nv04_display.c */ 1104/* nv04_display.c */
1057extern int nv04_display_create(struct drm_device *); 1105extern int nv04_display_create(struct drm_device *);
@@ -1290,14 +1338,14 @@ nv_two_reg_pll(struct drm_device *dev)
1290 return false; 1338 return false;
1291} 1339}
1292 1340
1293#define NV50_NVSW 0x0000506e 1341#define NV_SW 0x0000506e
1294#define NV50_NVSW_DMA_SEMAPHORE 0x00000060 1342#define NV_SW_DMA_SEMAPHORE 0x00000060
1295#define NV50_NVSW_SEMAPHORE_OFFSET 0x00000064 1343#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1296#define NV50_NVSW_SEMAPHORE_ACQUIRE 0x00000068 1344#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1297#define NV50_NVSW_SEMAPHORE_RELEASE 0x0000006c 1345#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1298#define NV50_NVSW_DMA_VBLSEM 0x0000018c 1346#define NV_SW_DMA_VBLSEM 0x0000018c
1299#define NV50_NVSW_VBLSEM_OFFSET 0x00000400 1347#define NV_SW_VBLSEM_OFFSET 0x00000400
1300#define NV50_NVSW_VBLSEM_RELEASE_VALUE 0x00000404 1348#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1301#define NV50_NVSW_VBLSEM_RELEASE 0x00000408 1349#define NV_SW_VBLSEM_RELEASE 0x00000408
1302 1350
1303#endif /* __NOUVEAU_DRV_H__ */ 1351#endif /* __NOUVEAU_DRV_H__ */
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 84af25c238b6..ea879a2efef3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -64,8 +64,7 @@ nouveau_fbcon_sync(struct fb_info *info)
64 return 0; 64 return 0;
65 65
66 if (RING_SPACE(chan, 4)) { 66 if (RING_SPACE(chan, 4)) {
67 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 67 nouveau_fbcon_gpu_lockup(info);
68 info->flags |= FBINFO_HWACCEL_DISABLED;
69 return 0; 68 return 0;
70 } 69 }
71 70
@@ -86,8 +85,7 @@ nouveau_fbcon_sync(struct fb_info *info)
86 } 85 }
87 86
88 if (ret) { 87 if (ret) {
89 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 88 nouveau_fbcon_gpu_lockup(info);
90 info->flags |= FBINFO_HWACCEL_DISABLED;
91 return 0; 89 return 0;
92 } 90 }
93 91
@@ -109,6 +107,34 @@ static struct fb_ops nouveau_fbcon_ops = {
109 .fb_setcmap = drm_fb_helper_setcmap, 107 .fb_setcmap = drm_fb_helper_setcmap,
110}; 108};
111 109
110static struct fb_ops nv04_fbcon_ops = {
111 .owner = THIS_MODULE,
112 .fb_check_var = drm_fb_helper_check_var,
113 .fb_set_par = drm_fb_helper_set_par,
114 .fb_setcolreg = drm_fb_helper_setcolreg,
115 .fb_fillrect = nv04_fbcon_fillrect,
116 .fb_copyarea = nv04_fbcon_copyarea,
117 .fb_imageblit = nv04_fbcon_imageblit,
118 .fb_sync = nouveau_fbcon_sync,
119 .fb_pan_display = drm_fb_helper_pan_display,
120 .fb_blank = drm_fb_helper_blank,
121 .fb_setcmap = drm_fb_helper_setcmap,
122};
123
124static struct fb_ops nv50_fbcon_ops = {
125 .owner = THIS_MODULE,
126 .fb_check_var = drm_fb_helper_check_var,
127 .fb_set_par = drm_fb_helper_set_par,
128 .fb_setcolreg = drm_fb_helper_setcolreg,
129 .fb_fillrect = nv50_fbcon_fillrect,
130 .fb_copyarea = nv50_fbcon_copyarea,
131 .fb_imageblit = nv50_fbcon_imageblit,
132 .fb_sync = nouveau_fbcon_sync,
133 .fb_pan_display = drm_fb_helper_pan_display,
134 .fb_blank = drm_fb_helper_blank,
135 .fb_setcmap = drm_fb_helper_setcmap,
136};
137
112static void nouveau_fbcon_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 138static void nouveau_fbcon_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
113 u16 blue, int regno) 139 u16 blue, int regno)
114{ 140{
@@ -212,11 +238,11 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
212 238
213 mode_cmd.bpp = surface_bpp; 239 mode_cmd.bpp = surface_bpp;
214 mode_cmd.pitch = mode_cmd.width * (mode_cmd.bpp >> 3); 240 mode_cmd.pitch = mode_cmd.width * (mode_cmd.bpp >> 3);
215 mode_cmd.pitch = ALIGN(mode_cmd.pitch, 256); 241 mode_cmd.pitch = roundup(mode_cmd.pitch, 256);
216 mode_cmd.depth = surface_depth; 242 mode_cmd.depth = surface_depth;
217 243
218 size = mode_cmd.pitch * mode_cmd.height; 244 size = mode_cmd.pitch * mode_cmd.height;
219 size = ALIGN(size, PAGE_SIZE); 245 size = roundup(size, PAGE_SIZE);
220 246
221 ret = nouveau_gem_new(dev, dev_priv->channel, size, 0, TTM_PL_FLAG_VRAM, 247 ret = nouveau_gem_new(dev, dev_priv->channel, size, 0, TTM_PL_FLAG_VRAM,
222 0, 0x0000, false, true, &nvbo); 248 0, 0x0000, false, true, &nvbo);
@@ -269,8 +295,12 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
269 dev_priv->fbdev_info = info; 295 dev_priv->fbdev_info = info;
270 296
271 strcpy(info->fix.id, "nouveaufb"); 297 strcpy(info->fix.id, "nouveaufb");
272 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA | 298 if (nouveau_nofbaccel)
273 FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_IMAGEBLIT; 299 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_DISABLED;
300 else
301 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
302 FBINFO_HWACCEL_FILLRECT |
303 FBINFO_HWACCEL_IMAGEBLIT;
274 info->fbops = &nouveau_fbcon_ops; 304 info->fbops = &nouveau_fbcon_ops;
275 info->fix.smem_start = dev->mode_config.fb_base + nvbo->bo.offset - 305 info->fix.smem_start = dev->mode_config.fb_base + nvbo->bo.offset -
276 dev_priv->vm_vram_base; 306 dev_priv->vm_vram_base;
@@ -318,13 +348,15 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
318 par->nouveau_fb = nouveau_fb; 348 par->nouveau_fb = nouveau_fb;
319 par->dev = dev; 349 par->dev = dev;
320 350
321 if (dev_priv->channel) { 351 if (dev_priv->channel && !nouveau_nofbaccel) {
322 switch (dev_priv->card_type) { 352 switch (dev_priv->card_type) {
323 case NV_50: 353 case NV_50:
324 nv50_fbcon_accel_init(info); 354 nv50_fbcon_accel_init(info);
355 info->fbops = &nv50_fbcon_ops;
325 break; 356 break;
326 default: 357 default:
327 nv04_fbcon_accel_init(info); 358 nv04_fbcon_accel_init(info);
359 info->fbops = &nv04_fbcon_ops;
328 break; 360 break;
329 }; 361 };
330 } 362 }
@@ -380,3 +412,12 @@ nouveau_fbcon_remove(struct drm_device *dev, struct drm_framebuffer *fb)
380 412
381 return 0; 413 return 0;
382} 414}
415
416void nouveau_fbcon_gpu_lockup(struct fb_info *info)
417{
418 struct nouveau_fbcon_par *par = info->par;
419 struct drm_device *dev = par->dev;
420
421 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
422 info->flags |= FBINFO_HWACCEL_DISABLED;
423}
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
index 8531140fedbc..f9c34e1a8c11 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
@@ -40,8 +40,15 @@ int nouveau_fbcon_remove(struct drm_device *dev, struct drm_framebuffer *fb);
40void nouveau_fbcon_restore(void); 40void nouveau_fbcon_restore(void);
41void nouveau_fbcon_zfill(struct drm_device *dev); 41void nouveau_fbcon_zfill(struct drm_device *dev);
42 42
43void nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region);
44void nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
45void nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image);
43int nv04_fbcon_accel_init(struct fb_info *info); 46int nv04_fbcon_accel_init(struct fb_info *info);
47void nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
48void nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region);
49void nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image);
44int nv50_fbcon_accel_init(struct fb_info *info); 50int nv50_fbcon_accel_init(struct fb_info *info);
45 51
52void nouveau_fbcon_gpu_lockup(struct fb_info *info);
46#endif /* __NV50_FBCON_H__ */ 53#endif /* __NV50_FBCON_H__ */
47 54
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index dacac9a0842a..faddf53ff9ed 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -142,7 +142,7 @@ nouveau_fence_emit(struct nouveau_fence *fence)
142 list_add_tail(&fence->entry, &chan->fence.pending); 142 list_add_tail(&fence->entry, &chan->fence.pending);
143 spin_unlock_irqrestore(&chan->fence.lock, flags); 143 spin_unlock_irqrestore(&chan->fence.lock, flags);
144 144
145 BEGIN_RING(chan, NvSubM2MF, USE_REFCNT ? 0x0050 : 0x0150, 1); 145 BEGIN_RING(chan, NvSubSw, USE_REFCNT ? 0x0050 : 0x0150, 1);
146 OUT_RING(chan, fence->sequence); 146 OUT_RING(chan, fence->sequence);
147 FIRE_RING(chan); 147 FIRE_RING(chan);
148 148
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 18fd8ac9fca7..70cc30803e3b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -220,7 +220,6 @@ nouveau_gem_set_domain(struct drm_gem_object *gem, uint32_t read_domains,
220} 220}
221 221
222struct validate_op { 222struct validate_op {
223 struct nouveau_fence *fence;
224 struct list_head vram_list; 223 struct list_head vram_list;
225 struct list_head gart_list; 224 struct list_head gart_list;
226 struct list_head both_list; 225 struct list_head both_list;
@@ -252,17 +251,11 @@ validate_fini_list(struct list_head *list, struct nouveau_fence *fence)
252} 251}
253 252
254static void 253static void
255validate_fini(struct validate_op *op, bool success) 254validate_fini(struct validate_op *op, struct nouveau_fence* fence)
256{ 255{
257 struct nouveau_fence *fence = op->fence; 256 validate_fini_list(&op->vram_list, fence);
258 257 validate_fini_list(&op->gart_list, fence);
259 if (unlikely(!success)) 258 validate_fini_list(&op->both_list, fence);
260 op->fence = NULL;
261
262 validate_fini_list(&op->vram_list, op->fence);
263 validate_fini_list(&op->gart_list, op->fence);
264 validate_fini_list(&op->both_list, op->fence);
265 nouveau_fence_unref((void *)&fence);
266} 259}
267 260
268static int 261static int
@@ -328,6 +321,7 @@ retry:
328 else { 321 else {
329 NV_ERROR(dev, "invalid valid domains: 0x%08x\n", 322 NV_ERROR(dev, "invalid valid domains: 0x%08x\n",
330 b->valid_domains); 323 b->valid_domains);
324 list_add_tail(&nvbo->entry, &op->both_list);
331 validate_fini(op, NULL); 325 validate_fini(op, NULL);
332 return -EINVAL; 326 return -EINVAL;
333 } 327 }
@@ -420,10 +414,6 @@ nouveau_gem_pushbuf_validate(struct nouveau_channel *chan,
420 INIT_LIST_HEAD(&op->gart_list); 414 INIT_LIST_HEAD(&op->gart_list);
421 INIT_LIST_HEAD(&op->both_list); 415 INIT_LIST_HEAD(&op->both_list);
422 416
423 ret = nouveau_fence_new(chan, &op->fence, false);
424 if (ret)
425 return ret;
426
427 if (nr_buffers == 0) 417 if (nr_buffers == 0)
428 return 0; 418 return 0;
429 419
@@ -477,13 +467,14 @@ u_memcpya(uint64_t user, unsigned nmemb, unsigned size)
477static int 467static int
478nouveau_gem_pushbuf_reloc_apply(struct nouveau_channel *chan, int nr_bo, 468nouveau_gem_pushbuf_reloc_apply(struct nouveau_channel *chan, int nr_bo,
479 struct drm_nouveau_gem_pushbuf_bo *bo, 469 struct drm_nouveau_gem_pushbuf_bo *bo,
480 int nr_relocs, uint64_t ptr_relocs, 470 unsigned nr_relocs, uint64_t ptr_relocs,
481 int nr_dwords, int first_dword, 471 unsigned nr_dwords, unsigned first_dword,
482 uint32_t *pushbuf, bool is_iomem) 472 uint32_t *pushbuf, bool is_iomem)
483{ 473{
484 struct drm_nouveau_gem_pushbuf_reloc *reloc = NULL; 474 struct drm_nouveau_gem_pushbuf_reloc *reloc = NULL;
485 struct drm_device *dev = chan->dev; 475 struct drm_device *dev = chan->dev;
486 int ret = 0, i; 476 int ret = 0;
477 unsigned i;
487 478
488 reloc = u_memcpya(ptr_relocs, nr_relocs, sizeof(*reloc)); 479 reloc = u_memcpya(ptr_relocs, nr_relocs, sizeof(*reloc));
489 if (IS_ERR(reloc)) 480 if (IS_ERR(reloc))
@@ -541,6 +532,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
541 struct drm_nouveau_gem_pushbuf_bo *bo = NULL; 532 struct drm_nouveau_gem_pushbuf_bo *bo = NULL;
542 struct nouveau_channel *chan; 533 struct nouveau_channel *chan;
543 struct validate_op op; 534 struct validate_op op;
535 struct nouveau_fence* fence = 0;
544 uint32_t *pushbuf = NULL; 536 uint32_t *pushbuf = NULL;
545 int ret = 0, do_reloc = 0, i; 537 int ret = 0, do_reloc = 0, i;
546 538
@@ -597,7 +589,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
597 589
598 OUT_RINGp(chan, pushbuf, req->nr_dwords); 590 OUT_RINGp(chan, pushbuf, req->nr_dwords);
599 591
600 ret = nouveau_fence_emit(op.fence); 592 ret = nouveau_fence_new(chan, &fence, true);
601 if (ret) { 593 if (ret) {
602 NV_ERROR(dev, "error fencing pushbuf: %d\n", ret); 594 NV_ERROR(dev, "error fencing pushbuf: %d\n", ret);
603 WIND_RING(chan); 595 WIND_RING(chan);
@@ -605,7 +597,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
605 } 597 }
606 598
607 if (nouveau_gem_pushbuf_sync(chan)) { 599 if (nouveau_gem_pushbuf_sync(chan)) {
608 ret = nouveau_fence_wait(op.fence, NULL, false, false); 600 ret = nouveau_fence_wait(fence, NULL, false, false);
609 if (ret) { 601 if (ret) {
610 for (i = 0; i < req->nr_dwords; i++) 602 for (i = 0; i < req->nr_dwords; i++)
611 NV_ERROR(dev, "0x%08x\n", pushbuf[i]); 603 NV_ERROR(dev, "0x%08x\n", pushbuf[i]);
@@ -614,7 +606,8 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
614 } 606 }
615 607
616out: 608out:
617 validate_fini(&op, ret == 0); 609 validate_fini(&op, fence);
610 nouveau_fence_unref((void**)&fence);
618 mutex_unlock(&dev->struct_mutex); 611 mutex_unlock(&dev->struct_mutex);
619 kfree(pushbuf); 612 kfree(pushbuf);
620 kfree(bo); 613 kfree(bo);
@@ -634,6 +627,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
634 struct drm_gem_object *gem; 627 struct drm_gem_object *gem;
635 struct nouveau_bo *pbbo; 628 struct nouveau_bo *pbbo;
636 struct validate_op op; 629 struct validate_op op;
630 struct nouveau_fence* fence = 0;
637 int i, ret = 0, do_reloc = 0; 631 int i, ret = 0, do_reloc = 0;
638 632
639 NOUVEAU_CHECK_INITIALISED_WITH_RETURN; 633 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
@@ -675,6 +669,18 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
675 } 669 }
676 pbbo = nouveau_gem_object(gem); 670 pbbo = nouveau_gem_object(gem);
677 671
672 if ((req->offset & 3) || req->nr_dwords < 2 ||
673 (unsigned long)req->offset > (unsigned long)pbbo->bo.mem.size ||
674 (unsigned long)req->nr_dwords >
675 ((unsigned long)(pbbo->bo.mem.size - req->offset ) >> 2)) {
676 NV_ERROR(dev, "pb call misaligned or out of bounds: "
677 "%d + %d * 4 > %ld\n",
678 req->offset, req->nr_dwords, pbbo->bo.mem.size);
679 ret = -EINVAL;
680 drm_gem_object_unreference(gem);
681 goto out;
682 }
683
678 ret = ttm_bo_reserve(&pbbo->bo, false, false, true, 684 ret = ttm_bo_reserve(&pbbo->bo, false, false, true,
679 chan->fence.sequence); 685 chan->fence.sequence);
680 if (ret) { 686 if (ret) {
@@ -772,7 +778,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
772 OUT_RING(chan, 0); 778 OUT_RING(chan, 0);
773 } 779 }
774 780
775 ret = nouveau_fence_emit(op.fence); 781 ret = nouveau_fence_new(chan, &fence, true);
776 if (ret) { 782 if (ret) {
777 NV_ERROR(dev, "error fencing pushbuf: %d\n", ret); 783 NV_ERROR(dev, "error fencing pushbuf: %d\n", ret);
778 WIND_RING(chan); 784 WIND_RING(chan);
@@ -780,7 +786,8 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
780 } 786 }
781 787
782out: 788out:
783 validate_fini(&op, ret == 0); 789 validate_fini(&op, fence);
790 nouveau_fence_unref((void**)&fence);
784 mutex_unlock(&dev->struct_mutex); 791 mutex_unlock(&dev->struct_mutex);
785 kfree(bo); 792 kfree(bo);
786 793
@@ -918,7 +925,9 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
918 } 925 }
919 926
920 if (req->flags & NOUVEAU_GEM_CPU_PREP_NOBLOCK) { 927 if (req->flags & NOUVEAU_GEM_CPU_PREP_NOBLOCK) {
928 spin_lock(&nvbo->bo.lock);
921 ret = ttm_bo_wait(&nvbo->bo, false, false, no_wait); 929 ret = ttm_bo_wait(&nvbo->bo, false, false, no_wait);
930 spin_unlock(&nvbo->bo.lock);
922 } else { 931 } else {
923 ret = ttm_bo_synccpu_write_grab(&nvbo->bo, no_wait); 932 ret = ttm_bo_synccpu_write_grab(&nvbo->bo, no_wait);
924 if (ret == 0) 933 if (ret == 0)
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.c b/drivers/gpu/drm/nouveau/nouveau_grctx.c
index 419f4c2b3b89..c7ebec696747 100644
--- a/drivers/gpu/drm/nouveau/nouveau_grctx.c
+++ b/drivers/gpu/drm/nouveau/nouveau_grctx.c
@@ -97,8 +97,8 @@ nouveau_grctx_prog_load(struct drm_device *dev)
97 } 97 }
98 98
99 pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL); 99 pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL);
100 if (!pgraph->ctxprog) { 100 if (!pgraph->ctxvals) {
101 NV_ERROR(dev, "OOM copying ctxprog\n"); 101 NV_ERROR(dev, "OOM copying ctxvals\n");
102 release_firmware(fw); 102 release_firmware(fw);
103 nouveau_grctx_fini(dev); 103 nouveau_grctx_fini(dev);
104 return -ENOMEM; 104 return -ENOMEM;
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 370c72c968d1..447f9f69d6b1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -211,6 +211,20 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
211 get + 4); 211 get + 4);
212 } 212 }
213 213
214 if (status & NV_PFIFO_INTR_SEMAPHORE) {
215 uint32_t sem;
216
217 status &= ~NV_PFIFO_INTR_SEMAPHORE;
218 nv_wr32(dev, NV03_PFIFO_INTR_0,
219 NV_PFIFO_INTR_SEMAPHORE);
220
221 sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
222 nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
223
224 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
225 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
226 }
227
214 if (status) { 228 if (status) {
215 NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n", 229 NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
216 status, chid); 230 status, chid);
@@ -483,6 +497,13 @@ nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
483 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { 497 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
484 if (nouveau_pgraph_intr_swmthd(dev, &trap)) 498 if (nouveau_pgraph_intr_swmthd(dev, &trap))
485 unhandled = 1; 499 unhandled = 1;
500 } else if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
501 uint32_t v = nv_rd32(dev, 0x402000);
502 nv_wr32(dev, 0x402000, v);
503
504 /* dump the error anyway for now: it's useful for
505 Gallium development */
506 unhandled = 1;
486 } else { 507 } else {
487 unhandled = 1; 508 unhandled = 1;
488 } 509 }
@@ -559,85 +580,99 @@ nouveau_pgraph_irq_handler(struct drm_device *dev)
559static void 580static void
560nv50_pgraph_irq_handler(struct drm_device *dev) 581nv50_pgraph_irq_handler(struct drm_device *dev)
561{ 582{
562 uint32_t status, nsource; 583 uint32_t status;
563 584
564 status = nv_rd32(dev, NV03_PGRAPH_INTR); 585 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
565 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE); 586 uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
566 587
567 if (status & 0x00000001) { 588 if (status & 0x00000001) {
568 nouveau_pgraph_intr_notify(dev, nsource); 589 nouveau_pgraph_intr_notify(dev, nsource);
569 status &= ~0x00000001; 590 status &= ~0x00000001;
570 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001); 591 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
571 } 592 }
572 593
573 if (status & 0x00000010) { 594 if (status & 0x00000010) {
574 nouveau_pgraph_intr_error(dev, nsource | 595 nouveau_pgraph_intr_error(dev, nsource |
575 NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD); 596 NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD);
576 597
577 status &= ~0x00000010; 598 status &= ~0x00000010;
578 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010); 599 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
579 } 600 }
580 601
581 if (status & 0x00001000) { 602 if (status & 0x00001000) {
582 nv_wr32(dev, 0x400500, 0x00000000); 603 nv_wr32(dev, 0x400500, 0x00000000);
583 nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); 604 nv_wr32(dev, NV03_PGRAPH_INTR,
584 nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev, 605 NV_PGRAPH_INTR_CONTEXT_SWITCH);
585 NV40_PGRAPH_INTR_EN) & ~NV_PGRAPH_INTR_CONTEXT_SWITCH); 606 nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
586 nv_wr32(dev, 0x400500, 0x00010001); 607 NV40_PGRAPH_INTR_EN) &
608 ~NV_PGRAPH_INTR_CONTEXT_SWITCH);
609 nv_wr32(dev, 0x400500, 0x00010001);
587 610
588 nv50_graph_context_switch(dev); 611 nv50_graph_context_switch(dev);
589 612
590 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; 613 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
591 } 614 }
592 615
593 if (status & 0x00100000) { 616 if (status & 0x00100000) {
594 nouveau_pgraph_intr_error(dev, nsource | 617 nouveau_pgraph_intr_error(dev, nsource |
595 NV03_PGRAPH_NSOURCE_DATA_ERROR); 618 NV03_PGRAPH_NSOURCE_DATA_ERROR);
596 619
597 status &= ~0x00100000; 620 status &= ~0x00100000;
598 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000); 621 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
599 } 622 }
600 623
601 if (status & 0x00200000) { 624 if (status & 0x00200000) {
602 int r; 625 int r;
603 626
604 nouveau_pgraph_intr_error(dev, nsource | 627 nouveau_pgraph_intr_error(dev, nsource |
605 NV03_PGRAPH_NSOURCE_PROTECTION_ERROR); 628 NV03_PGRAPH_NSOURCE_PROTECTION_ERROR);
606 629
607 NV_ERROR(dev, "magic set 1:\n"); 630 NV_ERROR(dev, "magic set 1:\n");
608 for (r = 0x408900; r <= 0x408910; r += 4) 631 for (r = 0x408900; r <= 0x408910; r += 4)
609 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); 632 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
610 nv_wr32(dev, 0x408900, nv_rd32(dev, 0x408904) | 0xc0000000); 633 nv_rd32(dev, r));
611 for (r = 0x408e08; r <= 0x408e24; r += 4) 634 nv_wr32(dev, 0x408900,
612 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); 635 nv_rd32(dev, 0x408904) | 0xc0000000);
613 nv_wr32(dev, 0x408e08, nv_rd32(dev, 0x408e08) | 0xc0000000); 636 for (r = 0x408e08; r <= 0x408e24; r += 4)
614 637 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
615 NV_ERROR(dev, "magic set 2:\n"); 638 nv_rd32(dev, r));
616 for (r = 0x409900; r <= 0x409910; r += 4) 639 nv_wr32(dev, 0x408e08,
617 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); 640 nv_rd32(dev, 0x408e08) | 0xc0000000);
618 nv_wr32(dev, 0x409900, nv_rd32(dev, 0x409904) | 0xc0000000); 641
619 for (r = 0x409e08; r <= 0x409e24; r += 4) 642 NV_ERROR(dev, "magic set 2:\n");
620 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); 643 for (r = 0x409900; r <= 0x409910; r += 4)
621 nv_wr32(dev, 0x409e08, nv_rd32(dev, 0x409e08) | 0xc0000000); 644 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
622 645 nv_rd32(dev, r));
623 status &= ~0x00200000; 646 nv_wr32(dev, 0x409900,
624 nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource); 647 nv_rd32(dev, 0x409904) | 0xc0000000);
625 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000); 648 for (r = 0x409e08; r <= 0x409e24; r += 4)
626 } 649 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
650 nv_rd32(dev, r));
651 nv_wr32(dev, 0x409e08,
652 nv_rd32(dev, 0x409e08) | 0xc0000000);
653
654 status &= ~0x00200000;
655 nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource);
656 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
657 }
627 658
628 if (status) { 659 if (status) {
629 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status); 660 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
630 nv_wr32(dev, NV03_PGRAPH_INTR, status); 661 status);
631 } 662 nv_wr32(dev, NV03_PGRAPH_INTR, status);
663 }
632 664
633 { 665 {
634 const int isb = (1 << 16) | (1 << 0); 666 const int isb = (1 << 16) | (1 << 0);
635 667
636 if ((nv_rd32(dev, 0x400500) & isb) != isb) 668 if ((nv_rd32(dev, 0x400500) & isb) != isb)
637 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | isb); 669 nv_wr32(dev, 0x400500,
670 nv_rd32(dev, 0x400500) | isb);
671 }
638 } 672 }
639 673
640 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); 674 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
675 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
641} 676}
642 677
643static void 678static void
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 5158a12f7844..2dc09dbd817d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -192,6 +192,92 @@ void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
192} 192}
193 193
194/* 194/*
195 * NV10-NV40 tiling helpers
196 */
197
198static void
199nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
200 uint32_t size, uint32_t pitch)
201{
202 struct drm_nouveau_private *dev_priv = dev->dev_private;
203 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
204 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
205 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
206 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
207
208 tile->addr = addr;
209 tile->size = size;
210 tile->used = !!pitch;
211 nouveau_fence_unref((void **)&tile->fence);
212
213 if (!pfifo->cache_flush(dev))
214 return;
215
216 pfifo->reassign(dev, false);
217 pfifo->cache_flush(dev);
218 pfifo->cache_pull(dev, false);
219
220 nouveau_wait_for_idle(dev);
221
222 pgraph->set_region_tiling(dev, i, addr, size, pitch);
223 pfb->set_region_tiling(dev, i, addr, size, pitch);
224
225 pfifo->cache_pull(dev, true);
226 pfifo->reassign(dev, true);
227}
228
229struct nouveau_tile_reg *
230nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
231 uint32_t pitch)
232{
233 struct drm_nouveau_private *dev_priv = dev->dev_private;
234 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
235 struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
236 int i;
237
238 spin_lock(&dev_priv->tile.lock);
239
240 for (i = 0; i < pfb->num_tiles; i++) {
241 if (tile[i].used)
242 /* Tile region in use. */
243 continue;
244
245 if (tile[i].fence &&
246 !nouveau_fence_signalled(tile[i].fence, NULL))
247 /* Pending tile region. */
248 continue;
249
250 if (max(tile[i].addr, addr) <
251 min(tile[i].addr + tile[i].size, addr + size))
252 /* Kill an intersecting tile region. */
253 nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
254
255 if (pitch && !found) {
256 /* Free tile region. */
257 nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
258 found = &tile[i];
259 }
260 }
261
262 spin_unlock(&dev_priv->tile.lock);
263
264 return found;
265}
266
267void
268nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
269 struct nouveau_fence *fence)
270{
271 if (fence) {
272 /* Mark it as pending. */
273 tile->fence = fence;
274 nouveau_fence_ref(fence);
275 }
276
277 tile->used = false;
278}
279
280/*
195 * NV50 VM helpers 281 * NV50 VM helpers
196 */ 282 */
197int 283int
@@ -199,53 +285,50 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
199 uint32_t flags, uint64_t phys) 285 uint32_t flags, uint64_t phys)
200{ 286{
201 struct drm_nouveau_private *dev_priv = dev->dev_private; 287 struct drm_nouveau_private *dev_priv = dev->dev_private;
202 struct nouveau_gpuobj **pgt; 288 struct nouveau_gpuobj *pgt;
203 unsigned psz, pfl, pages; 289 unsigned block;
204 290 int i;
205 if (virt >= dev_priv->vm_gart_base && 291
206 (virt + size) < (dev_priv->vm_gart_base + dev_priv->vm_gart_size)) { 292 virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
207 psz = 12; 293 size = (size >> 16) << 1;
208 pgt = &dev_priv->gart_info.sg_ctxdma; 294
209 pfl = 0x21; 295 phys |= ((uint64_t)flags << 32);
210 virt -= dev_priv->vm_gart_base; 296 phys |= 1;
211 } else 297 if (dev_priv->vram_sys_base) {
212 if (virt >= dev_priv->vm_vram_base && 298 phys += dev_priv->vram_sys_base;
213 (virt + size) < (dev_priv->vm_vram_base + dev_priv->vm_vram_size)) { 299 phys |= 0x30;
214 psz = 16;
215 pgt = dev_priv->vm_vram_pt;
216 pfl = 0x01;
217 virt -= dev_priv->vm_vram_base;
218 } else {
219 NV_ERROR(dev, "Invalid address: 0x%16llx-0x%16llx\n",
220 virt, virt + size - 1);
221 return -EINVAL;
222 } 300 }
223 301
224 pages = size >> psz;
225
226 dev_priv->engine.instmem.prepare_access(dev, true); 302 dev_priv->engine.instmem.prepare_access(dev, true);
227 if (flags & 0x80000000) { 303 while (size) {
228 while (pages--) { 304 unsigned offset_h = upper_32_bits(phys);
229 struct nouveau_gpuobj *pt = pgt[virt >> 29]; 305 unsigned offset_l = lower_32_bits(phys);
230 unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1; 306 unsigned pte, end;
307
308 for (i = 7; i >= 0; i--) {
309 block = 1 << (i + 1);
310 if (size >= block && !(virt & (block - 1)))
311 break;
312 }
313 offset_l |= (i << 7);
231 314
232 nv_wo32(dev, pt, pte++, 0x00000000); 315 phys += block << 15;
233 nv_wo32(dev, pt, pte++, 0x00000000); 316 size -= block;
234 317
235 virt += (1 << psz); 318 while (block) {
236 } 319 pgt = dev_priv->vm_vram_pt[virt >> 14];
237 } else { 320 pte = virt & 0x3ffe;
238 while (pages--) {
239 struct nouveau_gpuobj *pt = pgt[virt >> 29];
240 unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
241 unsigned offset_h = upper_32_bits(phys) & 0xff;
242 unsigned offset_l = lower_32_bits(phys);
243 321
244 nv_wo32(dev, pt, pte++, offset_l | pfl); 322 end = pte + block;
245 nv_wo32(dev, pt, pte++, offset_h | flags); 323 if (end > 16384)
324 end = 16384;
325 block -= (end - pte);
326 virt += (end - pte);
246 327
247 phys += (1 << psz); 328 while (pte < end) {
248 virt += (1 << psz); 329 nv_wo32(dev, pgt, pte++, offset_l);
330 nv_wo32(dev, pgt, pte++, offset_h);
331 }
249 } 332 }
250 } 333 }
251 dev_priv->engine.instmem.finish_access(dev); 334 dev_priv->engine.instmem.finish_access(dev);
@@ -270,7 +353,41 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
270void 353void
271nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) 354nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
272{ 355{
273 nv50_mem_vm_bind_linear(dev, virt, size, 0x80000000, 0); 356 struct drm_nouveau_private *dev_priv = dev->dev_private;
357 struct nouveau_gpuobj *pgt;
358 unsigned pages, pte, end;
359
360 virt -= dev_priv->vm_vram_base;
361 pages = (size >> 16) << 1;
362
363 dev_priv->engine.instmem.prepare_access(dev, true);
364 while (pages) {
365 pgt = dev_priv->vm_vram_pt[virt >> 29];
366 pte = (virt & 0x1ffe0000ULL) >> 15;
367
368 end = pte + pages;
369 if (end > 16384)
370 end = 16384;
371 pages -= (end - pte);
372 virt += (end - pte) << 15;
373
374 while (pte < end)
375 nv_wo32(dev, pgt, pte++, 0);
376 }
377 dev_priv->engine.instmem.finish_access(dev);
378
379 nv_wr32(dev, 0x100c80, 0x00050001);
380 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
381 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
382 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
383 return;
384 }
385
386 nv_wr32(dev, 0x100c80, 0x00000001);
387 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
388 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
389 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
390 }
274} 391}
275 392
276/* 393/*
@@ -297,9 +414,8 @@ void nouveau_mem_close(struct drm_device *dev)
297{ 414{
298 struct drm_nouveau_private *dev_priv = dev->dev_private; 415 struct drm_nouveau_private *dev_priv = dev->dev_private;
299 416
300 if (dev_priv->ttm.bdev.man[TTM_PL_PRIV0].has_type) 417 nouveau_bo_unpin(dev_priv->vga_ram);
301 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_PRIV0); 418 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
302 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
303 419
304 ttm_bo_device_release(&dev_priv->ttm.bdev); 420 ttm_bo_device_release(&dev_priv->ttm.bdev);
305 421
@@ -513,6 +629,7 @@ nouveau_mem_init(struct drm_device *dev)
513 629
514 INIT_LIST_HEAD(&dev_priv->ttm.bo_list); 630 INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
515 spin_lock_init(&dev_priv->ttm.bo_list_lock); 631 spin_lock_init(&dev_priv->ttm.bo_list_lock);
632 spin_lock_init(&dev_priv->tile.lock);
516 633
517 dev_priv->fb_available_size = nouveau_mem_fb_amount(dev); 634 dev_priv->fb_available_size = nouveau_mem_fb_amount(dev);
518 635
@@ -535,6 +652,15 @@ nouveau_mem_init(struct drm_device *dev)
535 return ret; 652 return ret;
536 } 653 }
537 654
655 ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
656 0, 0, true, true, &dev_priv->vga_ram);
657 if (ret == 0)
658 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
659 if (ret) {
660 NV_WARN(dev, "failed to reserve VGA memory\n");
661 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
662 }
663
538 /* GART */ 664 /* GART */
539#if !defined(__powerpc__) && !defined(__ia64__) 665#if !defined(__powerpc__) && !defined(__ia64__)
540 if (drm_device_is_agp(dev) && dev->agp) { 666 if (drm_device_is_agp(dev) && dev->agp) {
@@ -566,6 +692,7 @@ nouveau_mem_init(struct drm_device *dev)
566 dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1), 692 dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1),
567 drm_get_resource_len(dev, 1), 693 drm_get_resource_len(dev, 1),
568 DRM_MTRR_WC); 694 DRM_MTRR_WC);
695
569 return 0; 696 return 0;
570} 697}
571 698
diff --git a/drivers/gpu/drm/nouveau/nouveau_notifier.c b/drivers/gpu/drm/nouveau/nouveau_notifier.c
index 6c66a34b6345..d99dc087f9b1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_notifier.c
+++ b/drivers/gpu/drm/nouveau/nouveau_notifier.c
@@ -34,15 +34,20 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan)
34{ 34{
35 struct drm_device *dev = chan->dev; 35 struct drm_device *dev = chan->dev;
36 struct nouveau_bo *ntfy = NULL; 36 struct nouveau_bo *ntfy = NULL;
37 uint32_t flags;
37 int ret; 38 int ret;
38 39
39 ret = nouveau_gem_new(dev, NULL, PAGE_SIZE, 0, nouveau_vram_notify ? 40 if (nouveau_vram_notify)
40 TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT, 41 flags = TTM_PL_FLAG_VRAM;
42 else
43 flags = TTM_PL_FLAG_TT;
44
45 ret = nouveau_gem_new(dev, NULL, PAGE_SIZE, 0, flags,
41 0, 0x0000, false, true, &ntfy); 46 0, 0x0000, false, true, &ntfy);
42 if (ret) 47 if (ret)
43 return ret; 48 return ret;
44 49
45 ret = nouveau_bo_pin(ntfy, TTM_PL_FLAG_VRAM); 50 ret = nouveau_bo_pin(ntfy, flags);
46 if (ret) 51 if (ret)
47 goto out_err; 52 goto out_err;
48 53
@@ -128,6 +133,8 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
128 target = NV_DMA_TARGET_PCI; 133 target = NV_DMA_TARGET_PCI;
129 } else { 134 } else {
130 target = NV_DMA_TARGET_AGP; 135 target = NV_DMA_TARGET_AGP;
136 if (dev_priv->card_type >= NV_50)
137 offset += dev_priv->vm_gart_base;
131 } 138 }
132 } else { 139 } else {
133 NV_ERROR(dev, "Bad DMA target, mem_type %d!\n", 140 NV_ERROR(dev, "Bad DMA target, mem_type %d!\n",
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index 93379bb81bea..e7c100ba63a1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -881,15 +881,16 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class,
881 return 0; 881 return 0;
882} 882}
883 883
884static int 884int
885nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class, 885nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
886 struct nouveau_gpuobj **gpuobj_ret) 886 struct nouveau_gpuobj **gpuobj_ret)
887{ 887{
888 struct drm_nouveau_private *dev_priv = chan->dev->dev_private; 888 struct drm_nouveau_private *dev_priv;
889 struct nouveau_gpuobj *gpuobj; 889 struct nouveau_gpuobj *gpuobj;
890 890
891 if (!chan || !gpuobj_ret || *gpuobj_ret != NULL) 891 if (!chan || !gpuobj_ret || *gpuobj_ret != NULL)
892 return -EINVAL; 892 return -EINVAL;
893 dev_priv = chan->dev->dev_private;
893 894
894 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); 895 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
895 if (!gpuobj) 896 if (!gpuobj)
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index fa1b0e7165b9..aa9b310e41be 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -99,6 +99,7 @@
99 * the card will hang early on in the X init process. 99 * the card will hang early on in the X init process.
100 */ 100 */
101# define NV_PMC_ENABLE_UNK13 (1<<13) 101# define NV_PMC_ENABLE_UNK13 (1<<13)
102#define NV40_PMC_GRAPH_UNITS 0x00001540
102#define NV40_PMC_BACKLIGHT 0x000015f0 103#define NV40_PMC_BACKLIGHT 0x000015f0
103# define NV40_PMC_BACKLIGHT_MASK 0x001f0000 104# define NV40_PMC_BACKLIGHT_MASK 0x001f0000
104#define NV40_PMC_1700 0x00001700 105#define NV40_PMC_1700 0x00001700
@@ -349,19 +350,19 @@
349#define NV04_PGRAPH_BLEND 0x00400824 350#define NV04_PGRAPH_BLEND 0x00400824
350#define NV04_PGRAPH_STORED_FMT 0x00400830 351#define NV04_PGRAPH_STORED_FMT 0x00400830
351#define NV04_PGRAPH_PATT_COLORRAM 0x00400900 352#define NV04_PGRAPH_PATT_COLORRAM 0x00400900
352#define NV40_PGRAPH_TILE0(i) (0x00400900 + (i*16)) 353#define NV20_PGRAPH_TILE(i) (0x00400900 + (i*16))
353#define NV40_PGRAPH_TLIMIT0(i) (0x00400904 + (i*16)) 354#define NV20_PGRAPH_TLIMIT(i) (0x00400904 + (i*16))
354#define NV40_PGRAPH_TSIZE0(i) (0x00400908 + (i*16)) 355#define NV20_PGRAPH_TSIZE(i) (0x00400908 + (i*16))
355#define NV40_PGRAPH_TSTATUS0(i) (0x0040090C + (i*16)) 356#define NV20_PGRAPH_TSTATUS(i) (0x0040090C + (i*16))
356#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) 357#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16))
357#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) 358#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16))
358#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) 359#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16))
359#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) 360#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16))
360#define NV04_PGRAPH_U_RAM 0x00400D00 361#define NV04_PGRAPH_U_RAM 0x00400D00
361#define NV47_PGRAPH_TILE0(i) (0x00400D00 + (i*16)) 362#define NV47_PGRAPH_TILE(i) (0x00400D00 + (i*16))
362#define NV47_PGRAPH_TLIMIT0(i) (0x00400D04 + (i*16)) 363#define NV47_PGRAPH_TLIMIT(i) (0x00400D04 + (i*16))
363#define NV47_PGRAPH_TSIZE0(i) (0x00400D08 + (i*16)) 364#define NV47_PGRAPH_TSIZE(i) (0x00400D08 + (i*16))
364#define NV47_PGRAPH_TSTATUS0(i) (0x00400D0C + (i*16)) 365#define NV47_PGRAPH_TSTATUS(i) (0x00400D0C + (i*16))
365#define NV04_PGRAPH_V_RAM 0x00400D40 366#define NV04_PGRAPH_V_RAM 0x00400D40
366#define NV04_PGRAPH_W_RAM 0x00400D80 367#define NV04_PGRAPH_W_RAM 0x00400D80
367#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 368#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index 4c7f1e403e80..ed1590577b6c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -54,11 +54,12 @@ static void
54nouveau_sgdma_clear(struct ttm_backend *be) 54nouveau_sgdma_clear(struct ttm_backend *be)
55{ 55{
56 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be; 56 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
57 struct drm_device *dev = nvbe->dev; 57 struct drm_device *dev;
58
59 NV_DEBUG(nvbe->dev, "\n");
60 58
61 if (nvbe && nvbe->pages) { 59 if (nvbe && nvbe->pages) {
60 dev = nvbe->dev;
61 NV_DEBUG(dev, "\n");
62
62 if (nvbe->bound) 63 if (nvbe->bound)
63 be->func->unbind(be); 64 be->func->unbind(be);
64 65
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index e76ec2d207a9..a4851af5b05e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -76,6 +76,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
76 engine->fifo.disable = nv04_fifo_disable; 76 engine->fifo.disable = nv04_fifo_disable;
77 engine->fifo.enable = nv04_fifo_enable; 77 engine->fifo.enable = nv04_fifo_enable;
78 engine->fifo.reassign = nv04_fifo_reassign; 78 engine->fifo.reassign = nv04_fifo_reassign;
79 engine->fifo.cache_flush = nv04_fifo_cache_flush;
80 engine->fifo.cache_pull = nv04_fifo_cache_pull;
79 engine->fifo.channel_id = nv04_fifo_channel_id; 81 engine->fifo.channel_id = nv04_fifo_channel_id;
80 engine->fifo.create_context = nv04_fifo_create_context; 82 engine->fifo.create_context = nv04_fifo_create_context;
81 engine->fifo.destroy_context = nv04_fifo_destroy_context; 83 engine->fifo.destroy_context = nv04_fifo_destroy_context;
@@ -100,6 +102,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
100 engine->timer.takedown = nv04_timer_takedown; 102 engine->timer.takedown = nv04_timer_takedown;
101 engine->fb.init = nv10_fb_init; 103 engine->fb.init = nv10_fb_init;
102 engine->fb.takedown = nv10_fb_takedown; 104 engine->fb.takedown = nv10_fb_takedown;
105 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
103 engine->graph.grclass = nv10_graph_grclass; 106 engine->graph.grclass = nv10_graph_grclass;
104 engine->graph.init = nv10_graph_init; 107 engine->graph.init = nv10_graph_init;
105 engine->graph.takedown = nv10_graph_takedown; 108 engine->graph.takedown = nv10_graph_takedown;
@@ -109,12 +112,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
109 engine->graph.fifo_access = nv04_graph_fifo_access; 112 engine->graph.fifo_access = nv04_graph_fifo_access;
110 engine->graph.load_context = nv10_graph_load_context; 113 engine->graph.load_context = nv10_graph_load_context;
111 engine->graph.unload_context = nv10_graph_unload_context; 114 engine->graph.unload_context = nv10_graph_unload_context;
115 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
112 engine->fifo.channels = 32; 116 engine->fifo.channels = 32;
113 engine->fifo.init = nv10_fifo_init; 117 engine->fifo.init = nv10_fifo_init;
114 engine->fifo.takedown = nouveau_stub_takedown; 118 engine->fifo.takedown = nouveau_stub_takedown;
115 engine->fifo.disable = nv04_fifo_disable; 119 engine->fifo.disable = nv04_fifo_disable;
116 engine->fifo.enable = nv04_fifo_enable; 120 engine->fifo.enable = nv04_fifo_enable;
117 engine->fifo.reassign = nv04_fifo_reassign; 121 engine->fifo.reassign = nv04_fifo_reassign;
122 engine->fifo.cache_flush = nv04_fifo_cache_flush;
123 engine->fifo.cache_pull = nv04_fifo_cache_pull;
118 engine->fifo.channel_id = nv10_fifo_channel_id; 124 engine->fifo.channel_id = nv10_fifo_channel_id;
119 engine->fifo.create_context = nv10_fifo_create_context; 125 engine->fifo.create_context = nv10_fifo_create_context;
120 engine->fifo.destroy_context = nv10_fifo_destroy_context; 126 engine->fifo.destroy_context = nv10_fifo_destroy_context;
@@ -139,6 +145,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
139 engine->timer.takedown = nv04_timer_takedown; 145 engine->timer.takedown = nv04_timer_takedown;
140 engine->fb.init = nv10_fb_init; 146 engine->fb.init = nv10_fb_init;
141 engine->fb.takedown = nv10_fb_takedown; 147 engine->fb.takedown = nv10_fb_takedown;
148 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
142 engine->graph.grclass = nv20_graph_grclass; 149 engine->graph.grclass = nv20_graph_grclass;
143 engine->graph.init = nv20_graph_init; 150 engine->graph.init = nv20_graph_init;
144 engine->graph.takedown = nv20_graph_takedown; 151 engine->graph.takedown = nv20_graph_takedown;
@@ -148,12 +155,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
148 engine->graph.fifo_access = nv04_graph_fifo_access; 155 engine->graph.fifo_access = nv04_graph_fifo_access;
149 engine->graph.load_context = nv20_graph_load_context; 156 engine->graph.load_context = nv20_graph_load_context;
150 engine->graph.unload_context = nv20_graph_unload_context; 157 engine->graph.unload_context = nv20_graph_unload_context;
158 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
151 engine->fifo.channels = 32; 159 engine->fifo.channels = 32;
152 engine->fifo.init = nv10_fifo_init; 160 engine->fifo.init = nv10_fifo_init;
153 engine->fifo.takedown = nouveau_stub_takedown; 161 engine->fifo.takedown = nouveau_stub_takedown;
154 engine->fifo.disable = nv04_fifo_disable; 162 engine->fifo.disable = nv04_fifo_disable;
155 engine->fifo.enable = nv04_fifo_enable; 163 engine->fifo.enable = nv04_fifo_enable;
156 engine->fifo.reassign = nv04_fifo_reassign; 164 engine->fifo.reassign = nv04_fifo_reassign;
165 engine->fifo.cache_flush = nv04_fifo_cache_flush;
166 engine->fifo.cache_pull = nv04_fifo_cache_pull;
157 engine->fifo.channel_id = nv10_fifo_channel_id; 167 engine->fifo.channel_id = nv10_fifo_channel_id;
158 engine->fifo.create_context = nv10_fifo_create_context; 168 engine->fifo.create_context = nv10_fifo_create_context;
159 engine->fifo.destroy_context = nv10_fifo_destroy_context; 169 engine->fifo.destroy_context = nv10_fifo_destroy_context;
@@ -178,6 +188,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
178 engine->timer.takedown = nv04_timer_takedown; 188 engine->timer.takedown = nv04_timer_takedown;
179 engine->fb.init = nv10_fb_init; 189 engine->fb.init = nv10_fb_init;
180 engine->fb.takedown = nv10_fb_takedown; 190 engine->fb.takedown = nv10_fb_takedown;
191 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
181 engine->graph.grclass = nv30_graph_grclass; 192 engine->graph.grclass = nv30_graph_grclass;
182 engine->graph.init = nv30_graph_init; 193 engine->graph.init = nv30_graph_init;
183 engine->graph.takedown = nv20_graph_takedown; 194 engine->graph.takedown = nv20_graph_takedown;
@@ -187,12 +198,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
187 engine->graph.destroy_context = nv20_graph_destroy_context; 198 engine->graph.destroy_context = nv20_graph_destroy_context;
188 engine->graph.load_context = nv20_graph_load_context; 199 engine->graph.load_context = nv20_graph_load_context;
189 engine->graph.unload_context = nv20_graph_unload_context; 200 engine->graph.unload_context = nv20_graph_unload_context;
201 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
190 engine->fifo.channels = 32; 202 engine->fifo.channels = 32;
191 engine->fifo.init = nv10_fifo_init; 203 engine->fifo.init = nv10_fifo_init;
192 engine->fifo.takedown = nouveau_stub_takedown; 204 engine->fifo.takedown = nouveau_stub_takedown;
193 engine->fifo.disable = nv04_fifo_disable; 205 engine->fifo.disable = nv04_fifo_disable;
194 engine->fifo.enable = nv04_fifo_enable; 206 engine->fifo.enable = nv04_fifo_enable;
195 engine->fifo.reassign = nv04_fifo_reassign; 207 engine->fifo.reassign = nv04_fifo_reassign;
208 engine->fifo.cache_flush = nv04_fifo_cache_flush;
209 engine->fifo.cache_pull = nv04_fifo_cache_pull;
196 engine->fifo.channel_id = nv10_fifo_channel_id; 210 engine->fifo.channel_id = nv10_fifo_channel_id;
197 engine->fifo.create_context = nv10_fifo_create_context; 211 engine->fifo.create_context = nv10_fifo_create_context;
198 engine->fifo.destroy_context = nv10_fifo_destroy_context; 212 engine->fifo.destroy_context = nv10_fifo_destroy_context;
@@ -218,6 +232,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
218 engine->timer.takedown = nv04_timer_takedown; 232 engine->timer.takedown = nv04_timer_takedown;
219 engine->fb.init = nv40_fb_init; 233 engine->fb.init = nv40_fb_init;
220 engine->fb.takedown = nv40_fb_takedown; 234 engine->fb.takedown = nv40_fb_takedown;
235 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
221 engine->graph.grclass = nv40_graph_grclass; 236 engine->graph.grclass = nv40_graph_grclass;
222 engine->graph.init = nv40_graph_init; 237 engine->graph.init = nv40_graph_init;
223 engine->graph.takedown = nv40_graph_takedown; 238 engine->graph.takedown = nv40_graph_takedown;
@@ -227,12 +242,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
227 engine->graph.destroy_context = nv40_graph_destroy_context; 242 engine->graph.destroy_context = nv40_graph_destroy_context;
228 engine->graph.load_context = nv40_graph_load_context; 243 engine->graph.load_context = nv40_graph_load_context;
229 engine->graph.unload_context = nv40_graph_unload_context; 244 engine->graph.unload_context = nv40_graph_unload_context;
245 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
230 engine->fifo.channels = 32; 246 engine->fifo.channels = 32;
231 engine->fifo.init = nv40_fifo_init; 247 engine->fifo.init = nv40_fifo_init;
232 engine->fifo.takedown = nouveau_stub_takedown; 248 engine->fifo.takedown = nouveau_stub_takedown;
233 engine->fifo.disable = nv04_fifo_disable; 249 engine->fifo.disable = nv04_fifo_disable;
234 engine->fifo.enable = nv04_fifo_enable; 250 engine->fifo.enable = nv04_fifo_enable;
235 engine->fifo.reassign = nv04_fifo_reassign; 251 engine->fifo.reassign = nv04_fifo_reassign;
252 engine->fifo.cache_flush = nv04_fifo_cache_flush;
253 engine->fifo.cache_pull = nv04_fifo_cache_pull;
236 engine->fifo.channel_id = nv10_fifo_channel_id; 254 engine->fifo.channel_id = nv10_fifo_channel_id;
237 engine->fifo.create_context = nv40_fifo_create_context; 255 engine->fifo.create_context = nv40_fifo_create_context;
238 engine->fifo.destroy_context = nv40_fifo_destroy_context; 256 engine->fifo.destroy_context = nv40_fifo_destroy_context;
@@ -292,6 +310,14 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
292static unsigned int 310static unsigned int
293nouveau_vga_set_decode(void *priv, bool state) 311nouveau_vga_set_decode(void *priv, bool state)
294{ 312{
313 struct drm_device *dev = priv;
314 struct drm_nouveau_private *dev_priv = dev->dev_private;
315
316 if (dev_priv->chipset >= 0x40)
317 nv_wr32(dev, 0x88054, state);
318 else
319 nv_wr32(dev, 0x1854, state);
320
295 if (state) 321 if (state)
296 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 322 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
297 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 323 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
@@ -409,15 +435,19 @@ nouveau_card_init(struct drm_device *dev)
409 if (ret) 435 if (ret)
410 goto out_timer; 436 goto out_timer;
411 437
412 /* PGRAPH */ 438 if (nouveau_noaccel)
413 ret = engine->graph.init(dev); 439 engine->graph.accel_blocked = true;
414 if (ret) 440 else {
415 goto out_fb; 441 /* PGRAPH */
442 ret = engine->graph.init(dev);
443 if (ret)
444 goto out_fb;
416 445
417 /* PFIFO */ 446 /* PFIFO */
418 ret = engine->fifo.init(dev); 447 ret = engine->fifo.init(dev);
419 if (ret) 448 if (ret)
420 goto out_graph; 449 goto out_graph;
450 }
421 451
422 /* this call irq_preinstall, register irq handler and 452 /* this call irq_preinstall, register irq handler and
423 * call irq_postinstall 453 * call irq_postinstall
@@ -461,9 +491,11 @@ nouveau_card_init(struct drm_device *dev)
461out_irq: 491out_irq:
462 drm_irq_uninstall(dev); 492 drm_irq_uninstall(dev);
463out_fifo: 493out_fifo:
464 engine->fifo.takedown(dev); 494 if (!nouveau_noaccel)
495 engine->fifo.takedown(dev);
465out_graph: 496out_graph:
466 engine->graph.takedown(dev); 497 if (!nouveau_noaccel)
498 engine->graph.takedown(dev);
467out_fb: 499out_fb:
468 engine->fb.takedown(dev); 500 engine->fb.takedown(dev);
469out_timer: 501out_timer:
@@ -500,13 +532,16 @@ static void nouveau_card_takedown(struct drm_device *dev)
500 dev_priv->channel = NULL; 532 dev_priv->channel = NULL;
501 } 533 }
502 534
503 engine->fifo.takedown(dev); 535 if (!nouveau_noaccel) {
504 engine->graph.takedown(dev); 536 engine->fifo.takedown(dev);
537 engine->graph.takedown(dev);
538 }
505 engine->fb.takedown(dev); 539 engine->fb.takedown(dev);
506 engine->timer.takedown(dev); 540 engine->timer.takedown(dev);
507 engine->mc.takedown(dev); 541 engine->mc.takedown(dev);
508 542
509 mutex_lock(&dev->struct_mutex); 543 mutex_lock(&dev->struct_mutex);
544 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
510 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT); 545 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
511 mutex_unlock(&dev->struct_mutex); 546 mutex_unlock(&dev->struct_mutex);
512 nouveau_sgdma_takedown(dev); 547 nouveau_sgdma_takedown(dev);
@@ -624,7 +659,10 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
624 dev_priv->chipset = (reg0 & 0xff00000) >> 20; 659 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
625 /* NV04 or NV05 */ 660 /* NV04 or NV05 */
626 } else if ((reg0 & 0xff00fff0) == 0x20004000) { 661 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
627 dev_priv->chipset = 0x04; 662 if (reg0 & 0x00f00000)
663 dev_priv->chipset = 0x05;
664 else
665 dev_priv->chipset = 0x04;
628 } else 666 } else
629 dev_priv->chipset = 0xff; 667 dev_priv->chipset = 0xff;
630 668
@@ -704,8 +742,8 @@ static void nouveau_close(struct drm_device *dev)
704{ 742{
705 struct drm_nouveau_private *dev_priv = dev->dev_private; 743 struct drm_nouveau_private *dev_priv = dev->dev_private;
706 744
707 /* In the case of an error dev_priv may not be be allocated yet */ 745 /* In the case of an error dev_priv may not be allocated yet */
708 if (dev_priv && dev_priv->card_type) 746 if (dev_priv)
709 nouveau_card_takedown(dev); 747 nouveau_card_takedown(dev);
710} 748}
711 749
@@ -795,6 +833,15 @@ int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
795 case NOUVEAU_GETPARAM_VM_VRAM_BASE: 833 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
796 getparam->value = dev_priv->vm_vram_base; 834 getparam->value = dev_priv->vm_vram_base;
797 break; 835 break;
836 case NOUVEAU_GETPARAM_GRAPH_UNITS:
837 /* NV40 and NV50 versions are quite different, but register
838 * address is the same. User is supposed to know the card
839 * family anyway... */
840 if (dev_priv->chipset >= 0x40) {
841 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
842 break;
843 }
844 /* FALLTHRU */
798 default: 845 default:
799 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param); 846 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
800 return -EINVAL; 847 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 187eb84e4da5..c385d50f041b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -28,45 +28,17 @@
28 28
29#include "nouveau_drv.h" 29#include "nouveau_drv.h"
30 30
31static struct vm_operations_struct nouveau_ttm_vm_ops;
32static const struct vm_operations_struct *ttm_vm_ops;
33
34static int
35nouveau_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
36{
37 struct ttm_buffer_object *bo = vma->vm_private_data;
38 int ret;
39
40 if (unlikely(bo == NULL))
41 return VM_FAULT_NOPAGE;
42
43 ret = ttm_vm_ops->fault(vma, vmf);
44 return ret;
45}
46
47int 31int
48nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma) 32nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
49{ 33{
50 struct drm_file *file_priv = filp->private_data; 34 struct drm_file *file_priv = filp->private_data;
51 struct drm_nouveau_private *dev_priv = 35 struct drm_nouveau_private *dev_priv =
52 file_priv->minor->dev->dev_private; 36 file_priv->minor->dev->dev_private;
53 int ret;
54 37
55 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) 38 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
56 return drm_mmap(filp, vma); 39 return drm_mmap(filp, vma);
57 40
58 ret = ttm_bo_mmap(filp, vma, &dev_priv->ttm.bdev); 41 return ttm_bo_mmap(filp, vma, &dev_priv->ttm.bdev);
59 if (unlikely(ret != 0))
60 return ret;
61
62 if (unlikely(ttm_vm_ops == NULL)) {
63 ttm_vm_ops = vma->vm_ops;
64 nouveau_ttm_vm_ops = *ttm_vm_ops;
65 nouveau_ttm_vm_ops.fault = &nouveau_ttm_fault;
66 }
67
68 vma->vm_ops = &nouveau_ttm_vm_ops;
69 return 0;
70} 42}
71 43
72static int 44static int
diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
index d9f32879ba38..1d73b15d70da 100644
--- a/drivers/gpu/drm/nouveau/nv04_dac.c
+++ b/drivers/gpu/drm/nouveau/nv04_dac.c
@@ -119,7 +119,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
119 struct drm_connector *connector) 119 struct drm_connector *connector)
120{ 120{
121 struct drm_device *dev = encoder->dev; 121 struct drm_device *dev = encoder->dev;
122 uint8_t saved_seq1, saved_pi, saved_rpc1; 122 uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
123 uint8_t saved_palette0[3], saved_palette_mask; 123 uint8_t saved_palette0[3], saved_palette_mask;
124 uint32_t saved_rtest_ctrl, saved_rgen_ctrl; 124 uint32_t saved_rtest_ctrl, saved_rgen_ctrl;
125 int i; 125 int i;
@@ -135,6 +135,9 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
135 /* only implemented for head A for now */ 135 /* only implemented for head A for now */
136 NVSetOwner(dev, 0); 136 NVSetOwner(dev, 0);
137 137
138 saved_cr_mode = NVReadVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX);
139 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode | 0x80);
140
138 saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX); 141 saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX);
139 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20); 142 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);
140 143
@@ -203,6 +206,7 @@ out:
203 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi); 206 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
204 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1); 207 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
205 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1); 208 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
209 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode);
206 210
207 if (blue == 0x18) { 211 if (blue == 0x18) {
208 NV_INFO(dev, "Load detected on head A\n"); 212 NV_INFO(dev, "Load detected on head A\n");
@@ -212,16 +216,15 @@ out:
212 return connector_status_disconnected; 216 return connector_status_disconnected;
213} 217}
214 218
215enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder, 219uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
216 struct drm_connector *connector)
217{ 220{
218 struct drm_device *dev = encoder->dev; 221 struct drm_device *dev = encoder->dev;
219 struct drm_nouveau_private *dev_priv = dev->dev_private; 222 struct drm_nouveau_private *dev_priv = dev->dev_private;
220 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 223 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
221 uint32_t testval, regoffset = nv04_dac_output_offset(encoder); 224 uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
222 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, 225 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
223 saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput; 226 saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput;
224 int head, present = 0; 227 int head;
225 228
226#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) 229#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
227 if (dcb->type == OUTPUT_TV) { 230 if (dcb->type == OUTPUT_TV) {
@@ -287,13 +290,7 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
287 temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED); 290 temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
288 msleep(5); 291 msleep(5);
289 292
290 temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); 293 sample = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
291
292 if (dcb->type == OUTPUT_TV)
293 present = (nv17_tv_detect(encoder, connector, temp)
294 == connector_status_connected);
295 else
296 present = temp & NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI;
297 294
298 temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL); 295 temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
299 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL, 296 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL,
@@ -310,15 +307,25 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
310 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, saved_gpio1); 307 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, saved_gpio1);
311 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, saved_gpio0); 308 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, saved_gpio0);
312 309
313 if (present) { 310 return sample;
314 NV_INFO(dev, "Load detected on output %c\n", '@' + ffs(dcb->or)); 311}
312
313static enum drm_connector_status
314nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
315{
316 struct drm_device *dev = encoder->dev;
317 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
318 uint32_t sample = nv17_dac_sample_load(encoder);
319
320 if (sample & NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI) {
321 NV_INFO(dev, "Load detected on output %c\n",
322 '@' + ffs(dcb->or));
315 return connector_status_connected; 323 return connector_status_connected;
324 } else {
325 return connector_status_disconnected;
316 } 326 }
317
318 return connector_status_disconnected;
319} 327}
320 328
321
322static bool nv04_dac_mode_fixup(struct drm_encoder *encoder, 329static bool nv04_dac_mode_fixup(struct drm_encoder *encoder,
323 struct drm_display_mode *mode, 330 struct drm_display_mode *mode,
324 struct drm_display_mode *adjusted_mode) 331 struct drm_display_mode *adjusted_mode)
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c
index 09a31071ee58..fd01caabd5c3 100644
--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c
@@ -27,7 +27,7 @@
27#include "nouveau_dma.h" 27#include "nouveau_dma.h"
28#include "nouveau_fbcon.h" 28#include "nouveau_fbcon.h"
29 29
30static void 30void
31nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) 31nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
32{ 32{
33 struct nouveau_fbcon_par *par = info->par; 33 struct nouveau_fbcon_par *par = info->par;
@@ -39,8 +39,7 @@ nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
39 return; 39 return;
40 40
41 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 4)) { 41 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 4)) {
42 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 42 nouveau_fbcon_gpu_lockup(info);
43 info->flags |= FBINFO_HWACCEL_DISABLED;
44 } 43 }
45 44
46 if (info->flags & FBINFO_HWACCEL_DISABLED) { 45 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -55,21 +54,19 @@ nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
55 FIRE_RING(chan); 54 FIRE_RING(chan);
56} 55}
57 56
58static void 57void
59nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 58nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
60{ 59{
61 struct nouveau_fbcon_par *par = info->par; 60 struct nouveau_fbcon_par *par = info->par;
62 struct drm_device *dev = par->dev; 61 struct drm_device *dev = par->dev;
63 struct drm_nouveau_private *dev_priv = dev->dev_private; 62 struct drm_nouveau_private *dev_priv = dev->dev_private;
64 struct nouveau_channel *chan = dev_priv->channel; 63 struct nouveau_channel *chan = dev_priv->channel;
65 uint32_t color = ((uint32_t *) info->pseudo_palette)[rect->color];
66 64
67 if (info->state != FBINFO_STATE_RUNNING) 65 if (info->state != FBINFO_STATE_RUNNING)
68 return; 66 return;
69 67
70 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 7)) { 68 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 7)) {
71 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 69 nouveau_fbcon_gpu_lockup(info);
72 info->flags |= FBINFO_HWACCEL_DISABLED;
73 } 70 }
74 71
75 if (info->flags & FBINFO_HWACCEL_DISABLED) { 72 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -80,14 +77,18 @@ nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
80 BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1); 77 BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1);
81 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); 78 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
82 BEGIN_RING(chan, NvSubGdiRect, 0x03fc, 1); 79 BEGIN_RING(chan, NvSubGdiRect, 0x03fc, 1);
83 OUT_RING(chan, color); 80 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
81 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
82 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
83 else
84 OUT_RING(chan, rect->color);
84 BEGIN_RING(chan, NvSubGdiRect, 0x0400, 2); 85 BEGIN_RING(chan, NvSubGdiRect, 0x0400, 2);
85 OUT_RING(chan, (rect->dx << 16) | rect->dy); 86 OUT_RING(chan, (rect->dx << 16) | rect->dy);
86 OUT_RING(chan, (rect->width << 16) | rect->height); 87 OUT_RING(chan, (rect->width << 16) | rect->height);
87 FIRE_RING(chan); 88 FIRE_RING(chan);
88} 89}
89 90
90static void 91void
91nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) 92nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
92{ 93{
93 struct nouveau_fbcon_par *par = info->par; 94 struct nouveau_fbcon_par *par = info->par;
@@ -109,8 +110,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
109 } 110 }
110 111
111 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 8)) { 112 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 8)) {
112 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 113 nouveau_fbcon_gpu_lockup(info);
113 info->flags |= FBINFO_HWACCEL_DISABLED;
114 } 114 }
115 115
116 if (info->flags & FBINFO_HWACCEL_DISABLED) { 116 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -144,8 +144,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
144 int iter_len = dsize > 128 ? 128 : dsize; 144 int iter_len = dsize > 128 ? 128 : dsize;
145 145
146 if (RING_SPACE(chan, iter_len + 1)) { 146 if (RING_SPACE(chan, iter_len + 1)) {
147 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 147 nouveau_fbcon_gpu_lockup(info);
148 info->flags |= FBINFO_HWACCEL_DISABLED;
149 cfb_imageblit(info, image); 148 cfb_imageblit(info, image);
150 return; 149 return;
151 } 150 }
@@ -184,6 +183,7 @@ nv04_fbcon_accel_init(struct fb_info *info)
184 struct drm_device *dev = par->dev; 183 struct drm_device *dev = par->dev;
185 struct drm_nouveau_private *dev_priv = dev->dev_private; 184 struct drm_nouveau_private *dev_priv = dev->dev_private;
186 struct nouveau_channel *chan = dev_priv->channel; 185 struct nouveau_channel *chan = dev_priv->channel;
186 const int sub = NvSubCtxSurf2D;
187 int surface_fmt, pattern_fmt, rect_fmt; 187 int surface_fmt, pattern_fmt, rect_fmt;
188 int ret; 188 int ret;
189 189
@@ -242,30 +242,29 @@ nv04_fbcon_accel_init(struct fb_info *info)
242 return ret; 242 return ret;
243 243
244 if (RING_SPACE(chan, 49)) { 244 if (RING_SPACE(chan, 49)) {
245 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 245 nouveau_fbcon_gpu_lockup(info);
246 info->flags |= FBINFO_HWACCEL_DISABLED;
247 return 0; 246 return 0;
248 } 247 }
249 248
250 BEGIN_RING(chan, 1, 0x0000, 1); 249 BEGIN_RING(chan, sub, 0x0000, 1);
251 OUT_RING(chan, NvCtxSurf2D); 250 OUT_RING(chan, NvCtxSurf2D);
252 BEGIN_RING(chan, 1, 0x0184, 2); 251 BEGIN_RING(chan, sub, 0x0184, 2);
253 OUT_RING(chan, NvDmaFB); 252 OUT_RING(chan, NvDmaFB);
254 OUT_RING(chan, NvDmaFB); 253 OUT_RING(chan, NvDmaFB);
255 BEGIN_RING(chan, 1, 0x0300, 4); 254 BEGIN_RING(chan, sub, 0x0300, 4);
256 OUT_RING(chan, surface_fmt); 255 OUT_RING(chan, surface_fmt);
257 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); 256 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
258 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); 257 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
259 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); 258 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
260 259
261 BEGIN_RING(chan, 1, 0x0000, 1); 260 BEGIN_RING(chan, sub, 0x0000, 1);
262 OUT_RING(chan, NvRop); 261 OUT_RING(chan, NvRop);
263 BEGIN_RING(chan, 1, 0x0300, 1); 262 BEGIN_RING(chan, sub, 0x0300, 1);
264 OUT_RING(chan, 0x55); 263 OUT_RING(chan, 0x55);
265 264
266 BEGIN_RING(chan, 1, 0x0000, 1); 265 BEGIN_RING(chan, sub, 0x0000, 1);
267 OUT_RING(chan, NvImagePatt); 266 OUT_RING(chan, NvImagePatt);
268 BEGIN_RING(chan, 1, 0x0300, 8); 267 BEGIN_RING(chan, sub, 0x0300, 8);
269 OUT_RING(chan, pattern_fmt); 268 OUT_RING(chan, pattern_fmt);
270#ifdef __BIG_ENDIAN 269#ifdef __BIG_ENDIAN
271 OUT_RING(chan, 2); 270 OUT_RING(chan, 2);
@@ -279,9 +278,9 @@ nv04_fbcon_accel_init(struct fb_info *info)
279 OUT_RING(chan, ~0); 278 OUT_RING(chan, ~0);
280 OUT_RING(chan, ~0); 279 OUT_RING(chan, ~0);
281 280
282 BEGIN_RING(chan, 1, 0x0000, 1); 281 BEGIN_RING(chan, sub, 0x0000, 1);
283 OUT_RING(chan, NvClipRect); 282 OUT_RING(chan, NvClipRect);
284 BEGIN_RING(chan, 1, 0x0300, 2); 283 BEGIN_RING(chan, sub, 0x0300, 2);
285 OUT_RING(chan, 0); 284 OUT_RING(chan, 0);
286 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); 285 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);
287 286
@@ -308,9 +307,6 @@ nv04_fbcon_accel_init(struct fb_info *info)
308 307
309 FIRE_RING(chan); 308 FIRE_RING(chan);
310 309
311 info->fbops->fb_fillrect = nv04_fbcon_fillrect;
312 info->fbops->fb_copyarea = nv04_fbcon_copyarea;
313 info->fbops->fb_imageblit = nv04_fbcon_imageblit;
314 return 0; 310 return 0;
315} 311}
316 312
diff --git a/drivers/gpu/drm/nouveau/nv04_fifo.c b/drivers/gpu/drm/nouveau/nv04_fifo.c
index 0c3cd53c7313..f31347b8c9b0 100644
--- a/drivers/gpu/drm/nouveau/nv04_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv04_fifo.c
@@ -71,6 +71,40 @@ nv04_fifo_reassign(struct drm_device *dev, bool enable)
71 return (reassign == 1); 71 return (reassign == 1);
72} 72}
73 73
74bool
75nv04_fifo_cache_flush(struct drm_device *dev)
76{
77 struct drm_nouveau_private *dev_priv = dev->dev_private;
78 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
79 uint64_t start = ptimer->read(dev);
80
81 do {
82 if (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) ==
83 nv_rd32(dev, NV03_PFIFO_CACHE1_PUT))
84 return true;
85
86 } while (ptimer->read(dev) - start < 100000000);
87
88 NV_ERROR(dev, "Timeout flushing the PFIFO cache.\n");
89
90 return false;
91}
92
93bool
94nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
95{
96 uint32_t pull = nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0);
97
98 if (enable) {
99 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull | 1);
100 } else {
101 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull & ~1);
102 nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
103 }
104
105 return !!(pull & 1);
106}
107
74int 108int
75nv04_fifo_channel_id(struct drm_device *dev) 109nv04_fifo_channel_id(struct drm_device *dev)
76{ 110{
diff --git a/drivers/gpu/drm/nouveau/nv04_graph.c b/drivers/gpu/drm/nouveau/nv04_graph.c
index d561d773c0f4..e260986ea65a 100644
--- a/drivers/gpu/drm/nouveau/nv04_graph.c
+++ b/drivers/gpu/drm/nouveau/nv04_graph.c
@@ -28,6 +28,10 @@
28#include "nouveau_drv.h" 28#include "nouveau_drv.h"
29 29
30static uint32_t nv04_graph_ctx_regs[] = { 30static uint32_t nv04_graph_ctx_regs[] = {
31 0x0040053c,
32 0x00400544,
33 0x00400540,
34 0x00400548,
31 NV04_PGRAPH_CTX_SWITCH1, 35 NV04_PGRAPH_CTX_SWITCH1,
32 NV04_PGRAPH_CTX_SWITCH2, 36 NV04_PGRAPH_CTX_SWITCH2,
33 NV04_PGRAPH_CTX_SWITCH3, 37 NV04_PGRAPH_CTX_SWITCH3,
@@ -102,69 +106,69 @@ static uint32_t nv04_graph_ctx_regs[] = {
102 NV04_PGRAPH_PATT_COLOR0, 106 NV04_PGRAPH_PATT_COLOR0,
103 NV04_PGRAPH_PATT_COLOR1, 107 NV04_PGRAPH_PATT_COLOR1,
104 NV04_PGRAPH_PATT_COLORRAM+0x00, 108 NV04_PGRAPH_PATT_COLORRAM+0x00,
105 NV04_PGRAPH_PATT_COLORRAM+0x01,
106 NV04_PGRAPH_PATT_COLORRAM+0x02,
107 NV04_PGRAPH_PATT_COLORRAM+0x03,
108 NV04_PGRAPH_PATT_COLORRAM+0x04, 109 NV04_PGRAPH_PATT_COLORRAM+0x04,
109 NV04_PGRAPH_PATT_COLORRAM+0x05,
110 NV04_PGRAPH_PATT_COLORRAM+0x06,
111 NV04_PGRAPH_PATT_COLORRAM+0x07,
112 NV04_PGRAPH_PATT_COLORRAM+0x08, 110 NV04_PGRAPH_PATT_COLORRAM+0x08,
113 NV04_PGRAPH_PATT_COLORRAM+0x09, 111 NV04_PGRAPH_PATT_COLORRAM+0x0c,
114 NV04_PGRAPH_PATT_COLORRAM+0x0A,
115 NV04_PGRAPH_PATT_COLORRAM+0x0B,
116 NV04_PGRAPH_PATT_COLORRAM+0x0C,
117 NV04_PGRAPH_PATT_COLORRAM+0x0D,
118 NV04_PGRAPH_PATT_COLORRAM+0x0E,
119 NV04_PGRAPH_PATT_COLORRAM+0x0F,
120 NV04_PGRAPH_PATT_COLORRAM+0x10, 112 NV04_PGRAPH_PATT_COLORRAM+0x10,
121 NV04_PGRAPH_PATT_COLORRAM+0x11,
122 NV04_PGRAPH_PATT_COLORRAM+0x12,
123 NV04_PGRAPH_PATT_COLORRAM+0x13,
124 NV04_PGRAPH_PATT_COLORRAM+0x14, 113 NV04_PGRAPH_PATT_COLORRAM+0x14,
125 NV04_PGRAPH_PATT_COLORRAM+0x15,
126 NV04_PGRAPH_PATT_COLORRAM+0x16,
127 NV04_PGRAPH_PATT_COLORRAM+0x17,
128 NV04_PGRAPH_PATT_COLORRAM+0x18, 114 NV04_PGRAPH_PATT_COLORRAM+0x18,
129 NV04_PGRAPH_PATT_COLORRAM+0x19, 115 NV04_PGRAPH_PATT_COLORRAM+0x1c,
130 NV04_PGRAPH_PATT_COLORRAM+0x1A,
131 NV04_PGRAPH_PATT_COLORRAM+0x1B,
132 NV04_PGRAPH_PATT_COLORRAM+0x1C,
133 NV04_PGRAPH_PATT_COLORRAM+0x1D,
134 NV04_PGRAPH_PATT_COLORRAM+0x1E,
135 NV04_PGRAPH_PATT_COLORRAM+0x1F,
136 NV04_PGRAPH_PATT_COLORRAM+0x20, 116 NV04_PGRAPH_PATT_COLORRAM+0x20,
137 NV04_PGRAPH_PATT_COLORRAM+0x21,
138 NV04_PGRAPH_PATT_COLORRAM+0x22,
139 NV04_PGRAPH_PATT_COLORRAM+0x23,
140 NV04_PGRAPH_PATT_COLORRAM+0x24, 117 NV04_PGRAPH_PATT_COLORRAM+0x24,
141 NV04_PGRAPH_PATT_COLORRAM+0x25,
142 NV04_PGRAPH_PATT_COLORRAM+0x26,
143 NV04_PGRAPH_PATT_COLORRAM+0x27,
144 NV04_PGRAPH_PATT_COLORRAM+0x28, 118 NV04_PGRAPH_PATT_COLORRAM+0x28,
145 NV04_PGRAPH_PATT_COLORRAM+0x29, 119 NV04_PGRAPH_PATT_COLORRAM+0x2c,
146 NV04_PGRAPH_PATT_COLORRAM+0x2A,
147 NV04_PGRAPH_PATT_COLORRAM+0x2B,
148 NV04_PGRAPH_PATT_COLORRAM+0x2C,
149 NV04_PGRAPH_PATT_COLORRAM+0x2D,
150 NV04_PGRAPH_PATT_COLORRAM+0x2E,
151 NV04_PGRAPH_PATT_COLORRAM+0x2F,
152 NV04_PGRAPH_PATT_COLORRAM+0x30, 120 NV04_PGRAPH_PATT_COLORRAM+0x30,
153 NV04_PGRAPH_PATT_COLORRAM+0x31,
154 NV04_PGRAPH_PATT_COLORRAM+0x32,
155 NV04_PGRAPH_PATT_COLORRAM+0x33,
156 NV04_PGRAPH_PATT_COLORRAM+0x34, 121 NV04_PGRAPH_PATT_COLORRAM+0x34,
157 NV04_PGRAPH_PATT_COLORRAM+0x35,
158 NV04_PGRAPH_PATT_COLORRAM+0x36,
159 NV04_PGRAPH_PATT_COLORRAM+0x37,
160 NV04_PGRAPH_PATT_COLORRAM+0x38, 122 NV04_PGRAPH_PATT_COLORRAM+0x38,
161 NV04_PGRAPH_PATT_COLORRAM+0x39, 123 NV04_PGRAPH_PATT_COLORRAM+0x3c,
162 NV04_PGRAPH_PATT_COLORRAM+0x3A, 124 NV04_PGRAPH_PATT_COLORRAM+0x40,
163 NV04_PGRAPH_PATT_COLORRAM+0x3B, 125 NV04_PGRAPH_PATT_COLORRAM+0x44,
164 NV04_PGRAPH_PATT_COLORRAM+0x3C, 126 NV04_PGRAPH_PATT_COLORRAM+0x48,
165 NV04_PGRAPH_PATT_COLORRAM+0x3D, 127 NV04_PGRAPH_PATT_COLORRAM+0x4c,
166 NV04_PGRAPH_PATT_COLORRAM+0x3E, 128 NV04_PGRAPH_PATT_COLORRAM+0x50,
167 NV04_PGRAPH_PATT_COLORRAM+0x3F, 129 NV04_PGRAPH_PATT_COLORRAM+0x54,
130 NV04_PGRAPH_PATT_COLORRAM+0x58,
131 NV04_PGRAPH_PATT_COLORRAM+0x5c,
132 NV04_PGRAPH_PATT_COLORRAM+0x60,
133 NV04_PGRAPH_PATT_COLORRAM+0x64,
134 NV04_PGRAPH_PATT_COLORRAM+0x68,
135 NV04_PGRAPH_PATT_COLORRAM+0x6c,
136 NV04_PGRAPH_PATT_COLORRAM+0x70,
137 NV04_PGRAPH_PATT_COLORRAM+0x74,
138 NV04_PGRAPH_PATT_COLORRAM+0x78,
139 NV04_PGRAPH_PATT_COLORRAM+0x7c,
140 NV04_PGRAPH_PATT_COLORRAM+0x80,
141 NV04_PGRAPH_PATT_COLORRAM+0x84,
142 NV04_PGRAPH_PATT_COLORRAM+0x88,
143 NV04_PGRAPH_PATT_COLORRAM+0x8c,
144 NV04_PGRAPH_PATT_COLORRAM+0x90,
145 NV04_PGRAPH_PATT_COLORRAM+0x94,
146 NV04_PGRAPH_PATT_COLORRAM+0x98,
147 NV04_PGRAPH_PATT_COLORRAM+0x9c,
148 NV04_PGRAPH_PATT_COLORRAM+0xa0,
149 NV04_PGRAPH_PATT_COLORRAM+0xa4,
150 NV04_PGRAPH_PATT_COLORRAM+0xa8,
151 NV04_PGRAPH_PATT_COLORRAM+0xac,
152 NV04_PGRAPH_PATT_COLORRAM+0xb0,
153 NV04_PGRAPH_PATT_COLORRAM+0xb4,
154 NV04_PGRAPH_PATT_COLORRAM+0xb8,
155 NV04_PGRAPH_PATT_COLORRAM+0xbc,
156 NV04_PGRAPH_PATT_COLORRAM+0xc0,
157 NV04_PGRAPH_PATT_COLORRAM+0xc4,
158 NV04_PGRAPH_PATT_COLORRAM+0xc8,
159 NV04_PGRAPH_PATT_COLORRAM+0xcc,
160 NV04_PGRAPH_PATT_COLORRAM+0xd0,
161 NV04_PGRAPH_PATT_COLORRAM+0xd4,
162 NV04_PGRAPH_PATT_COLORRAM+0xd8,
163 NV04_PGRAPH_PATT_COLORRAM+0xdc,
164 NV04_PGRAPH_PATT_COLORRAM+0xe0,
165 NV04_PGRAPH_PATT_COLORRAM+0xe4,
166 NV04_PGRAPH_PATT_COLORRAM+0xe8,
167 NV04_PGRAPH_PATT_COLORRAM+0xec,
168 NV04_PGRAPH_PATT_COLORRAM+0xf0,
169 NV04_PGRAPH_PATT_COLORRAM+0xf4,
170 NV04_PGRAPH_PATT_COLORRAM+0xf8,
171 NV04_PGRAPH_PATT_COLORRAM+0xfc,
168 NV04_PGRAPH_PATTERN, 172 NV04_PGRAPH_PATTERN,
169 0x0040080c, 173 0x0040080c,
170 NV04_PGRAPH_PATTERN_SHAPE, 174 NV04_PGRAPH_PATTERN_SHAPE,
@@ -247,14 +251,6 @@ static uint32_t nv04_graph_ctx_regs[] = {
247 0x004004f8, 251 0x004004f8,
248 0x0040047c, 252 0x0040047c,
249 0x004004fc, 253 0x004004fc,
250 0x0040053c,
251 0x00400544,
252 0x00400540,
253 0x00400548,
254 0x00400560,
255 0x00400568,
256 0x00400564,
257 0x0040056c,
258 0x00400534, 254 0x00400534,
259 0x00400538, 255 0x00400538,
260 0x00400514, 256 0x00400514,
@@ -341,9 +337,8 @@ static uint32_t nv04_graph_ctx_regs[] = {
341 0x00400500, 337 0x00400500,
342 0x00400504, 338 0x00400504,
343 NV04_PGRAPH_VALID1, 339 NV04_PGRAPH_VALID1,
344 NV04_PGRAPH_VALID2 340 NV04_PGRAPH_VALID2,
345 341 NV04_PGRAPH_DEBUG_3
346
347}; 342};
348 343
349struct graph_state { 344struct graph_state {
@@ -388,6 +383,18 @@ nv04_graph_context_switch(struct drm_device *dev)
388 pgraph->fifo_access(dev, true); 383 pgraph->fifo_access(dev, true);
389} 384}
390 385
386static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
387{
388 int i;
389
390 for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
391 if (nv04_graph_ctx_regs[i] == reg)
392 return &ctx->nv04[i];
393 }
394
395 return NULL;
396}
397
391int nv04_graph_create_context(struct nouveau_channel *chan) 398int nv04_graph_create_context(struct nouveau_channel *chan)
392{ 399{
393 struct graph_state *pgraph_ctx; 400 struct graph_state *pgraph_ctx;
@@ -398,15 +405,8 @@ int nv04_graph_create_context(struct nouveau_channel *chan)
398 if (pgraph_ctx == NULL) 405 if (pgraph_ctx == NULL)
399 return -ENOMEM; 406 return -ENOMEM;
400 407
401 /* dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; */ 408 *ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
402 pgraph_ctx->nv04[0] = 0x0001ffff; 409
403 /* is it really needed ??? */
404#if 0
405 dev_priv->fifos[channel].pgraph_ctx[1] =
406 nv_rd32(dev, NV_PGRAPH_DEBUG_4);
407 dev_priv->fifos[channel].pgraph_ctx[2] =
408 nv_rd32(dev, 0x004006b0);
409#endif
410 return 0; 410 return 0;
411} 411}
412 412
@@ -429,9 +429,13 @@ int nv04_graph_load_context(struct nouveau_channel *chan)
429 nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]); 429 nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
430 430
431 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100); 431 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
432 nv_wr32(dev, NV04_PGRAPH_CTX_USER, chan->id << 24); 432
433 tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
434 nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp | chan->id << 24);
435
433 tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2); 436 tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2);
434 nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff); 437 nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff);
438
435 return 0; 439 return 0;
436} 440}
437 441
@@ -494,7 +498,7 @@ int nv04_graph_init(struct drm_device *dev)
494 nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF); 498 nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF);
495 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100); 499 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
496 tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; 500 tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
497 tmp |= dev_priv->engine.fifo.channels << 24; 501 tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
498 nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp); 502 nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
499 503
500 /* These don't belong here, they're part of a per-channel context */ 504 /* These don't belong here, they're part of a per-channel context */
@@ -533,7 +537,7 @@ nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
533 int mthd, uint32_t data) 537 int mthd, uint32_t data)
534{ 538{
535 struct drm_device *dev = chan->dev; 539 struct drm_device *dev = chan->dev;
536 uint32_t instance = nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff; 540 uint32_t instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
537 int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; 541 int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
538 uint32_t tmp; 542 uint32_t tmp;
539 543
@@ -547,7 +551,7 @@ nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
547 return 0; 551 return 0;
548} 552}
549 553
550static struct nouveau_pgraph_object_method nv04_graph_mthds_m2mf[] = { 554static struct nouveau_pgraph_object_method nv04_graph_mthds_sw[] = {
551 { 0x0150, nv04_graph_mthd_set_ref }, 555 { 0x0150, nv04_graph_mthd_set_ref },
552 {} 556 {}
553}; 557};
@@ -558,7 +562,7 @@ static struct nouveau_pgraph_object_method nv04_graph_mthds_set_operation[] = {
558}; 562};
559 563
560struct nouveau_pgraph_object_class nv04_graph_grclass[] = { 564struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
561 { 0x0039, false, nv04_graph_mthds_m2mf }, 565 { 0x0039, false, NULL },
562 { 0x004a, false, nv04_graph_mthds_set_operation }, /* gdirect */ 566 { 0x004a, false, nv04_graph_mthds_set_operation }, /* gdirect */
563 { 0x005f, false, nv04_graph_mthds_set_operation }, /* imageblit */ 567 { 0x005f, false, nv04_graph_mthds_set_operation }, /* imageblit */
564 { 0x0061, false, nv04_graph_mthds_set_operation }, /* ifc */ 568 { 0x0061, false, nv04_graph_mthds_set_operation }, /* ifc */
@@ -574,6 +578,7 @@ struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
574 { 0x0053, false, NULL }, /* surf3d */ 578 { 0x0053, false, NULL }, /* surf3d */
575 { 0x0054, false, NULL }, /* tex_tri */ 579 { 0x0054, false, NULL }, /* tex_tri */
576 { 0x0055, false, NULL }, /* multitex_tri */ 580 { 0x0055, false, NULL }, /* multitex_tri */
581 { 0x506e, true, nv04_graph_mthds_sw },
577 {} 582 {}
578}; 583};
579 584
diff --git a/drivers/gpu/drm/nouveau/nv04_instmem.c b/drivers/gpu/drm/nouveau/nv04_instmem.c
index a20c206625a2..a3b9563a6f60 100644
--- a/drivers/gpu/drm/nouveau/nv04_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv04_instmem.c
@@ -30,7 +30,7 @@ nv04_instmem_determine_amount(struct drm_device *dev)
30 * of vram. For now, only reserve a small piece until we know 30 * of vram. For now, only reserve a small piece until we know
31 * more about what each chipset requires. 31 * more about what each chipset requires.
32 */ 32 */
33 switch (dev_priv->chipset & 0xf0) { 33 switch (dev_priv->chipset) {
34 case 0x40: 34 case 0x40:
35 case 0x47: 35 case 0x47:
36 case 0x49: 36 case 0x49:
diff --git a/drivers/gpu/drm/nouveau/nv10_fb.c b/drivers/gpu/drm/nouveau/nv10_fb.c
index 79e2d104d70a..cc5cda44e501 100644
--- a/drivers/gpu/drm/nouveau/nv10_fb.c
+++ b/drivers/gpu/drm/nouveau/nv10_fb.c
@@ -3,17 +3,37 @@
3#include "nouveau_drv.h" 3#include "nouveau_drv.h"
4#include "nouveau_drm.h" 4#include "nouveau_drm.h"
5 5
6void
7nv10_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
8 uint32_t size, uint32_t pitch)
9{
10 struct drm_nouveau_private *dev_priv = dev->dev_private;
11 uint32_t limit = max(1u, addr + size) - 1;
12
13 if (pitch) {
14 if (dev_priv->card_type >= NV_20)
15 addr |= 1;
16 else
17 addr |= 1 << 31;
18 }
19
20 nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
21 nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
22 nv_wr32(dev, NV10_PFB_TILE(i), addr);
23}
24
6int 25int
7nv10_fb_init(struct drm_device *dev) 26nv10_fb_init(struct drm_device *dev)
8{ 27{
9 uint32_t fb_bar_size; 28 struct drm_nouveau_private *dev_priv = dev->dev_private;
29 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
10 int i; 30 int i;
11 31
12 fb_bar_size = drm_get_resource_len(dev, 0) - 1; 32 pfb->num_tiles = NV10_PFB_TILE__SIZE;
13 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { 33
14 nv_wr32(dev, NV10_PFB_TILE(i), 0); 34 /* Turn all the tiling regions off. */
15 nv_wr32(dev, NV10_PFB_TLIMIT(i), fb_bar_size); 35 for (i = 0; i < pfb->num_tiles; i++)
16 } 36 pfb->set_region_tiling(dev, i, 0, 0, 0);
17 37
18 return 0; 38 return 0;
19} 39}
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index 6870e0ee2e7e..fcf2cdd19493 100644
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -807,6 +807,20 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan)
807 chan->pgraph_ctx = NULL; 807 chan->pgraph_ctx = NULL;
808} 808}
809 809
810void
811nv10_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
812 uint32_t size, uint32_t pitch)
813{
814 uint32_t limit = max(1u, addr + size) - 1;
815
816 if (pitch)
817 addr |= 1 << 31;
818
819 nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), limit);
820 nv_wr32(dev, NV10_PGRAPH_TSIZE(i), pitch);
821 nv_wr32(dev, NV10_PGRAPH_TILE(i), addr);
822}
823
810int nv10_graph_init(struct drm_device *dev) 824int nv10_graph_init(struct drm_device *dev)
811{ 825{
812 struct drm_nouveau_private *dev_priv = dev->dev_private; 826 struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -838,17 +852,9 @@ int nv10_graph_init(struct drm_device *dev)
838 } else 852 } else
839 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000); 853 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);
840 854
841 /* copy tile info from PFB */ 855 /* Turn all the tiling regions off. */
842 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { 856 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
843 nv_wr32(dev, NV10_PGRAPH_TILE(i), 857 nv10_graph_set_region_tiling(dev, i, 0, 0, 0);
844 nv_rd32(dev, NV10_PFB_TILE(i)));
845 nv_wr32(dev, NV10_PGRAPH_TLIMIT(i),
846 nv_rd32(dev, NV10_PFB_TLIMIT(i)));
847 nv_wr32(dev, NV10_PGRAPH_TSIZE(i),
848 nv_rd32(dev, NV10_PFB_TSIZE(i)));
849 nv_wr32(dev, NV10_PGRAPH_TSTATUS(i),
850 nv_rd32(dev, NV10_PFB_TSTATUS(i)));
851 }
852 858
853 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH1, 0x00000000); 859 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH1, 0x00000000);
854 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH2, 0x00000000); 860 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH2, 0x00000000);
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
index 81c01353a9f9..21ac6e49b6ee 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -33,13 +33,103 @@
33#include "nouveau_hw.h" 33#include "nouveau_hw.h"
34#include "nv17_tv.h" 34#include "nv17_tv.h"
35 35
36enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder, 36static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
37 struct drm_connector *connector,
38 uint32_t pin_mask)
39{ 37{
38 struct drm_device *dev = encoder->dev;
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
40 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
41 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
42 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
43 uint32_t sample = 0;
44 int head;
45
46#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
47 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
48 if (dev_priv->vbios->tvdactestval)
49 testval = dev_priv->vbios->tvdactestval;
50
51 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
52 head = (dacclk & 0x100) >> 8;
53
54 /* Save the previous state. */
55 gpio1 = nv17_gpio_get(dev, DCB_GPIO_TVDAC1);
56 gpio0 = nv17_gpio_get(dev, DCB_GPIO_TVDAC0);
57 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
58 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
59 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
60 fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
61 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
62 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
63 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
64 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
65
66 /* Prepare the DAC for load detection. */
67 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, true);
68 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, true);
69
70 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
71 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
72 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
73 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
74 NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
75 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
76 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
77 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
78 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
79
80 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
81
82 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
83 (dacclk & ~0xff) | 0x22);
84 msleep(1);
85 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
86 (dacclk & ~0xff) | 0x21);
87
88 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
89 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
90
91 /* Sample pin 0x4 (usually S-video luma). */
92 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
93 msleep(20);
94 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
95 & 0x4 << 28;
96
97 /* Sample the remaining pins. */
98 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
99 msleep(20);
100 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
101 & 0xa << 28;
102
103 /* Restore the previous state. */
104 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
105 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
106 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
107 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
108 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
109 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
110 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
111 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
112 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
113 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, gpio1);
114 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, gpio0);
115
116 return sample;
117}
118
119static enum drm_connector_status
120nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
121{
122 struct drm_device *dev = encoder->dev;
123 struct drm_nouveau_private *dev_priv = dev->dev_private;
124 struct drm_mode_config *conf = &dev->mode_config;
40 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 125 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
126 struct dcb_entry *dcb = tv_enc->base.dcb;
41 127
42 tv_enc->pin_mask = pin_mask >> 28 & 0xe; 128 if (dev_priv->chipset == 0x42 ||
129 dev_priv->chipset == 0x43)
130 tv_enc->pin_mask = nv42_tv_sample_load(encoder) >> 28 & 0xe;
131 else
132 tv_enc->pin_mask = nv17_dac_sample_load(encoder) >> 28 & 0xe;
43 133
44 switch (tv_enc->pin_mask) { 134 switch (tv_enc->pin_mask) {
45 case 0x2: 135 case 0x2:
@@ -50,7 +140,7 @@ enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
50 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO; 140 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
51 break; 141 break;
52 case 0xe: 142 case 0xe:
53 if (nouveau_encoder(encoder)->dcb->tvconf.has_component_output) 143 if (dcb->tvconf.has_component_output)
54 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component; 144 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
55 else 145 else
56 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART; 146 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
@@ -61,11 +151,16 @@ enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
61 } 151 }
62 152
63 drm_connector_property_set_value(connector, 153 drm_connector_property_set_value(connector,
64 encoder->dev->mode_config.tv_subconnector_property, 154 conf->tv_subconnector_property,
65 tv_enc->subconnector); 155 tv_enc->subconnector);
66 156
67 return tv_enc->subconnector ? connector_status_connected : 157 if (tv_enc->subconnector) {
68 connector_status_disconnected; 158 NV_INFO(dev, "Load detected on output %c\n",
159 '@' + ffs(dcb->or));
160 return connector_status_connected;
161 } else {
162 return connector_status_disconnected;
163 }
69} 164}
70 165
71static const struct { 166static const struct {
@@ -484,6 +579,8 @@ static void nv17_tv_restore(struct drm_encoder *encoder)
484 nouveau_encoder(encoder)->restore.output); 579 nouveau_encoder(encoder)->restore.output);
485 580
486 nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state); 581 nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
582
583 nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
487} 584}
488 585
489static int nv17_tv_create_resources(struct drm_encoder *encoder, 586static int nv17_tv_create_resources(struct drm_encoder *encoder,
@@ -633,7 +730,7 @@ static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
633 .prepare = nv17_tv_prepare, 730 .prepare = nv17_tv_prepare,
634 .commit = nv17_tv_commit, 731 .commit = nv17_tv_commit,
635 .mode_set = nv17_tv_mode_set, 732 .mode_set = nv17_tv_mode_set,
636 .detect = nv17_dac_detect, 733 .detect = nv17_tv_detect,
637}; 734};
638 735
639static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = { 736static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c
index 18ba74f19703..d6fc0a82f03d 100644
--- a/drivers/gpu/drm/nouveau/nv20_graph.c
+++ b/drivers/gpu/drm/nouveau/nv20_graph.c
@@ -514,6 +514,27 @@ nv20_graph_rdi(struct drm_device *dev)
514 nouveau_wait_for_idle(dev); 514 nouveau_wait_for_idle(dev);
515} 515}
516 516
517void
518nv20_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
519 uint32_t size, uint32_t pitch)
520{
521 uint32_t limit = max(1u, addr + size) - 1;
522
523 if (pitch)
524 addr |= 1;
525
526 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
527 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
528 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
529
530 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
531 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, limit);
532 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
533 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, pitch);
534 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
535 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, addr);
536}
537
517int 538int
518nv20_graph_init(struct drm_device *dev) 539nv20_graph_init(struct drm_device *dev)
519{ 540{
@@ -572,27 +593,10 @@ nv20_graph_init(struct drm_device *dev)
572 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030); 593 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030);
573 } 594 }
574 595
575 /* copy tile info from PFB */ 596 /* Turn all the tiling regions off. */
576 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { 597 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
577 nv_wr32(dev, 0x00400904 + i * 0x10, 598 nv20_graph_set_region_tiling(dev, i, 0, 0, 0);
578 nv_rd32(dev, NV10_PFB_TLIMIT(i))); 599
579 /* which is NV40_PGRAPH_TLIMIT0(i) ?? */
580 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + i * 4);
581 nv_wr32(dev, NV10_PGRAPH_RDI_DATA,
582 nv_rd32(dev, NV10_PFB_TLIMIT(i)));
583 nv_wr32(dev, 0x00400908 + i * 0x10,
584 nv_rd32(dev, NV10_PFB_TSIZE(i)));
585 /* which is NV40_PGRAPH_TSIZE0(i) ?? */
586 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + i * 4);
587 nv_wr32(dev, NV10_PGRAPH_RDI_DATA,
588 nv_rd32(dev, NV10_PFB_TSIZE(i)));
589 nv_wr32(dev, 0x00400900 + i * 0x10,
590 nv_rd32(dev, NV10_PFB_TILE(i)));
591 /* which is NV40_PGRAPH_TILE0(i) ?? */
592 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + i * 4);
593 nv_wr32(dev, NV10_PGRAPH_RDI_DATA,
594 nv_rd32(dev, NV10_PFB_TILE(i)));
595 }
596 for (i = 0; i < 8; i++) { 600 for (i = 0; i < 8; i++) {
597 nv_wr32(dev, 0x400980 + i * 4, nv_rd32(dev, 0x100300 + i * 4)); 601 nv_wr32(dev, 0x400980 + i * 4, nv_rd32(dev, 0x100300 + i * 4));
598 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0090 + i * 4); 602 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0090 + i * 4);
@@ -704,18 +708,9 @@ nv30_graph_init(struct drm_device *dev)
704 708
705 nv_wr32(dev, 0x4000c0, 0x00000016); 709 nv_wr32(dev, 0x4000c0, 0x00000016);
706 710
707 /* copy tile info from PFB */ 711 /* Turn all the tiling regions off. */
708 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { 712 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
709 nv_wr32(dev, 0x00400904 + i * 0x10, 713 nv20_graph_set_region_tiling(dev, i, 0, 0, 0);
710 nv_rd32(dev, NV10_PFB_TLIMIT(i)));
711 /* which is NV40_PGRAPH_TLIMIT0(i) ?? */
712 nv_wr32(dev, 0x00400908 + i * 0x10,
713 nv_rd32(dev, NV10_PFB_TSIZE(i)));
714 /* which is NV40_PGRAPH_TSIZE0(i) ?? */
715 nv_wr32(dev, 0x00400900 + i * 0x10,
716 nv_rd32(dev, NV10_PFB_TILE(i)));
717 /* which is NV40_PGRAPH_TILE0(i) ?? */
718 }
719 714
720 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 715 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
721 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); 716 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
diff --git a/drivers/gpu/drm/nouveau/nv40_fb.c b/drivers/gpu/drm/nouveau/nv40_fb.c
index ca1d27107a8e..3cd07d8d5bd7 100644
--- a/drivers/gpu/drm/nouveau/nv40_fb.c
+++ b/drivers/gpu/drm/nouveau/nv40_fb.c
@@ -3,12 +3,37 @@
3#include "nouveau_drv.h" 3#include "nouveau_drv.h"
4#include "nouveau_drm.h" 4#include "nouveau_drm.h"
5 5
6void
7nv40_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
8 uint32_t size, uint32_t pitch)
9{
10 struct drm_nouveau_private *dev_priv = dev->dev_private;
11 uint32_t limit = max(1u, addr + size) - 1;
12
13 if (pitch)
14 addr |= 1;
15
16 switch (dev_priv->chipset) {
17 case 0x40:
18 nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
19 nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
20 nv_wr32(dev, NV10_PFB_TILE(i), addr);
21 break;
22
23 default:
24 nv_wr32(dev, NV40_PFB_TLIMIT(i), limit);
25 nv_wr32(dev, NV40_PFB_TSIZE(i), pitch);
26 nv_wr32(dev, NV40_PFB_TILE(i), addr);
27 break;
28 }
29}
30
6int 31int
7nv40_fb_init(struct drm_device *dev) 32nv40_fb_init(struct drm_device *dev)
8{ 33{
9 struct drm_nouveau_private *dev_priv = dev->dev_private; 34 struct drm_nouveau_private *dev_priv = dev->dev_private;
10 uint32_t fb_bar_size, tmp; 35 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
11 int num_tiles; 36 uint32_t tmp;
12 int i; 37 int i;
13 38
14 /* This is strictly a NV4x register (don't know about NV5x). */ 39 /* This is strictly a NV4x register (don't know about NV5x). */
@@ -23,35 +48,23 @@ nv40_fb_init(struct drm_device *dev)
23 case 0x45: 48 case 0x45:
24 tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2); 49 tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2);
25 nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15)); 50 nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15));
26 num_tiles = NV10_PFB_TILE__SIZE; 51 pfb->num_tiles = NV10_PFB_TILE__SIZE;
27 break; 52 break;
28 case 0x46: /* G72 */ 53 case 0x46: /* G72 */
29 case 0x47: /* G70 */ 54 case 0x47: /* G70 */
30 case 0x49: /* G71 */ 55 case 0x49: /* G71 */
31 case 0x4b: /* G73 */ 56 case 0x4b: /* G73 */
32 case 0x4c: /* C51 (G7X version) */ 57 case 0x4c: /* C51 (G7X version) */
33 num_tiles = NV40_PFB_TILE__SIZE_1; 58 pfb->num_tiles = NV40_PFB_TILE__SIZE_1;
34 break; 59 break;
35 default: 60 default:
36 num_tiles = NV40_PFB_TILE__SIZE_0; 61 pfb->num_tiles = NV40_PFB_TILE__SIZE_0;
37 break; 62 break;
38 } 63 }
39 64
40 fb_bar_size = drm_get_resource_len(dev, 0) - 1; 65 /* Turn all the tiling regions off. */
41 switch (dev_priv->chipset) { 66 for (i = 0; i < pfb->num_tiles; i++)
42 case 0x40: 67 pfb->set_region_tiling(dev, i, 0, 0, 0);
43 for (i = 0; i < num_tiles; i++) {
44 nv_wr32(dev, NV10_PFB_TILE(i), 0);
45 nv_wr32(dev, NV10_PFB_TLIMIT(i), fb_bar_size);
46 }
47 break;
48 default:
49 for (i = 0; i < num_tiles; i++) {
50 nv_wr32(dev, NV40_PFB_TILE(i), 0);
51 nv_wr32(dev, NV40_PFB_TLIMIT(i), fb_bar_size);
52 }
53 break;
54 }
55 68
56 return 0; 69 return 0;
57} 70}
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 2b332bb55acf..53e8afe1dcd1 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -181,6 +181,48 @@ nv40_graph_unload_context(struct drm_device *dev)
181 return ret; 181 return ret;
182} 182}
183 183
184void
185nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
186 uint32_t size, uint32_t pitch)
187{
188 struct drm_nouveau_private *dev_priv = dev->dev_private;
189 uint32_t limit = max(1u, addr + size) - 1;
190
191 if (pitch)
192 addr |= 1;
193
194 switch (dev_priv->chipset) {
195 case 0x44:
196 case 0x4a:
197 case 0x4e:
198 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
199 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
200 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
201 break;
202
203 case 0x46:
204 case 0x47:
205 case 0x49:
206 case 0x4b:
207 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
208 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
209 nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
210 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
211 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
212 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
213 break;
214
215 default:
216 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
217 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
218 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
219 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
220 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
221 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
222 break;
223 }
224}
225
184/* 226/*
185 * G70 0x47 227 * G70 0x47
186 * G71 0x49 228 * G71 0x49
@@ -195,7 +237,8 @@ nv40_graph_init(struct drm_device *dev)
195{ 237{
196 struct drm_nouveau_private *dev_priv = 238 struct drm_nouveau_private *dev_priv =
197 (struct drm_nouveau_private *)dev->dev_private; 239 (struct drm_nouveau_private *)dev->dev_private;
198 uint32_t vramsz, tmp; 240 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
241 uint32_t vramsz;
199 int i, j; 242 int i, j;
200 243
201 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & 244 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
@@ -292,74 +335,9 @@ nv40_graph_init(struct drm_device *dev)
292 nv_wr32(dev, 0x400b38, 0x2ffff800); 335 nv_wr32(dev, 0x400b38, 0x2ffff800);
293 nv_wr32(dev, 0x400b3c, 0x00006000); 336 nv_wr32(dev, 0x400b3c, 0x00006000);
294 337
295 /* copy tile info from PFB */ 338 /* Turn all the tiling regions off. */
296 switch (dev_priv->chipset) { 339 for (i = 0; i < pfb->num_tiles; i++)
297 case 0x40: /* vanilla NV40 */ 340 nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
298 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
299 tmp = nv_rd32(dev, NV10_PFB_TILE(i));
300 nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
301 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
302 tmp = nv_rd32(dev, NV10_PFB_TLIMIT(i));
303 nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
304 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
305 tmp = nv_rd32(dev, NV10_PFB_TSIZE(i));
306 nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
307 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
308 tmp = nv_rd32(dev, NV10_PFB_TSTATUS(i));
309 nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
310 nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
311 }
312 break;
313 case 0x44:
314 case 0x4a:
315 case 0x4e: /* NV44-based cores don't have 0x406900? */
316 for (i = 0; i < NV40_PFB_TILE__SIZE_0; i++) {
317 tmp = nv_rd32(dev, NV40_PFB_TILE(i));
318 nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
319 tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
320 nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
321 tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
322 nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
323 tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
324 nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
325 }
326 break;
327 case 0x46:
328 case 0x47:
329 case 0x49:
330 case 0x4b: /* G7X-based cores */
331 for (i = 0; i < NV40_PFB_TILE__SIZE_1; i++) {
332 tmp = nv_rd32(dev, NV40_PFB_TILE(i));
333 nv_wr32(dev, NV47_PGRAPH_TILE0(i), tmp);
334 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
335 tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
336 nv_wr32(dev, NV47_PGRAPH_TLIMIT0(i), tmp);
337 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
338 tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
339 nv_wr32(dev, NV47_PGRAPH_TSIZE0(i), tmp);
340 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
341 tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
342 nv_wr32(dev, NV47_PGRAPH_TSTATUS0(i), tmp);
343 nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
344 }
345 break;
346 default: /* everything else */
347 for (i = 0; i < NV40_PFB_TILE__SIZE_0; i++) {
348 tmp = nv_rd32(dev, NV40_PFB_TILE(i));
349 nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
350 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
351 tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
352 nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
353 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
354 tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
355 nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
356 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
357 tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
358 nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
359 nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
360 }
361 break;
362 }
363 341
364 /* begin RAM config */ 342 /* begin RAM config */
365 vramsz = drm_get_resource_len(dev, 0) - 1; 343 vramsz = drm_get_resource_len(dev, 0) - 1;
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index 118d3285fd8c..d1a651e3400c 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -298,14 +298,17 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
298static void 298static void
299nv50_crtc_destroy(struct drm_crtc *crtc) 299nv50_crtc_destroy(struct drm_crtc *crtc)
300{ 300{
301 struct drm_device *dev = crtc->dev; 301 struct drm_device *dev;
302 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 302 struct nouveau_crtc *nv_crtc;
303
304 NV_DEBUG_KMS(dev, "\n");
305 303
306 if (!crtc) 304 if (!crtc)
307 return; 305 return;
308 306
307 dev = crtc->dev;
308 nv_crtc = nouveau_crtc(crtc);
309
310 NV_DEBUG_KMS(dev, "\n");
311
309 drm_crtc_cleanup(&nv_crtc->base); 312 drm_crtc_cleanup(&nv_crtc->base);
310 313
311 nv50_cursor_fini(nv_crtc); 314 nv50_cursor_fini(nv_crtc);
@@ -432,6 +435,7 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
432 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 435 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
433 struct drm_device *dev = crtc->dev; 436 struct drm_device *dev = crtc->dev;
434 struct drm_encoder *encoder; 437 struct drm_encoder *encoder;
438 uint32_t dac = 0, sor = 0;
435 439
436 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 440 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
437 441
@@ -439,9 +443,28 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
439 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 443 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
440 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 444 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
441 445
442 if (drm_helper_encoder_in_use(encoder)) 446 if (!drm_helper_encoder_in_use(encoder))
443 continue; 447 continue;
444 448
449 if (nv_encoder->dcb->type == OUTPUT_ANALOG ||
450 nv_encoder->dcb->type == OUTPUT_TV)
451 dac |= (1 << nv_encoder->or);
452 else
453 sor |= (1 << nv_encoder->or);
454 }
455
456 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
457 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
458
459 if (nv_encoder->dcb->type == OUTPUT_ANALOG ||
460 nv_encoder->dcb->type == OUTPUT_TV) {
461 if (dac & (1 << nv_encoder->or))
462 continue;
463 } else {
464 if (sor & (1 << nv_encoder->or))
465 continue;
466 }
467
445 nv_encoder->disconnect(nv_encoder); 468 nv_encoder->disconnect(nv_encoder);
446 } 469 }
447 470
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index a9263d92a231..90f0bf59fbcd 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -690,9 +690,21 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
690 int pxclk) 690 int pxclk)
691{ 691{
692 struct drm_nouveau_private *dev_priv = dev->dev_private; 692 struct drm_nouveau_private *dev_priv = dev->dev_private;
693 struct nouveau_connector *nv_connector = NULL;
694 struct drm_encoder *encoder;
693 struct nvbios *bios = &dev_priv->VBIOS; 695 struct nvbios *bios = &dev_priv->VBIOS;
694 uint32_t mc, script = 0, or; 696 uint32_t mc, script = 0, or;
695 697
698 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
699 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
700
701 if (nv_encoder->dcb != dcbent)
702 continue;
703
704 nv_connector = nouveau_encoder_connector_get(nv_encoder);
705 break;
706 }
707
696 or = ffs(dcbent->or) - 1; 708 or = ffs(dcbent->or) - 1;
697 mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or); 709 mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or);
698 switch (dcbent->type) { 710 switch (dcbent->type) {
@@ -711,6 +723,11 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
711 } else 723 } else
712 if (bios->fp.strapless_is_24bit & 1) 724 if (bios->fp.strapless_is_24bit & 1)
713 script |= 0x0200; 725 script |= 0x0200;
726
727 if (nv_connector && nv_connector->edid &&
728 (nv_connector->edid->revision >= 4) &&
729 (nv_connector->edid->input & 0x70) >= 0x20)
730 script |= 0x0200;
714 } 731 }
715 732
716 if (nouveau_uscript_lvds >= 0) { 733 if (nouveau_uscript_lvds >= 0) {
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c
index 6bcc6d39e9b0..0f57cdf7ccb2 100644
--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
@@ -3,7 +3,7 @@
3#include "nouveau_dma.h" 3#include "nouveau_dma.h"
4#include "nouveau_fbcon.h" 4#include "nouveau_fbcon.h"
5 5
6static void 6void
7nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 7nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
8{ 8{
9 struct nouveau_fbcon_par *par = info->par; 9 struct nouveau_fbcon_par *par = info->par;
@@ -16,9 +16,7 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
16 16
17 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && 17 if (!(info->flags & FBINFO_HWACCEL_DISABLED) &&
18 RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11)) { 18 RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11)) {
19 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 19 nouveau_fbcon_gpu_lockup(info);
20
21 info->flags |= FBINFO_HWACCEL_DISABLED;
22 } 20 }
23 21
24 if (info->flags & FBINFO_HWACCEL_DISABLED) { 22 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -31,7 +29,11 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
31 OUT_RING(chan, 1); 29 OUT_RING(chan, 1);
32 } 30 }
33 BEGIN_RING(chan, NvSub2D, 0x0588, 1); 31 BEGIN_RING(chan, NvSub2D, 0x0588, 1);
34 OUT_RING(chan, rect->color); 32 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
33 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
34 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
35 else
36 OUT_RING(chan, rect->color);
35 BEGIN_RING(chan, NvSub2D, 0x0600, 4); 37 BEGIN_RING(chan, NvSub2D, 0x0600, 4);
36 OUT_RING(chan, rect->dx); 38 OUT_RING(chan, rect->dx);
37 OUT_RING(chan, rect->dy); 39 OUT_RING(chan, rect->dy);
@@ -44,7 +46,7 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
44 FIRE_RING(chan); 46 FIRE_RING(chan);
45} 47}
46 48
47static void 49void
48nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) 50nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
49{ 51{
50 struct nouveau_fbcon_par *par = info->par; 52 struct nouveau_fbcon_par *par = info->par;
@@ -56,9 +58,7 @@ nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
56 return; 58 return;
57 59
58 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 12)) { 60 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 12)) {
59 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 61 nouveau_fbcon_gpu_lockup(info);
60
61 info->flags |= FBINFO_HWACCEL_DISABLED;
62 } 62 }
63 63
64 if (info->flags & FBINFO_HWACCEL_DISABLED) { 64 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -81,7 +81,7 @@ nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
81 FIRE_RING(chan); 81 FIRE_RING(chan);
82} 82}
83 83
84static void 84void
85nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) 85nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
86{ 86{
87 struct nouveau_fbcon_par *par = info->par; 87 struct nouveau_fbcon_par *par = info->par;
@@ -101,8 +101,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
101 } 101 }
102 102
103 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 11)) { 103 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 11)) {
104 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 104 nouveau_fbcon_gpu_lockup(info);
105 info->flags |= FBINFO_HWACCEL_DISABLED;
106 } 105 }
107 106
108 if (info->flags & FBINFO_HWACCEL_DISABLED) { 107 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -135,9 +134,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
135 int push = dwords > 2047 ? 2047 : dwords; 134 int push = dwords > 2047 ? 2047 : dwords;
136 135
137 if (RING_SPACE(chan, push + 1)) { 136 if (RING_SPACE(chan, push + 1)) {
138 NV_ERROR(dev, 137 nouveau_fbcon_gpu_lockup(info);
139 "GPU lockup - switching to software fbcon\n");
140 info->flags |= FBINFO_HWACCEL_DISABLED;
141 cfb_imageblit(info, image); 138 cfb_imageblit(info, image);
142 return; 139 return;
143 } 140 }
@@ -199,7 +196,7 @@ nv50_fbcon_accel_init(struct fb_info *info)
199 196
200 ret = RING_SPACE(chan, 59); 197 ret = RING_SPACE(chan, 59);
201 if (ret) { 198 if (ret) {
202 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 199 nouveau_fbcon_gpu_lockup(info);
203 return ret; 200 return ret;
204 } 201 }
205 202
@@ -265,9 +262,6 @@ nv50_fbcon_accel_init(struct fb_info *info)
265 OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys + 262 OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys +
266 dev_priv->vm_vram_base); 263 dev_priv->vm_vram_base);
267 264
268 info->fbops->fb_fillrect = nv50_fbcon_fillrect;
269 info->fbops->fb_copyarea = nv50_fbcon_copyarea;
270 info->fbops->fb_imageblit = nv50_fbcon_imageblit;
271 return 0; 265 return 0;
272} 266}
273 267
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index b7282284f080..204a79ff10f4 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -272,7 +272,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
272 return ret; 272 return ret;
273 ramfc = chan->ramfc->gpuobj; 273 ramfc = chan->ramfc->gpuobj;
274 274
275 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 256, 275 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 1024,
276 0, &chan->cache); 276 0, &chan->cache);
277 if (ret) 277 if (ret)
278 return ret; 278 return ret;
@@ -317,17 +317,20 @@ void
317nv50_fifo_destroy_context(struct nouveau_channel *chan) 317nv50_fifo_destroy_context(struct nouveau_channel *chan)
318{ 318{
319 struct drm_device *dev = chan->dev; 319 struct drm_device *dev = chan->dev;
320 struct nouveau_gpuobj_ref *ramfc = chan->ramfc;
320 321
321 NV_DEBUG(dev, "ch%d\n", chan->id); 322 NV_DEBUG(dev, "ch%d\n", chan->id);
322 323
323 nouveau_gpuobj_ref_del(dev, &chan->ramfc); 324 /* This will ensure the channel is seen as disabled. */
324 nouveau_gpuobj_ref_del(dev, &chan->cache); 325 chan->ramfc = NULL;
325
326 nv50_fifo_channel_disable(dev, chan->id, false); 326 nv50_fifo_channel_disable(dev, chan->id, false);
327 327
328 /* Dummy channel, also used on ch 127 */ 328 /* Dummy channel, also used on ch 127 */
329 if (chan->id == 0) 329 if (chan->id == 0)
330 nv50_fifo_channel_disable(dev, 127, false); 330 nv50_fifo_channel_disable(dev, 127, false);
331
332 nouveau_gpuobj_ref_del(dev, &ramfc);
333 nouveau_gpuobj_ref_del(dev, &chan->cache);
331} 334}
332 335
333int 336int
@@ -384,8 +387,8 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
384 nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr), 387 nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr),
385 nv_ro32(dev, cache, (ptr * 2) + 1)); 388 nv_ro32(dev, cache, (ptr * 2) + 1));
386 } 389 }
387 nv_wr32(dev, 0x3210, cnt << 2); 390 nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, cnt << 2);
388 nv_wr32(dev, 0x3270, 0); 391 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
389 392
390 /* guessing that all the 0x34xx regs aren't on NV50 */ 393 /* guessing that all the 0x34xx regs aren't on NV50 */
391 if (!IS_G80) { 394 if (!IS_G80) {
@@ -398,8 +401,6 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
398 401
399 dev_priv->engine.instmem.finish_access(dev); 402 dev_priv->engine.instmem.finish_access(dev);
400 403
401 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
402 nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
403 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16)); 404 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
404 return 0; 405 return 0;
405} 406}
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index ca79f32be44c..6d504801b514 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -84,7 +84,7 @@ nv50_graph_init_regs__nv(struct drm_device *dev)
84 nv_wr32(dev, 0x400804, 0xc0000000); 84 nv_wr32(dev, 0x400804, 0xc0000000);
85 nv_wr32(dev, 0x406800, 0xc0000000); 85 nv_wr32(dev, 0x406800, 0xc0000000);
86 nv_wr32(dev, 0x400c04, 0xc0000000); 86 nv_wr32(dev, 0x400c04, 0xc0000000);
87 nv_wr32(dev, 0x401804, 0xc0000000); 87 nv_wr32(dev, 0x401800, 0xc0000000);
88 nv_wr32(dev, 0x405018, 0xc0000000); 88 nv_wr32(dev, 0x405018, 0xc0000000);
89 nv_wr32(dev, 0x402000, 0xc0000000); 89 nv_wr32(dev, 0x402000, 0xc0000000);
90 90
@@ -165,6 +165,12 @@ nv50_graph_channel(struct drm_device *dev)
165 uint32_t inst; 165 uint32_t inst;
166 int i; 166 int i;
167 167
168 /* Be sure we're not in the middle of a context switch or bad things
169 * will happen, such as unloading the wrong pgraph context.
170 */
171 if (!nv_wait(0x400300, 0x00000001, 0x00000000))
172 NV_ERROR(dev, "Ctxprog is still running\n");
173
168 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR); 174 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
169 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED)) 175 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
170 return NULL; 176 return NULL;
@@ -275,19 +281,18 @@ nv50_graph_load_context(struct nouveau_channel *chan)
275int 281int
276nv50_graph_unload_context(struct drm_device *dev) 282nv50_graph_unload_context(struct drm_device *dev)
277{ 283{
278 uint32_t inst, fifo = nv_rd32(dev, 0x400500); 284 uint32_t inst;
279 285
280 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR); 286 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
281 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED)) 287 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
282 return 0; 288 return 0;
283 inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE; 289 inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
284 290
285 nv_wr32(dev, 0x400500, fifo & ~1); 291 nouveau_wait_for_idle(dev);
286 nv_wr32(dev, 0x400784, inst); 292 nv_wr32(dev, 0x400784, inst);
287 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20); 293 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
288 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01); 294 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
289 nouveau_wait_for_idle(dev); 295 nouveau_wait_for_idle(dev);
290 nv_wr32(dev, 0x400500, fifo);
291 296
292 nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst); 297 nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
293 return 0; 298 return 0;
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
index 94400f777e7f..f0dc4e36ef05 100644
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
@@ -76,6 +76,11 @@ nv50_instmem_init(struct drm_device *dev)
76 for (i = 0x1700; i <= 0x1710; i += 4) 76 for (i = 0x1700; i <= 0x1710; i += 4)
77 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i); 77 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
78 78
79 if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
80 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;
81 else
82 dev_priv->vram_sys_base = 0;
83
79 /* Reserve the last MiB of VRAM, we should probably try to avoid 84 /* Reserve the last MiB of VRAM, we should probably try to avoid
80 * setting up the below tables over the top of the VBIOS image at 85 * setting up the below tables over the top of the VBIOS image at
81 * some point. 86 * some point.
@@ -172,16 +177,28 @@ nv50_instmem_init(struct drm_device *dev)
172 * We map the entire fake channel into the start of the PRAMIN BAR 177 * We map the entire fake channel into the start of the PRAMIN BAR
173 */ 178 */
174 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000, 179 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000,
175 0, &priv->pramin_pt); 180 0, &priv->pramin_pt);
176 if (ret) 181 if (ret)
177 return ret; 182 return ret;
178 183
179 for (i = 0, v = c_offset; i < pt_size; i += 8, v += 0x1000) { 184 v = c_offset | 1;
180 if (v < (c_offset + c_size)) 185 if (dev_priv->vram_sys_base) {
181 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1); 186 v += dev_priv->vram_sys_base;
182 else 187 v |= 0x30;
183 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009); 188 }
189
190 i = 0;
191 while (v < dev_priv->vram_sys_base + c_offset + c_size) {
192 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v);
193 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
194 v += 0x1000;
195 i += 8;
196 }
197
198 while (i < pt_size) {
199 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000000);
184 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000); 200 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
201 i += 8;
185 } 202 }
186 203
187 BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63); 204 BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
@@ -416,7 +433,9 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
416{ 433{
417 struct drm_nouveau_private *dev_priv = dev->dev_private; 434 struct drm_nouveau_private *dev_priv = dev->dev_private;
418 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv; 435 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
419 uint32_t pte, pte_end, vram; 436 struct nouveau_gpuobj *pramin_pt = priv->pramin_pt->gpuobj;
437 uint32_t pte, pte_end;
438 uint64_t vram;
420 439
421 if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound) 440 if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
422 return -EINVAL; 441 return -EINVAL;
@@ -424,20 +443,24 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
424 NV_DEBUG(dev, "st=0x%0llx sz=0x%0llx\n", 443 NV_DEBUG(dev, "st=0x%0llx sz=0x%0llx\n",
425 gpuobj->im_pramin->start, gpuobj->im_pramin->size); 444 gpuobj->im_pramin->start, gpuobj->im_pramin->size);
426 445
427 pte = (gpuobj->im_pramin->start >> 12) << 3; 446 pte = (gpuobj->im_pramin->start >> 12) << 1;
428 pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; 447 pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
429 vram = gpuobj->im_backing_start; 448 vram = gpuobj->im_backing_start;
430 449
431 NV_DEBUG(dev, "pramin=0x%llx, pte=%d, pte_end=%d\n", 450 NV_DEBUG(dev, "pramin=0x%llx, pte=%d, pte_end=%d\n",
432 gpuobj->im_pramin->start, pte, pte_end); 451 gpuobj->im_pramin->start, pte, pte_end);
433 NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start); 452 NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
434 453
454 vram |= 1;
455 if (dev_priv->vram_sys_base) {
456 vram += dev_priv->vram_sys_base;
457 vram |= 0x30;
458 }
459
435 dev_priv->engine.instmem.prepare_access(dev, true); 460 dev_priv->engine.instmem.prepare_access(dev, true);
436 while (pte < pte_end) { 461 while (pte < pte_end) {
437 nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1); 462 nv_wo32(dev, pramin_pt, pte++, lower_32_bits(vram));
438 nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000); 463 nv_wo32(dev, pramin_pt, pte++, upper_32_bits(vram));
439
440 pte += 8;
441 vram += NV50_INSTMEM_PAGE_SIZE; 464 vram += NV50_INSTMEM_PAGE_SIZE;
442 } 465 }
443 dev_priv->engine.instmem.finish_access(dev); 466 dev_priv->engine.instmem.finish_access(dev);
@@ -470,14 +493,13 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
470 if (gpuobj->im_bound == 0) 493 if (gpuobj->im_bound == 0)
471 return -EINVAL; 494 return -EINVAL;
472 495
473 pte = (gpuobj->im_pramin->start >> 12) << 3; 496 pte = (gpuobj->im_pramin->start >> 12) << 1;
474 pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; 497 pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
475 498
476 dev_priv->engine.instmem.prepare_access(dev, true); 499 dev_priv->engine.instmem.prepare_access(dev, true);
477 while (pte < pte_end) { 500 while (pte < pte_end) {
478 nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009); 501 nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
479 nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000); 502 nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
480 pte += 8;
481 } 503 }
482 dev_priv->engine.instmem.finish_access(dev); 504 dev_priv->engine.instmem.finish_access(dev);
483 505
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
index e395c16d30f5..c2fff543b06f 100644
--- a/drivers/gpu/drm/nouveau/nv50_sor.c
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -90,11 +90,25 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
90{ 90{
91 struct drm_device *dev = encoder->dev; 91 struct drm_device *dev = encoder->dev;
92 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 92 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
93 struct drm_encoder *enc;
93 uint32_t val; 94 uint32_t val;
94 int or = nv_encoder->or; 95 int or = nv_encoder->or;
95 96
96 NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode); 97 NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode);
97 98
99 nv_encoder->last_dpms = mode;
100 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
101 struct nouveau_encoder *nvenc = nouveau_encoder(enc);
102
103 if (nvenc == nv_encoder ||
104 nvenc->disconnect != nv50_sor_disconnect ||
105 nvenc->dcb->or != nv_encoder->dcb->or)
106 continue;
107
108 if (nvenc->last_dpms == DRM_MODE_DPMS_ON)
109 return;
110 }
111
98 /* wait for it to be done */ 112 /* wait for it to be done */
99 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_CTRL(or), 113 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_CTRL(or),
100 NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING, 0)) { 114 NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING, 0)) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 21:50:52 -0500