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path: root/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c216
1 files changed, 216 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c
new file mode 100644
index 000000000000..c5685228c322
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c
@@ -0,0 +1,216 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/bios.h>
26#include <subdev/bios/bit.h>
27#include <subdev/bios/ramcfg.h>
28#include <subdev/bios/rammap.h>
29
30u32
31nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
32 u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
33{
34 struct bit_entry bit_P;
35 u16 rammap = 0x0000;
36
37 if (!bit_entry(bios, 'P', &bit_P)) {
38 if (bit_P.version == 2)
39 rammap = nv_ro16(bios, bit_P.offset + 4);
40
41 if (rammap) {
42 *ver = nv_ro08(bios, rammap + 0);
43 switch (*ver) {
44 case 0x10:
45 case 0x11:
46 *hdr = nv_ro08(bios, rammap + 1);
47 *cnt = nv_ro08(bios, rammap + 5);
48 *len = nv_ro08(bios, rammap + 2);
49 *snr = nv_ro08(bios, rammap + 4);
50 *ssz = nv_ro08(bios, rammap + 3);
51 return rammap;
52 default:
53 break;
54 }
55 }
56 }
57
58 return 0x0000;
59}
60
61u32
62nvbios_rammapEe(struct nouveau_bios *bios, int idx,
63 u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
64{
65 u8 snr, ssz;
66 u16 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz);
67 if (rammap && idx < *cnt) {
68 rammap = rammap + *hdr + (idx * (*len + (snr * ssz)));
69 *hdr = *len;
70 *cnt = snr;
71 *len = ssz;
72 return rammap;
73 }
74 return 0x0000;
75}
76
77u32
78nvbios_rammapEp(struct nouveau_bios *bios, int idx,
79 u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
80 struct nvbios_ramcfg *p)
81{
82 u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len), temp;
83 memset(p, 0x00, sizeof(*p));
84 p->rammap_ver = *ver;
85 p->rammap_hdr = *hdr;
86 switch (!!data * *ver) {
87 case 0x10:
88 p->rammap_min = nv_ro16(bios, data + 0x00);
89 p->rammap_max = nv_ro16(bios, data + 0x02);
90 p->rammap_10_04_02 = (nv_ro08(bios, data + 0x04) & 0x02) >> 1;
91 p->rammap_10_04_08 = (nv_ro08(bios, data + 0x04) & 0x08) >> 3;
92 break;
93 case 0x11:
94 p->rammap_min = nv_ro16(bios, data + 0x00);
95 p->rammap_max = nv_ro16(bios, data + 0x02);
96 p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0;
97 p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2;
98 p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4;
99 temp = nv_ro32(bios, data + 0x09);
100 p->rammap_11_09_01ff = (temp & 0x000001ff) >> 0;
101 p->rammap_11_0a_03fe = (temp & 0x0003fe00) >> 9;
102 p->rammap_11_0a_0400 = (temp & 0x00040000) >> 18;
103 p->rammap_11_0a_0800 = (temp & 0x00080000) >> 19;
104 p->rammap_11_0b_01f0 = (temp & 0x01f00000) >> 20;
105 p->rammap_11_0b_0200 = (temp & 0x02000000) >> 25;
106 p->rammap_11_0b_0400 = (temp & 0x04000000) >> 26;
107 p->rammap_11_0b_0800 = (temp & 0x08000000) >> 27;
108 p->rammap_11_0d = nv_ro08(bios, data + 0x0d);
109 p->rammap_11_0e = nv_ro08(bios, data + 0x0e);
110 p->rammap_11_0f = nv_ro08(bios, data + 0x0f);
111 p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2;
112 break;
113 default:
114 data = 0;
115 break;
116 }
117 return data;
118}
119
120u32
121nvbios_rammapEm(struct nouveau_bios *bios, u16 mhz,
122 u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
123 struct nvbios_ramcfg *info)
124{
125 int idx = 0;
126 u32 data;
127 while ((data = nvbios_rammapEp(bios, idx++, ver, hdr, cnt, len, info))) {
128 if (mhz >= info->rammap_min && mhz <= info->rammap_max)
129 break;
130 }
131 return data;
132}
133
134u32
135nvbios_rammapSe(struct nouveau_bios *bios, u32 data,
136 u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
137 u8 *ver, u8 *hdr)
138{
139 if (idx < ecnt) {
140 data = data + ehdr + (idx * elen);
141 *ver = ever;
142 *hdr = elen;
143 return data;
144 }
145 return 0;
146}
147
148u32
149nvbios_rammapSp(struct nouveau_bios *bios, u32 data,
150 u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
151 u8 *ver, u8 *hdr, struct nvbios_ramcfg *p)
152{
153 data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr);
154 p->ramcfg_ver = *ver;
155 p->ramcfg_hdr = *hdr;
156 switch (!!data * *ver) {
157 case 0x10:
158 p->ramcfg_timing = nv_ro08(bios, data + 0x01);
159 p->ramcfg_10_02_01 = (nv_ro08(bios, data + 0x02) & 0x01) >> 0;
160 p->ramcfg_10_02_02 = (nv_ro08(bios, data + 0x02) & 0x02) >> 1;
161 p->ramcfg_10_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2;
162 p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
163 p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
164 p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5;
165 p->ramcfg_10_DLLoff = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
166 p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
167 p->ramcfg_10_04_01 = (nv_ro08(bios, data + 0x04) & 0x01) >> 0;
168 p->ramcfg_10_05 = (nv_ro08(bios, data + 0x05) & 0xff) >> 0;
169 p->ramcfg_10_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0;
170 p->ramcfg_10_07 = (nv_ro08(bios, data + 0x07) & 0xff) >> 0;
171 p->ramcfg_10_08 = (nv_ro08(bios, data + 0x08) & 0xff) >> 0;
172 p->ramcfg_10_09_0f = (nv_ro08(bios, data + 0x09) & 0x0f) >> 0;
173 p->ramcfg_10_09_f0 = (nv_ro08(bios, data + 0x09) & 0xf0) >> 4;
174 break;
175 case 0x11:
176 p->ramcfg_timing = nv_ro08(bios, data + 0x00);
177 p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0;
178 p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1;
179 p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2;
180 p->ramcfg_11_01_08 = (nv_ro08(bios, data + 0x01) & 0x08) >> 3;
181 p->ramcfg_11_01_10 = (nv_ro08(bios, data + 0x01) & 0x10) >> 4;
182 p->ramcfg_11_01_20 = (nv_ro08(bios, data + 0x01) & 0x20) >> 5;
183 p->ramcfg_11_01_40 = (nv_ro08(bios, data + 0x01) & 0x40) >> 6;
184 p->ramcfg_11_01_80 = (nv_ro08(bios, data + 0x01) & 0x80) >> 7;
185 p->ramcfg_11_02_03 = (nv_ro08(bios, data + 0x02) & 0x03) >> 0;
186 p->ramcfg_11_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2;
187 p->ramcfg_11_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
188 p->ramcfg_11_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
189 p->ramcfg_11_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
190 p->ramcfg_11_02_80 = (nv_ro08(bios, data + 0x02) & 0x80) >> 7;
191 p->ramcfg_11_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
192 p->ramcfg_11_03_30 = (nv_ro08(bios, data + 0x03) & 0x30) >> 4;
193 p->ramcfg_11_03_c0 = (nv_ro08(bios, data + 0x03) & 0xc0) >> 6;
194 p->ramcfg_11_03_f0 = (nv_ro08(bios, data + 0x03) & 0xf0) >> 4;
195 p->ramcfg_11_04 = (nv_ro08(bios, data + 0x04) & 0xff) >> 0;
196 p->ramcfg_11_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0;
197 p->ramcfg_11_07_02 = (nv_ro08(bios, data + 0x07) & 0x02) >> 1;
198 p->ramcfg_11_07_04 = (nv_ro08(bios, data + 0x07) & 0x04) >> 2;
199 p->ramcfg_11_07_08 = (nv_ro08(bios, data + 0x07) & 0x08) >> 3;
200 p->ramcfg_11_07_10 = (nv_ro08(bios, data + 0x07) & 0x10) >> 4;
201 p->ramcfg_11_07_40 = (nv_ro08(bios, data + 0x07) & 0x40) >> 6;
202 p->ramcfg_11_07_80 = (nv_ro08(bios, data + 0x07) & 0x80) >> 7;
203 p->ramcfg_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0;
204 p->ramcfg_11_08_02 = (nv_ro08(bios, data + 0x08) & 0x02) >> 1;
205 p->ramcfg_11_08_04 = (nv_ro08(bios, data + 0x08) & 0x04) >> 2;
206 p->ramcfg_11_08_08 = (nv_ro08(bios, data + 0x08) & 0x08) >> 3;
207 p->ramcfg_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4;
208 p->ramcfg_11_08_20 = (nv_ro08(bios, data + 0x08) & 0x20) >> 5;
209 p->ramcfg_11_09 = (nv_ro08(bios, data + 0x09) & 0xff) >> 0;
210 break;
211 default:
212 data = 0;
213 break;
214 }
215 return data;
216}
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-25 12:34:28 -0400