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path: root/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c2227
1 files changed, 2227 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
new file mode 100644
index 000000000000..c6579ef32cd1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
@@ -0,0 +1,2227 @@
1#include <core/engine.h>
2#include <core/device.h>
3
4#include <subdev/bios.h>
5#include <subdev/bios/bmp.h>
6#include <subdev/bios/bit.h>
7#include <subdev/bios/conn.h>
8#include <subdev/bios/dcb.h>
9#include <subdev/bios/dp.h>
10#include <subdev/bios/gpio.h>
11#include <subdev/bios/init.h>
12#include <subdev/bios/ramcfg.h>
13#include <subdev/devinit.h>
14#include <subdev/i2c.h>
15#include <subdev/vga.h>
16#include <subdev/gpio.h>
17
18#define bioslog(lvl, fmt, args...) do { \
19 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
20 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
21} while(0)
22#define cont(fmt, args...) do { \
23 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
24 printk(fmt, ##args); \
25} while(0)
26#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
27#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
28#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
29
30/******************************************************************************
31 * init parser control flow helpers
32 *****************************************************************************/
33
34static inline bool
35init_exec(struct nvbios_init *init)
36{
37 return (init->execute == 1) || ((init->execute & 5) == 5);
38}
39
40static inline void
41init_exec_set(struct nvbios_init *init, bool exec)
42{
43 if (exec) init->execute &= 0xfd;
44 else init->execute |= 0x02;
45}
46
47static inline void
48init_exec_inv(struct nvbios_init *init)
49{
50 init->execute ^= 0x02;
51}
52
53static inline void
54init_exec_force(struct nvbios_init *init, bool exec)
55{
56 if (exec) init->execute |= 0x04;
57 else init->execute &= 0xfb;
58}
59
60/******************************************************************************
61 * init parser wrappers for normal register/i2c/whatever accessors
62 *****************************************************************************/
63
64static inline int
65init_or(struct nvbios_init *init)
66{
67 if (init_exec(init)) {
68 if (init->outp)
69 return ffs(init->outp->or) - 1;
70 error("script needs OR!!\n");
71 }
72 return 0;
73}
74
75static inline int
76init_link(struct nvbios_init *init)
77{
78 if (init_exec(init)) {
79 if (init->outp)
80 return !(init->outp->sorconf.link & 1);
81 error("script needs OR link\n");
82 }
83 return 0;
84}
85
86static inline int
87init_crtc(struct nvbios_init *init)
88{
89 if (init_exec(init)) {
90 if (init->crtc >= 0)
91 return init->crtc;
92 error("script needs crtc\n");
93 }
94 return 0;
95}
96
97static u8
98init_conn(struct nvbios_init *init)
99{
100 struct nouveau_bios *bios = init->bios;
101 struct nvbios_connE connE;
102 u8 ver, hdr;
103 u32 conn;
104
105 if (init_exec(init)) {
106 if (init->outp) {
107 conn = init->outp->connector;
108 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
109 if (conn)
110 return connE.type;
111 }
112
113 error("script needs connector type\n");
114 }
115
116 return 0xff;
117}
118
119static inline u32
120init_nvreg(struct nvbios_init *init, u32 reg)
121{
122 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
123
124 /* C51 (at least) sometimes has the lower bits set which the VBIOS
125 * interprets to mean that access needs to go through certain IO
126 * ports instead. The NVIDIA binary driver has been seen to access
127 * these through the NV register address, so lets assume we can
128 * do the same
129 */
130 reg &= ~0x00000003;
131
132 /* GF8+ display scripts need register addresses mangled a bit to
133 * select a specific CRTC/OR
134 */
135 if (nv_device(init->bios)->card_type >= NV_50) {
136 if (reg & 0x80000000) {
137 reg += init_crtc(init) * 0x800;
138 reg &= ~0x80000000;
139 }
140
141 if (reg & 0x40000000) {
142 reg += init_or(init) * 0x800;
143 reg &= ~0x40000000;
144 if (reg & 0x20000000) {
145 reg += init_link(init) * 0x80;
146 reg &= ~0x20000000;
147 }
148 }
149 }
150
151 if (reg & ~0x00fffffc)
152 warn("unknown bits in register 0x%08x\n", reg);
153
154 if (devinit->mmio)
155 reg = devinit->mmio(devinit, reg);
156 return reg;
157}
158
159static u32
160init_rd32(struct nvbios_init *init, u32 reg)
161{
162 reg = init_nvreg(init, reg);
163 if (reg != ~0 && init_exec(init))
164 return nv_rd32(init->subdev, reg);
165 return 0x00000000;
166}
167
168static void
169init_wr32(struct nvbios_init *init, u32 reg, u32 val)
170{
171 reg = init_nvreg(init, reg);
172 if (reg != ~0 && init_exec(init))
173 nv_wr32(init->subdev, reg, val);
174}
175
176static u32
177init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
178{
179 reg = init_nvreg(init, reg);
180 if (reg != ~0 && init_exec(init)) {
181 u32 tmp = nv_rd32(init->subdev, reg);
182 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
183 return tmp;
184 }
185 return 0x00000000;
186}
187
188static u8
189init_rdport(struct nvbios_init *init, u16 port)
190{
191 if (init_exec(init))
192 return nv_rdport(init->subdev, init->crtc, port);
193 return 0x00;
194}
195
196static void
197init_wrport(struct nvbios_init *init, u16 port, u8 value)
198{
199 if (init_exec(init))
200 nv_wrport(init->subdev, init->crtc, port, value);
201}
202
203static u8
204init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
205{
206 struct nouveau_subdev *subdev = init->subdev;
207 if (init_exec(init)) {
208 int head = init->crtc < 0 ? 0 : init->crtc;
209 return nv_rdvgai(subdev, head, port, index);
210 }
211 return 0x00;
212}
213
214static void
215init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
216{
217 /* force head 0 for updates to cr44, it only exists on first head */
218 if (nv_device(init->subdev)->card_type < NV_50) {
219 if (port == 0x03d4 && index == 0x44)
220 init->crtc = 0;
221 }
222
223 if (init_exec(init)) {
224 int head = init->crtc < 0 ? 0 : init->crtc;
225 nv_wrvgai(init->subdev, head, port, index, value);
226 }
227
228 /* select head 1 if cr44 write selected it */
229 if (nv_device(init->subdev)->card_type < NV_50) {
230 if (port == 0x03d4 && index == 0x44 && value == 3)
231 init->crtc = 1;
232 }
233}
234
235static struct nouveau_i2c_port *
236init_i2c(struct nvbios_init *init, int index)
237{
238 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
239
240 if (index == 0xff) {
241 index = NV_I2C_DEFAULT(0);
242 if (init->outp && init->outp->i2c_upper_default)
243 index = NV_I2C_DEFAULT(1);
244 } else
245 if (index < 0) {
246 if (!init->outp) {
247 if (init_exec(init))
248 error("script needs output for i2c\n");
249 return NULL;
250 }
251
252 if (index == -2 && init->outp->location) {
253 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
254 return i2c->find_type(i2c, index);
255 }
256
257 index = init->outp->i2c_index;
258 if (init->outp->type == DCB_OUTPUT_DP)
259 index += NV_I2C_AUX(0);
260 }
261
262 return i2c->find(i2c, index);
263}
264
265static int
266init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
267{
268 struct nouveau_i2c_port *port = init_i2c(init, index);
269 if (port && init_exec(init))
270 return nv_rdi2cr(port, addr, reg);
271 return -ENODEV;
272}
273
274static int
275init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
276{
277 struct nouveau_i2c_port *port = init_i2c(init, index);
278 if (port && init_exec(init))
279 return nv_wri2cr(port, addr, reg, val);
280 return -ENODEV;
281}
282
283static u8
284init_rdauxr(struct nvbios_init *init, u32 addr)
285{
286 struct nouveau_i2c_port *port = init_i2c(init, -2);
287 u8 data;
288
289 if (port && init_exec(init)) {
290 int ret = nv_rdaux(port, addr, &data, 1);
291 if (ret == 0)
292 return data;
293 trace("auxch read failed with %d\n", ret);
294 }
295
296 return 0x00;
297}
298
299static int
300init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
301{
302 struct nouveau_i2c_port *port = init_i2c(init, -2);
303 if (port && init_exec(init)) {
304 int ret = nv_wraux(port, addr, &data, 1);
305 if (ret)
306 trace("auxch write failed with %d\n", ret);
307 return ret;
308 }
309 return -ENODEV;
310}
311
312static void
313init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
314{
315 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
316 if (devinit->pll_set && init_exec(init)) {
317 int ret = devinit->pll_set(devinit, id, freq);
318 if (ret)
319 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
320 }
321}
322
323/******************************************************************************
324 * parsing of bios structures that are required to execute init tables
325 *****************************************************************************/
326
327static u16
328init_table(struct nouveau_bios *bios, u16 *len)
329{
330 struct bit_entry bit_I;
331
332 if (!bit_entry(bios, 'I', &bit_I)) {
333 *len = bit_I.length;
334 return bit_I.offset;
335 }
336
337 if (bmp_version(bios) >= 0x0510) {
338 *len = 14;
339 return bios->bmp_offset + 75;
340 }
341
342 return 0x0000;
343}
344
345static u16
346init_table_(struct nvbios_init *init, u16 offset, const char *name)
347{
348 struct nouveau_bios *bios = init->bios;
349 u16 len, data = init_table(bios, &len);
350 if (data) {
351 if (len >= offset + 2) {
352 data = nv_ro16(bios, data + offset);
353 if (data)
354 return data;
355
356 warn("%s pointer invalid\n", name);
357 return 0x0000;
358 }
359
360 warn("init data too short for %s pointer", name);
361 return 0x0000;
362 }
363
364 warn("init data not found\n");
365 return 0x0000;
366}
367
368#define init_script_table(b) init_table_((b), 0x00, "script table")
369#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
370#define init_macro_table(b) init_table_((b), 0x04, "macro table")
371#define init_condition_table(b) init_table_((b), 0x06, "condition table")
372#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
373#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
374#define init_function_table(b) init_table_((b), 0x0c, "function table")
375#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
376
377static u16
378init_script(struct nouveau_bios *bios, int index)
379{
380 struct nvbios_init init = { .bios = bios };
381 u16 bmp_ver = bmp_version(bios), data;
382
383 if (bmp_ver && bmp_ver < 0x0510) {
384 if (index > 1 || bmp_ver < 0x0100)
385 return 0x0000;
386
387 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
388 return nv_ro16(bios, data + (index * 2));
389 }
390
391 data = init_script_table(&init);
392 if (data)
393 return nv_ro16(bios, data + (index * 2));
394
395 return 0x0000;
396}
397
398static u16
399init_unknown_script(struct nouveau_bios *bios)
400{
401 u16 len, data = init_table(bios, &len);
402 if (data && len >= 16)
403 return nv_ro16(bios, data + 14);
404 return 0x0000;
405}
406
407static u8
408init_ram_restrict_group_count(struct nvbios_init *init)
409{
410 return nvbios_ramcfg_count(init->bios);
411}
412
413static u8
414init_ram_restrict(struct nvbios_init *init)
415{
416 /* This appears to be the behaviour of the VBIOS parser, and *is*
417 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
418 * avoid fucking up the memory controller (somehow) by reading it
419 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
420 *
421 * Preserving the non-caching behaviour on earlier chipsets just
422 * in case *not* re-reading the strap causes similar breakage.
423 */
424 if (!init->ramcfg || init->bios->version.major < 0x70)
425 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
426 return (init->ramcfg & 0x7fffffff);
427}
428
429static u8
430init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
431{
432 struct nouveau_bios *bios = init->bios;
433 u16 table = init_xlat_table(init);
434 if (table) {
435 u16 data = nv_ro16(bios, table + (index * 2));
436 if (data)
437 return nv_ro08(bios, data + offset);
438 warn("xlat table pointer %d invalid\n", index);
439 }
440 return 0x00;
441}
442
443/******************************************************************************
444 * utility functions used by various init opcode handlers
445 *****************************************************************************/
446
447static bool
448init_condition_met(struct nvbios_init *init, u8 cond)
449{
450 struct nouveau_bios *bios = init->bios;
451 u16 table = init_condition_table(init);
452 if (table) {
453 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
454 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
455 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
456 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
457 cond, reg, msk, val);
458 return (init_rd32(init, reg) & msk) == val;
459 }
460 return false;
461}
462
463static bool
464init_io_condition_met(struct nvbios_init *init, u8 cond)
465{
466 struct nouveau_bios *bios = init->bios;
467 u16 table = init_io_condition_table(init);
468 if (table) {
469 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
470 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
471 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
472 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
473 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
474 cond, port, index, mask, value);
475 return (init_rdvgai(init, port, index) & mask) == value;
476 }
477 return false;
478}
479
480static bool
481init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
482{
483 struct nouveau_bios *bios = init->bios;
484 u16 table = init_io_flag_condition_table(init);
485 if (table) {
486 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
487 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
488 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
489 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
490 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
491 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
492 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
493 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
494 return (nv_ro08(bios, data + ioval) & dmask) == value;
495 }
496 return false;
497}
498
499static inline u32
500init_shift(u32 data, u8 shift)
501{
502 if (shift < 0x80)
503 return data >> shift;
504 return data << (0x100 - shift);
505}
506
507static u32
508init_tmds_reg(struct nvbios_init *init, u8 tmds)
509{
510 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
511 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
512 * CR58 for CR57 = 0 to index a table of offsets to the basic
513 * 0x6808b0 address.
514 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
515 * CR58 for CR57 = 0 to index a table of offsets to the basic
516 * 0x6808b0 address, and then flip the offset by 8.
517 */
518
519 const int pramdac_offset[13] = {
520 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
521 const u32 pramdac_table[4] = {
522 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
523
524 if (tmds >= 0x80) {
525 if (init->outp) {
526 u32 dacoffset = pramdac_offset[init->outp->or];
527 if (tmds == 0x81)
528 dacoffset ^= 8;
529 return 0x6808b0 + dacoffset;
530 }
531
532 if (init_exec(init))
533 error("tmds opcodes need dcb\n");
534 } else {
535 if (tmds < ARRAY_SIZE(pramdac_table))
536 return pramdac_table[tmds];
537
538 error("tmds selector 0x%02x unknown\n", tmds);
539 }
540
541 return 0;
542}
543
544/******************************************************************************
545 * init opcode handlers
546 *****************************************************************************/
547
548/**
549 * init_reserved - stub for various unknown/unused single-byte opcodes
550 *
551 */
552static void
553init_reserved(struct nvbios_init *init)
554{
555 u8 opcode = nv_ro08(init->bios, init->offset);
556 u8 length, i;
557
558 switch (opcode) {
559 case 0xaa:
560 length = 4;
561 break;
562 default:
563 length = 1;
564 break;
565 }
566
567 trace("RESERVED 0x%02x\t", opcode);
568 for (i = 1; i < length; i++)
569 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
570 cont("\n");
571 init->offset += length;
572}
573
574/**
575 * INIT_DONE - opcode 0x71
576 *
577 */
578static void
579init_done(struct nvbios_init *init)
580{
581 trace("DONE\n");
582 init->offset = 0x0000;
583}
584
585/**
586 * INIT_IO_RESTRICT_PROG - opcode 0x32
587 *
588 */
589static void
590init_io_restrict_prog(struct nvbios_init *init)
591{
592 struct nouveau_bios *bios = init->bios;
593 u16 port = nv_ro16(bios, init->offset + 1);
594 u8 index = nv_ro08(bios, init->offset + 3);
595 u8 mask = nv_ro08(bios, init->offset + 4);
596 u8 shift = nv_ro08(bios, init->offset + 5);
597 u8 count = nv_ro08(bios, init->offset + 6);
598 u32 reg = nv_ro32(bios, init->offset + 7);
599 u8 conf, i;
600
601 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
602 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
603 reg, port, index, mask, shift);
604 init->offset += 11;
605
606 conf = (init_rdvgai(init, port, index) & mask) >> shift;
607 for (i = 0; i < count; i++) {
608 u32 data = nv_ro32(bios, init->offset);
609
610 if (i == conf) {
611 trace("\t0x%08x *\n", data);
612 init_wr32(init, reg, data);
613 } else {
614 trace("\t0x%08x\n", data);
615 }
616
617 init->offset += 4;
618 }
619 trace("}]\n");
620}
621
622/**
623 * INIT_REPEAT - opcode 0x33
624 *
625 */
626static void
627init_repeat(struct nvbios_init *init)
628{
629 struct nouveau_bios *bios = init->bios;
630 u8 count = nv_ro08(bios, init->offset + 1);
631 u16 repeat = init->repeat;
632
633 trace("REPEAT\t0x%02x\n", count);
634 init->offset += 2;
635
636 init->repeat = init->offset;
637 init->repend = init->offset;
638 while (count--) {
639 init->offset = init->repeat;
640 nvbios_exec(init);
641 if (count)
642 trace("REPEAT\t0x%02x\n", count);
643 }
644 init->offset = init->repend;
645 init->repeat = repeat;
646}
647
648/**
649 * INIT_IO_RESTRICT_PLL - opcode 0x34
650 *
651 */
652static void
653init_io_restrict_pll(struct nvbios_init *init)
654{
655 struct nouveau_bios *bios = init->bios;
656 u16 port = nv_ro16(bios, init->offset + 1);
657 u8 index = nv_ro08(bios, init->offset + 3);
658 u8 mask = nv_ro08(bios, init->offset + 4);
659 u8 shift = nv_ro08(bios, init->offset + 5);
660 s8 iofc = nv_ro08(bios, init->offset + 6);
661 u8 count = nv_ro08(bios, init->offset + 7);
662 u32 reg = nv_ro32(bios, init->offset + 8);
663 u8 conf, i;
664
665 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
666 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
667 reg, port, index, mask, shift, iofc);
668 init->offset += 12;
669
670 conf = (init_rdvgai(init, port, index) & mask) >> shift;
671 for (i = 0; i < count; i++) {
672 u32 freq = nv_ro16(bios, init->offset) * 10;
673
674 if (i == conf) {
675 trace("\t%dkHz *\n", freq);
676 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
677 freq *= 2;
678 init_prog_pll(init, reg, freq);
679 } else {
680 trace("\t%dkHz\n", freq);
681 }
682
683 init->offset += 2;
684 }
685 trace("}]\n");
686}
687
688/**
689 * INIT_END_REPEAT - opcode 0x36
690 *
691 */
692static void
693init_end_repeat(struct nvbios_init *init)
694{
695 trace("END_REPEAT\n");
696 init->offset += 1;
697
698 if (init->repeat) {
699 init->repend = init->offset;
700 init->offset = 0;
701 }
702}
703
704/**
705 * INIT_COPY - opcode 0x37
706 *
707 */
708static void
709init_copy(struct nvbios_init *init)
710{
711 struct nouveau_bios *bios = init->bios;
712 u32 reg = nv_ro32(bios, init->offset + 1);
713 u8 shift = nv_ro08(bios, init->offset + 5);
714 u8 smask = nv_ro08(bios, init->offset + 6);
715 u16 port = nv_ro16(bios, init->offset + 7);
716 u8 index = nv_ro08(bios, init->offset + 9);
717 u8 mask = nv_ro08(bios, init->offset + 10);
718 u8 data;
719
720 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
721 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
722 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
723 (shift & 0x80) ? (0x100 - shift) : shift, smask);
724 init->offset += 11;
725
726 data = init_rdvgai(init, port, index) & mask;
727 data |= init_shift(init_rd32(init, reg), shift) & smask;
728 init_wrvgai(init, port, index, data);
729}
730
731/**
732 * INIT_NOT - opcode 0x38
733 *
734 */
735static void
736init_not(struct nvbios_init *init)
737{
738 trace("NOT\n");
739 init->offset += 1;
740 init_exec_inv(init);
741}
742
743/**
744 * INIT_IO_FLAG_CONDITION - opcode 0x39
745 *
746 */
747static void
748init_io_flag_condition(struct nvbios_init *init)
749{
750 struct nouveau_bios *bios = init->bios;
751 u8 cond = nv_ro08(bios, init->offset + 1);
752
753 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
754 init->offset += 2;
755
756 if (!init_io_flag_condition_met(init, cond))
757 init_exec_set(init, false);
758}
759
760/**
761 * INIT_DP_CONDITION - opcode 0x3a
762 *
763 */
764static void
765init_dp_condition(struct nvbios_init *init)
766{
767 struct nouveau_bios *bios = init->bios;
768 struct nvbios_dpout info;
769 u8 cond = nv_ro08(bios, init->offset + 1);
770 u8 unkn = nv_ro08(bios, init->offset + 2);
771 u8 ver, hdr, cnt, len;
772 u16 data;
773
774 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
775 init->offset += 3;
776
777 switch (cond) {
778 case 0:
779 if (init_conn(init) != DCB_CONNECTOR_eDP)
780 init_exec_set(init, false);
781 break;
782 case 1:
783 case 2:
784 if ( init->outp &&
785 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
786 (init->outp->or << 0) |
787 (init->outp->sorconf.link << 6),
788 &ver, &hdr, &cnt, &len, &info)))
789 {
790 if (!(info.flags & cond))
791 init_exec_set(init, false);
792 break;
793 }
794
795 if (init_exec(init))
796 warn("script needs dp output table data\n");
797 break;
798 case 5:
799 if (!(init_rdauxr(init, 0x0d) & 1))
800 init_exec_set(init, false);
801 break;
802 default:
803 warn("unknown dp condition 0x%02x\n", cond);
804 break;
805 }
806}
807
808/**
809 * INIT_IO_MASK_OR - opcode 0x3b
810 *
811 */
812static void
813init_io_mask_or(struct nvbios_init *init)
814{
815 struct nouveau_bios *bios = init->bios;
816 u8 index = nv_ro08(bios, init->offset + 1);
817 u8 or = init_or(init);
818 u8 data;
819
820 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
821 init->offset += 2;
822
823 data = init_rdvgai(init, 0x03d4, index);
824 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
825}
826
827/**
828 * INIT_IO_OR - opcode 0x3c
829 *
830 */
831static void
832init_io_or(struct nvbios_init *init)
833{
834 struct nouveau_bios *bios = init->bios;
835 u8 index = nv_ro08(bios, init->offset + 1);
836 u8 or = init_or(init);
837 u8 data;
838
839 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
840 init->offset += 2;
841
842 data = init_rdvgai(init, 0x03d4, index);
843 init_wrvgai(init, 0x03d4, index, data | (1 << or));
844}
845
846/**
847 * INIT_ANDN_REG - opcode 0x47
848 *
849 */
850static void
851init_andn_reg(struct nvbios_init *init)
852{
853 struct nouveau_bios *bios = init->bios;
854 u32 reg = nv_ro32(bios, init->offset + 1);
855 u32 mask = nv_ro32(bios, init->offset + 5);
856
857 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask);
858 init->offset += 9;
859
860 init_mask(init, reg, mask, 0);
861}
862
863/**
864 * INIT_OR_REG - opcode 0x48
865 *
866 */
867static void
868init_or_reg(struct nvbios_init *init)
869{
870 struct nouveau_bios *bios = init->bios;
871 u32 reg = nv_ro32(bios, init->offset + 1);
872 u32 mask = nv_ro32(bios, init->offset + 5);
873
874 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask);
875 init->offset += 9;
876
877 init_mask(init, reg, 0, mask);
878}
879
880/**
881 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
882 *
883 */
884static void
885init_idx_addr_latched(struct nvbios_init *init)
886{
887 struct nouveau_bios *bios = init->bios;
888 u32 creg = nv_ro32(bios, init->offset + 1);
889 u32 dreg = nv_ro32(bios, init->offset + 5);
890 u32 mask = nv_ro32(bios, init->offset + 9);
891 u32 data = nv_ro32(bios, init->offset + 13);
892 u8 count = nv_ro08(bios, init->offset + 17);
893
894 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
895 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
896 init->offset += 18;
897
898 while (count--) {
899 u8 iaddr = nv_ro08(bios, init->offset + 0);
900 u8 idata = nv_ro08(bios, init->offset + 1);
901
902 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
903 init->offset += 2;
904
905 init_wr32(init, dreg, idata);
906 init_mask(init, creg, ~mask, data | iaddr);
907 }
908}
909
910/**
911 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
912 *
913 */
914static void
915init_io_restrict_pll2(struct nvbios_init *init)
916{
917 struct nouveau_bios *bios = init->bios;
918 u16 port = nv_ro16(bios, init->offset + 1);
919 u8 index = nv_ro08(bios, init->offset + 3);
920 u8 mask = nv_ro08(bios, init->offset + 4);
921 u8 shift = nv_ro08(bios, init->offset + 5);
922 u8 count = nv_ro08(bios, init->offset + 6);
923 u32 reg = nv_ro32(bios, init->offset + 7);
924 u8 conf, i;
925
926 trace("IO_RESTRICT_PLL2\t"
927 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
928 reg, port, index, mask, shift);
929 init->offset += 11;
930
931 conf = (init_rdvgai(init, port, index) & mask) >> shift;
932 for (i = 0; i < count; i++) {
933 u32 freq = nv_ro32(bios, init->offset);
934 if (i == conf) {
935 trace("\t%dkHz *\n", freq);
936 init_prog_pll(init, reg, freq);
937 } else {
938 trace("\t%dkHz\n", freq);
939 }
940 init->offset += 4;
941 }
942 trace("}]\n");
943}
944
945/**
946 * INIT_PLL2 - opcode 0x4b
947 *
948 */
949static void
950init_pll2(struct nvbios_init *init)
951{
952 struct nouveau_bios *bios = init->bios;
953 u32 reg = nv_ro32(bios, init->offset + 1);
954 u32 freq = nv_ro32(bios, init->offset + 5);
955
956 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
957 init->offset += 9;
958
959 init_prog_pll(init, reg, freq);
960}
961
962/**
963 * INIT_I2C_BYTE - opcode 0x4c
964 *
965 */
966static void
967init_i2c_byte(struct nvbios_init *init)
968{
969 struct nouveau_bios *bios = init->bios;
970 u8 index = nv_ro08(bios, init->offset + 1);
971 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
972 u8 count = nv_ro08(bios, init->offset + 3);
973
974 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
975 init->offset += 4;
976
977 while (count--) {
978 u8 reg = nv_ro08(bios, init->offset + 0);
979 u8 mask = nv_ro08(bios, init->offset + 1);
980 u8 data = nv_ro08(bios, init->offset + 2);
981 int val;
982
983 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
984 init->offset += 3;
985
986 val = init_rdi2cr(init, index, addr, reg);
987 if (val < 0)
988 continue;
989 init_wri2cr(init, index, addr, reg, (val & mask) | data);
990 }
991}
992
993/**
994 * INIT_ZM_I2C_BYTE - opcode 0x4d
995 *
996 */
997static void
998init_zm_i2c_byte(struct nvbios_init *init)
999{
1000 struct nouveau_bios *bios = init->bios;
1001 u8 index = nv_ro08(bios, init->offset + 1);
1002 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1003 u8 count = nv_ro08(bios, init->offset + 3);
1004
1005 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1006 init->offset += 4;
1007
1008 while (count--) {
1009 u8 reg = nv_ro08(bios, init->offset + 0);
1010 u8 data = nv_ro08(bios, init->offset + 1);
1011
1012 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1013 init->offset += 2;
1014
1015 init_wri2cr(init, index, addr, reg, data);
1016 }
1017
1018}
1019
1020/**
1021 * INIT_ZM_I2C - opcode 0x4e
1022 *
1023 */
1024static void
1025init_zm_i2c(struct nvbios_init *init)
1026{
1027 struct nouveau_bios *bios = init->bios;
1028 u8 index = nv_ro08(bios, init->offset + 1);
1029 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1030 u8 count = nv_ro08(bios, init->offset + 3);
1031 u8 data[256], i;
1032
1033 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1034 init->offset += 4;
1035
1036 for (i = 0; i < count; i++) {
1037 data[i] = nv_ro08(bios, init->offset);
1038 trace("\t0x%02x\n", data[i]);
1039 init->offset++;
1040 }
1041
1042 if (init_exec(init)) {
1043 struct nouveau_i2c_port *port = init_i2c(init, index);
1044 struct i2c_msg msg = {
1045 .addr = addr, .flags = 0, .len = count, .buf = data,
1046 };
1047 int ret;
1048
1049 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1050 warn("i2c wr failed, %d\n", ret);
1051 }
1052}
1053
1054/**
1055 * INIT_TMDS - opcode 0x4f
1056 *
1057 */
1058static void
1059init_tmds(struct nvbios_init *init)
1060{
1061 struct nouveau_bios *bios = init->bios;
1062 u8 tmds = nv_ro08(bios, init->offset + 1);
1063 u8 addr = nv_ro08(bios, init->offset + 2);
1064 u8 mask = nv_ro08(bios, init->offset + 3);
1065 u8 data = nv_ro08(bios, init->offset + 4);
1066 u32 reg = init_tmds_reg(init, tmds);
1067
1068 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1069 tmds, addr, mask, data);
1070 init->offset += 5;
1071
1072 if (reg == 0)
1073 return;
1074
1075 init_wr32(init, reg + 0, addr | 0x00010000);
1076 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1077 init_wr32(init, reg + 0, addr);
1078}
1079
1080/**
1081 * INIT_ZM_TMDS_GROUP - opcode 0x50
1082 *
1083 */
1084static void
1085init_zm_tmds_group(struct nvbios_init *init)
1086{
1087 struct nouveau_bios *bios = init->bios;
1088 u8 tmds = nv_ro08(bios, init->offset + 1);
1089 u8 count = nv_ro08(bios, init->offset + 2);
1090 u32 reg = init_tmds_reg(init, tmds);
1091
1092 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1093 init->offset += 3;
1094
1095 while (count--) {
1096 u8 addr = nv_ro08(bios, init->offset + 0);
1097 u8 data = nv_ro08(bios, init->offset + 1);
1098
1099 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1100 init->offset += 2;
1101
1102 init_wr32(init, reg + 4, data);
1103 init_wr32(init, reg + 0, addr);
1104 }
1105}
1106
1107/**
1108 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1109 *
1110 */
1111static void
1112init_cr_idx_adr_latch(struct nvbios_init *init)
1113{
1114 struct nouveau_bios *bios = init->bios;
1115 u8 addr0 = nv_ro08(bios, init->offset + 1);
1116 u8 addr1 = nv_ro08(bios, init->offset + 2);
1117 u8 base = nv_ro08(bios, init->offset + 3);
1118 u8 count = nv_ro08(bios, init->offset + 4);
1119 u8 save0;
1120
1121 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1122 init->offset += 5;
1123
1124 save0 = init_rdvgai(init, 0x03d4, addr0);
1125 while (count--) {
1126 u8 data = nv_ro08(bios, init->offset);
1127
1128 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1129 init->offset += 1;
1130
1131 init_wrvgai(init, 0x03d4, addr0, base++);
1132 init_wrvgai(init, 0x03d4, addr1, data);
1133 }
1134 init_wrvgai(init, 0x03d4, addr0, save0);
1135}
1136
1137/**
1138 * INIT_CR - opcode 0x52
1139 *
1140 */
1141static void
1142init_cr(struct nvbios_init *init)
1143{
1144 struct nouveau_bios *bios = init->bios;
1145 u8 addr = nv_ro08(bios, init->offset + 1);
1146 u8 mask = nv_ro08(bios, init->offset + 2);
1147 u8 data = nv_ro08(bios, init->offset + 3);
1148 u8 val;
1149
1150 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1151 init->offset += 4;
1152
1153 val = init_rdvgai(init, 0x03d4, addr) & mask;
1154 init_wrvgai(init, 0x03d4, addr, val | data);
1155}
1156
1157/**
1158 * INIT_ZM_CR - opcode 0x53
1159 *
1160 */
1161static void
1162init_zm_cr(struct nvbios_init *init)
1163{
1164 struct nouveau_bios *bios = init->bios;
1165 u8 addr = nv_ro08(bios, init->offset + 1);
1166 u8 data = nv_ro08(bios, init->offset + 2);
1167
1168 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1169 init->offset += 3;
1170
1171 init_wrvgai(init, 0x03d4, addr, data);
1172}
1173
1174/**
1175 * INIT_ZM_CR_GROUP - opcode 0x54
1176 *
1177 */
1178static void
1179init_zm_cr_group(struct nvbios_init *init)
1180{
1181 struct nouveau_bios *bios = init->bios;
1182 u8 count = nv_ro08(bios, init->offset + 1);
1183
1184 trace("ZM_CR_GROUP\n");
1185 init->offset += 2;
1186
1187 while (count--) {
1188 u8 addr = nv_ro08(bios, init->offset + 0);
1189 u8 data = nv_ro08(bios, init->offset + 1);
1190
1191 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1192 init->offset += 2;
1193
1194 init_wrvgai(init, 0x03d4, addr, data);
1195 }
1196}
1197
1198/**
1199 * INIT_CONDITION_TIME - opcode 0x56
1200 *
1201 */
1202static void
1203init_condition_time(struct nvbios_init *init)
1204{
1205 struct nouveau_bios *bios = init->bios;
1206 u8 cond = nv_ro08(bios, init->offset + 1);
1207 u8 retry = nv_ro08(bios, init->offset + 2);
1208 u8 wait = min((u16)retry * 50, 100);
1209
1210 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1211 init->offset += 3;
1212
1213 if (!init_exec(init))
1214 return;
1215
1216 while (wait--) {
1217 if (init_condition_met(init, cond))
1218 return;
1219 mdelay(20);
1220 }
1221
1222 init_exec_set(init, false);
1223}
1224
1225/**
1226 * INIT_LTIME - opcode 0x57
1227 *
1228 */
1229static void
1230init_ltime(struct nvbios_init *init)
1231{
1232 struct nouveau_bios *bios = init->bios;
1233 u16 msec = nv_ro16(bios, init->offset + 1);
1234
1235 trace("LTIME\t0x%04x\n", msec);
1236 init->offset += 3;
1237
1238 if (init_exec(init))
1239 mdelay(msec);
1240}
1241
1242/**
1243 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1244 *
1245 */
1246static void
1247init_zm_reg_sequence(struct nvbios_init *init)
1248{
1249 struct nouveau_bios *bios = init->bios;
1250 u32 base = nv_ro32(bios, init->offset + 1);
1251 u8 count = nv_ro08(bios, init->offset + 5);
1252
1253 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1254 init->offset += 6;
1255
1256 while (count--) {
1257 u32 data = nv_ro32(bios, init->offset);
1258
1259 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1260 init->offset += 4;
1261
1262 init_wr32(init, base, data);
1263 base += 4;
1264 }
1265}
1266
1267/**
1268 * INIT_SUB_DIRECT - opcode 0x5b
1269 *
1270 */
1271static void
1272init_sub_direct(struct nvbios_init *init)
1273{
1274 struct nouveau_bios *bios = init->bios;
1275 u16 addr = nv_ro16(bios, init->offset + 1);
1276 u16 save;
1277
1278 trace("SUB_DIRECT\t0x%04x\n", addr);
1279
1280 if (init_exec(init)) {
1281 save = init->offset;
1282 init->offset = addr;
1283 if (nvbios_exec(init)) {
1284 error("error parsing sub-table\n");
1285 return;
1286 }
1287 init->offset = save;
1288 }
1289
1290 init->offset += 3;
1291}
1292
1293/**
1294 * INIT_JUMP - opcode 0x5c
1295 *
1296 */
1297static void
1298init_jump(struct nvbios_init *init)
1299{
1300 struct nouveau_bios *bios = init->bios;
1301 u16 offset = nv_ro16(bios, init->offset + 1);
1302
1303 trace("JUMP\t0x%04x\n", offset);
1304
1305 if (init_exec(init))
1306 init->offset = offset;
1307 else
1308 init->offset += 3;
1309}
1310
1311/**
1312 * INIT_I2C_IF - opcode 0x5e
1313 *
1314 */
1315static void
1316init_i2c_if(struct nvbios_init *init)
1317{
1318 struct nouveau_bios *bios = init->bios;
1319 u8 index = nv_ro08(bios, init->offset + 1);
1320 u8 addr = nv_ro08(bios, init->offset + 2);
1321 u8 reg = nv_ro08(bios, init->offset + 3);
1322 u8 mask = nv_ro08(bios, init->offset + 4);
1323 u8 data = nv_ro08(bios, init->offset + 5);
1324 u8 value;
1325
1326 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1327 index, addr, reg, mask, data);
1328 init->offset += 6;
1329 init_exec_force(init, true);
1330
1331 value = init_rdi2cr(init, index, addr, reg);
1332 if ((value & mask) != data)
1333 init_exec_set(init, false);
1334
1335 init_exec_force(init, false);
1336}
1337
1338/**
1339 * INIT_COPY_NV_REG - opcode 0x5f
1340 *
1341 */
1342static void
1343init_copy_nv_reg(struct nvbios_init *init)
1344{
1345 struct nouveau_bios *bios = init->bios;
1346 u32 sreg = nv_ro32(bios, init->offset + 1);
1347 u8 shift = nv_ro08(bios, init->offset + 5);
1348 u32 smask = nv_ro32(bios, init->offset + 6);
1349 u32 sxor = nv_ro32(bios, init->offset + 10);
1350 u32 dreg = nv_ro32(bios, init->offset + 14);
1351 u32 dmask = nv_ro32(bios, init->offset + 18);
1352 u32 data;
1353
1354 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1355 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1356 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1357 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1358 init->offset += 22;
1359
1360 data = init_shift(init_rd32(init, sreg), shift);
1361 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1362}
1363
1364/**
1365 * INIT_ZM_INDEX_IO - opcode 0x62
1366 *
1367 */
1368static void
1369init_zm_index_io(struct nvbios_init *init)
1370{
1371 struct nouveau_bios *bios = init->bios;
1372 u16 port = nv_ro16(bios, init->offset + 1);
1373 u8 index = nv_ro08(bios, init->offset + 3);
1374 u8 data = nv_ro08(bios, init->offset + 4);
1375
1376 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1377 init->offset += 5;
1378
1379 init_wrvgai(init, port, index, data);
1380}
1381
1382/**
1383 * INIT_COMPUTE_MEM - opcode 0x63
1384 *
1385 */
1386static void
1387init_compute_mem(struct nvbios_init *init)
1388{
1389 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1390
1391 trace("COMPUTE_MEM\n");
1392 init->offset += 1;
1393
1394 init_exec_force(init, true);
1395 if (init_exec(init) && devinit->meminit)
1396 devinit->meminit(devinit);
1397 init_exec_force(init, false);
1398}
1399
1400/**
1401 * INIT_RESET - opcode 0x65
1402 *
1403 */
1404static void
1405init_reset(struct nvbios_init *init)
1406{
1407 struct nouveau_bios *bios = init->bios;
1408 u32 reg = nv_ro32(bios, init->offset + 1);
1409 u32 data1 = nv_ro32(bios, init->offset + 5);
1410 u32 data2 = nv_ro32(bios, init->offset + 9);
1411 u32 savepci19;
1412
1413 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1414 init->offset += 13;
1415 init_exec_force(init, true);
1416
1417 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1418 init_wr32(init, reg, data1);
1419 udelay(10);
1420 init_wr32(init, reg, data2);
1421 init_wr32(init, 0x00184c, savepci19);
1422 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1423
1424 init_exec_force(init, false);
1425}
1426
1427/**
1428 * INIT_CONFIGURE_MEM - opcode 0x66
1429 *
1430 */
1431static u16
1432init_configure_mem_clk(struct nvbios_init *init)
1433{
1434 u16 mdata = bmp_mem_init_table(init->bios);
1435 if (mdata)
1436 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1437 return mdata;
1438}
1439
1440static void
1441init_configure_mem(struct nvbios_init *init)
1442{
1443 struct nouveau_bios *bios = init->bios;
1444 u16 mdata, sdata;
1445 u32 addr, data;
1446
1447 trace("CONFIGURE_MEM\n");
1448 init->offset += 1;
1449
1450 if (bios->version.major > 2) {
1451 init_done(init);
1452 return;
1453 }
1454 init_exec_force(init, true);
1455
1456 mdata = init_configure_mem_clk(init);
1457 sdata = bmp_sdr_seq_table(bios);
1458 if (nv_ro08(bios, mdata) & 0x01)
1459 sdata = bmp_ddr_seq_table(bios);
1460 mdata += 6; /* skip to data */
1461
1462 data = init_rdvgai(init, 0x03c4, 0x01);
1463 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1464
1465 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
1466 switch (addr) {
1467 case 0x10021c: /* CKE_NORMAL */
1468 case 0x1002d0: /* CMD_REFRESH */
1469 case 0x1002d4: /* CMD_PRECHARGE */
1470 data = 0x00000001;
1471 break;
1472 default:
1473 data = nv_ro32(bios, mdata);
1474 mdata += 4;
1475 if (data == 0xffffffff)
1476 continue;
1477 break;
1478 }
1479
1480 init_wr32(init, addr, data);
1481 }
1482
1483 init_exec_force(init, false);
1484}
1485
1486/**
1487 * INIT_CONFIGURE_CLK - opcode 0x67
1488 *
1489 */
1490static void
1491init_configure_clk(struct nvbios_init *init)
1492{
1493 struct nouveau_bios *bios = init->bios;
1494 u16 mdata, clock;
1495
1496 trace("CONFIGURE_CLK\n");
1497 init->offset += 1;
1498
1499 if (bios->version.major > 2) {
1500 init_done(init);
1501 return;
1502 }
1503 init_exec_force(init, true);
1504
1505 mdata = init_configure_mem_clk(init);
1506
1507 /* NVPLL */
1508 clock = nv_ro16(bios, mdata + 4) * 10;
1509 init_prog_pll(init, 0x680500, clock);
1510
1511 /* MPLL */
1512 clock = nv_ro16(bios, mdata + 2) * 10;
1513 if (nv_ro08(bios, mdata) & 0x01)
1514 clock *= 2;
1515 init_prog_pll(init, 0x680504, clock);
1516
1517 init_exec_force(init, false);
1518}
1519
1520/**
1521 * INIT_CONFIGURE_PREINIT - opcode 0x68
1522 *
1523 */
1524static void
1525init_configure_preinit(struct nvbios_init *init)
1526{
1527 struct nouveau_bios *bios = init->bios;
1528 u32 strap;
1529
1530 trace("CONFIGURE_PREINIT\n");
1531 init->offset += 1;
1532
1533 if (bios->version.major > 2) {
1534 init_done(init);
1535 return;
1536 }
1537 init_exec_force(init, true);
1538
1539 strap = init_rd32(init, 0x101000);
1540 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1541 init_wrvgai(init, 0x03d4, 0x3c, strap);
1542
1543 init_exec_force(init, false);
1544}
1545
1546/**
1547 * INIT_IO - opcode 0x69
1548 *
1549 */
1550static void
1551init_io(struct nvbios_init *init)
1552{
1553 struct nouveau_bios *bios = init->bios;
1554 u16 port = nv_ro16(bios, init->offset + 1);
1555 u8 mask = nv_ro16(bios, init->offset + 3);
1556 u8 data = nv_ro16(bios, init->offset + 4);
1557 u8 value;
1558
1559 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1560 init->offset += 5;
1561
1562 /* ummm.. yes.. should really figure out wtf this is and why it's
1563 * needed some day.. it's almost certainly wrong, but, it also
1564 * somehow makes things work...
1565 */
1566 if (nv_device(init->bios)->card_type >= NV_50 &&
1567 port == 0x03c3 && data == 0x01) {
1568 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1569 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1570 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1571 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1572 mdelay(10);
1573 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1574 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1575 init_wr32(init, 0x614100, 0x00800018);
1576 init_wr32(init, 0x614900, 0x00800018);
1577 mdelay(10);
1578 init_wr32(init, 0x614100, 0x10000018);
1579 init_wr32(init, 0x614900, 0x10000018);
1580 }
1581
1582 value = init_rdport(init, port) & mask;
1583 init_wrport(init, port, data | value);
1584}
1585
1586/**
1587 * INIT_SUB - opcode 0x6b
1588 *
1589 */
1590static void
1591init_sub(struct nvbios_init *init)
1592{
1593 struct nouveau_bios *bios = init->bios;
1594 u8 index = nv_ro08(bios, init->offset + 1);
1595 u16 addr, save;
1596
1597 trace("SUB\t0x%02x\n", index);
1598
1599 addr = init_script(bios, index);
1600 if (addr && init_exec(init)) {
1601 save = init->offset;
1602 init->offset = addr;
1603 if (nvbios_exec(init)) {
1604 error("error parsing sub-table\n");
1605 return;
1606 }
1607 init->offset = save;
1608 }
1609
1610 init->offset += 2;
1611}
1612
1613/**
1614 * INIT_RAM_CONDITION - opcode 0x6d
1615 *
1616 */
1617static void
1618init_ram_condition(struct nvbios_init *init)
1619{
1620 struct nouveau_bios *bios = init->bios;
1621 u8 mask = nv_ro08(bios, init->offset + 1);
1622 u8 value = nv_ro08(bios, init->offset + 2);
1623
1624 trace("RAM_CONDITION\t"
1625 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1626 init->offset += 3;
1627
1628 if ((init_rd32(init, 0x100000) & mask) != value)
1629 init_exec_set(init, false);
1630}
1631
1632/**
1633 * INIT_NV_REG - opcode 0x6e
1634 *
1635 */
1636static void
1637init_nv_reg(struct nvbios_init *init)
1638{
1639 struct nouveau_bios *bios = init->bios;
1640 u32 reg = nv_ro32(bios, init->offset + 1);
1641 u32 mask = nv_ro32(bios, init->offset + 5);
1642 u32 data = nv_ro32(bios, init->offset + 9);
1643
1644 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1645 init->offset += 13;
1646
1647 init_mask(init, reg, ~mask, data);
1648}
1649
1650/**
1651 * INIT_MACRO - opcode 0x6f
1652 *
1653 */
1654static void
1655init_macro(struct nvbios_init *init)
1656{
1657 struct nouveau_bios *bios = init->bios;
1658 u8 macro = nv_ro08(bios, init->offset + 1);
1659 u16 table;
1660
1661 trace("MACRO\t0x%02x\n", macro);
1662
1663 table = init_macro_table(init);
1664 if (table) {
1665 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1666 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1667 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1668 init_wr32(init, addr, data);
1669 }
1670
1671 init->offset += 2;
1672}
1673
1674/**
1675 * INIT_RESUME - opcode 0x72
1676 *
1677 */
1678static void
1679init_resume(struct nvbios_init *init)
1680{
1681 trace("RESUME\n");
1682 init->offset += 1;
1683 init_exec_set(init, true);
1684}
1685
1686/**
1687 * INIT_TIME - opcode 0x74
1688 *
1689 */
1690static void
1691init_time(struct nvbios_init *init)
1692{
1693 struct nouveau_bios *bios = init->bios;
1694 u16 usec = nv_ro16(bios, init->offset + 1);
1695
1696 trace("TIME\t0x%04x\n", usec);
1697 init->offset += 3;
1698
1699 if (init_exec(init)) {
1700 if (usec < 1000)
1701 udelay(usec);
1702 else
1703 mdelay((usec + 900) / 1000);
1704 }
1705}
1706
1707/**
1708 * INIT_CONDITION - opcode 0x75
1709 *
1710 */
1711static void
1712init_condition(struct nvbios_init *init)
1713{
1714 struct nouveau_bios *bios = init->bios;
1715 u8 cond = nv_ro08(bios, init->offset + 1);
1716
1717 trace("CONDITION\t0x%02x\n", cond);
1718 init->offset += 2;
1719
1720 if (!init_condition_met(init, cond))
1721 init_exec_set(init, false);
1722}
1723
1724/**
1725 * INIT_IO_CONDITION - opcode 0x76
1726 *
1727 */
1728static void
1729init_io_condition(struct nvbios_init *init)
1730{
1731 struct nouveau_bios *bios = init->bios;
1732 u8 cond = nv_ro08(bios, init->offset + 1);
1733
1734 trace("IO_CONDITION\t0x%02x\n", cond);
1735 init->offset += 2;
1736
1737 if (!init_io_condition_met(init, cond))
1738 init_exec_set(init, false);
1739}
1740
1741/**
1742 * INIT_INDEX_IO - opcode 0x78
1743 *
1744 */
1745static void
1746init_index_io(struct nvbios_init *init)
1747{
1748 struct nouveau_bios *bios = init->bios;
1749 u16 port = nv_ro16(bios, init->offset + 1);
1750 u8 index = nv_ro16(bios, init->offset + 3);
1751 u8 mask = nv_ro08(bios, init->offset + 4);
1752 u8 data = nv_ro08(bios, init->offset + 5);
1753 u8 value;
1754
1755 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1756 port, index, mask, data);
1757 init->offset += 6;
1758
1759 value = init_rdvgai(init, port, index) & mask;
1760 init_wrvgai(init, port, index, data | value);
1761}
1762
1763/**
1764 * INIT_PLL - opcode 0x79
1765 *
1766 */
1767static void
1768init_pll(struct nvbios_init *init)
1769{
1770 struct nouveau_bios *bios = init->bios;
1771 u32 reg = nv_ro32(bios, init->offset + 1);
1772 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1773
1774 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1775 init->offset += 7;
1776
1777 init_prog_pll(init, reg, freq);
1778}
1779
1780/**
1781 * INIT_ZM_REG - opcode 0x7a
1782 *
1783 */
1784static void
1785init_zm_reg(struct nvbios_init *init)
1786{
1787 struct nouveau_bios *bios = init->bios;
1788 u32 addr = nv_ro32(bios, init->offset + 1);
1789 u32 data = nv_ro32(bios, init->offset + 5);
1790
1791 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1792 init->offset += 9;
1793
1794 if (addr == 0x000200)
1795 data |= 0x00000001;
1796
1797 init_wr32(init, addr, data);
1798}
1799
1800/**
1801 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1802 *
1803 */
1804static void
1805init_ram_restrict_pll(struct nvbios_init *init)
1806{
1807 struct nouveau_bios *bios = init->bios;
1808 u8 type = nv_ro08(bios, init->offset + 1);
1809 u8 count = init_ram_restrict_group_count(init);
1810 u8 strap = init_ram_restrict(init);
1811 u8 cconf;
1812
1813 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1814 init->offset += 2;
1815
1816 for (cconf = 0; cconf < count; cconf++) {
1817 u32 freq = nv_ro32(bios, init->offset);
1818
1819 if (cconf == strap) {
1820 trace("%dkHz *\n", freq);
1821 init_prog_pll(init, type, freq);
1822 } else {
1823 trace("%dkHz\n", freq);
1824 }
1825
1826 init->offset += 4;
1827 }
1828}
1829
1830/**
1831 * INIT_GPIO - opcode 0x8e
1832 *
1833 */
1834static void
1835init_gpio(struct nvbios_init *init)
1836{
1837 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1838
1839 trace("GPIO\n");
1840 init->offset += 1;
1841
1842 if (init_exec(init) && gpio && gpio->reset)
1843 gpio->reset(gpio, DCB_GPIO_UNUSED);
1844}
1845
1846/**
1847 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1848 *
1849 */
1850static void
1851init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1852{
1853 struct nouveau_bios *bios = init->bios;
1854 u32 addr = nv_ro32(bios, init->offset + 1);
1855 u8 incr = nv_ro08(bios, init->offset + 5);
1856 u8 num = nv_ro08(bios, init->offset + 6);
1857 u8 count = init_ram_restrict_group_count(init);
1858 u8 index = init_ram_restrict(init);
1859 u8 i, j;
1860
1861 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1862 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1863 init->offset += 7;
1864
1865 for (i = 0; i < num; i++) {
1866 trace("\tR[0x%06x] = {\n", addr);
1867 for (j = 0; j < count; j++) {
1868 u32 data = nv_ro32(bios, init->offset);
1869
1870 if (j == index) {
1871 trace("\t\t0x%08x *\n", data);
1872 init_wr32(init, addr, data);
1873 } else {
1874 trace("\t\t0x%08x\n", data);
1875 }
1876
1877 init->offset += 4;
1878 }
1879 trace("\t}\n");
1880 addr += incr;
1881 }
1882}
1883
1884/**
1885 * INIT_COPY_ZM_REG - opcode 0x90
1886 *
1887 */
1888static void
1889init_copy_zm_reg(struct nvbios_init *init)
1890{
1891 struct nouveau_bios *bios = init->bios;
1892 u32 sreg = nv_ro32(bios, init->offset + 1);
1893 u32 dreg = nv_ro32(bios, init->offset + 5);
1894
1895 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1896 init->offset += 9;
1897
1898 init_wr32(init, dreg, init_rd32(init, sreg));
1899}
1900
1901/**
1902 * INIT_ZM_REG_GROUP - opcode 0x91
1903 *
1904 */
1905static void
1906init_zm_reg_group(struct nvbios_init *init)
1907{
1908 struct nouveau_bios *bios = init->bios;
1909 u32 addr = nv_ro32(bios, init->offset + 1);
1910 u8 count = nv_ro08(bios, init->offset + 5);
1911
1912 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
1913 init->offset += 6;
1914
1915 while (count--) {
1916 u32 data = nv_ro32(bios, init->offset);
1917 trace("\t0x%08x\n", data);
1918 init_wr32(init, addr, data);
1919 init->offset += 4;
1920 }
1921}
1922
1923/**
1924 * INIT_XLAT - opcode 0x96
1925 *
1926 */
1927static void
1928init_xlat(struct nvbios_init *init)
1929{
1930 struct nouveau_bios *bios = init->bios;
1931 u32 saddr = nv_ro32(bios, init->offset + 1);
1932 u8 sshift = nv_ro08(bios, init->offset + 5);
1933 u8 smask = nv_ro08(bios, init->offset + 6);
1934 u8 index = nv_ro08(bios, init->offset + 7);
1935 u32 daddr = nv_ro32(bios, init->offset + 8);
1936 u32 dmask = nv_ro32(bios, init->offset + 12);
1937 u8 shift = nv_ro08(bios, init->offset + 16);
1938 u32 data;
1939
1940 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1941 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1942 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1943 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1944 init->offset += 17;
1945
1946 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1947 data = init_xlat_(init, index, data) << shift;
1948 init_mask(init, daddr, ~dmask, data);
1949}
1950
1951/**
1952 * INIT_ZM_MASK_ADD - opcode 0x97
1953 *
1954 */
1955static void
1956init_zm_mask_add(struct nvbios_init *init)
1957{
1958 struct nouveau_bios *bios = init->bios;
1959 u32 addr = nv_ro32(bios, init->offset + 1);
1960 u32 mask = nv_ro32(bios, init->offset + 5);
1961 u32 add = nv_ro32(bios, init->offset + 9);
1962 u32 data;
1963
1964 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1965 init->offset += 13;
1966
1967 data = init_rd32(init, addr);
1968 data = (data & mask) | ((data + add) & ~mask);
1969 init_wr32(init, addr, data);
1970}
1971
1972/**
1973 * INIT_AUXCH - opcode 0x98
1974 *
1975 */
1976static void
1977init_auxch(struct nvbios_init *init)
1978{
1979 struct nouveau_bios *bios = init->bios;
1980 u32 addr = nv_ro32(bios, init->offset + 1);
1981 u8 count = nv_ro08(bios, init->offset + 5);
1982
1983 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1984 init->offset += 6;
1985
1986 while (count--) {
1987 u8 mask = nv_ro08(bios, init->offset + 0);
1988 u8 data = nv_ro08(bios, init->offset + 1);
1989 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1990 mask = init_rdauxr(init, addr) & mask;
1991 init_wrauxr(init, addr, mask | data);
1992 init->offset += 2;
1993 }
1994}
1995
1996/**
1997 * INIT_AUXCH - opcode 0x99
1998 *
1999 */
2000static void
2001init_zm_auxch(struct nvbios_init *init)
2002{
2003 struct nouveau_bios *bios = init->bios;
2004 u32 addr = nv_ro32(bios, init->offset + 1);
2005 u8 count = nv_ro08(bios, init->offset + 5);
2006
2007 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2008 init->offset += 6;
2009
2010 while (count--) {
2011 u8 data = nv_ro08(bios, init->offset + 0);
2012 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2013 init_wrauxr(init, addr, data);
2014 init->offset += 1;
2015 }
2016}
2017
2018/**
2019 * INIT_I2C_LONG_IF - opcode 0x9a
2020 *
2021 */
2022static void
2023init_i2c_long_if(struct nvbios_init *init)
2024{
2025 struct nouveau_bios *bios = init->bios;
2026 u8 index = nv_ro08(bios, init->offset + 1);
2027 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
2028 u8 reglo = nv_ro08(bios, init->offset + 3);
2029 u8 reghi = nv_ro08(bios, init->offset + 4);
2030 u8 mask = nv_ro08(bios, init->offset + 5);
2031 u8 data = nv_ro08(bios, init->offset + 6);
2032 struct nouveau_i2c_port *port;
2033
2034 trace("I2C_LONG_IF\t"
2035 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2036 index, addr, reglo, reghi, mask, data);
2037 init->offset += 7;
2038
2039 port = init_i2c(init, index);
2040 if (port) {
2041 u8 i[2] = { reghi, reglo };
2042 u8 o[1] = {};
2043 struct i2c_msg msg[] = {
2044 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2045 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2046 };
2047 int ret;
2048
2049 ret = i2c_transfer(&port->adapter, msg, 2);
2050 if (ret == 2 && ((o[0] & mask) == data))
2051 return;
2052 }
2053
2054 init_exec_set(init, false);
2055}
2056
2057/**
2058 * INIT_GPIO_NE - opcode 0xa9
2059 *
2060 */
2061static void
2062init_gpio_ne(struct nvbios_init *init)
2063{
2064 struct nouveau_bios *bios = init->bios;
2065 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2066 struct dcb_gpio_func func;
2067 u8 count = nv_ro08(bios, init->offset + 1);
2068 u8 idx = 0, ver, len;
2069 u16 data, i;
2070
2071 trace("GPIO_NE\t");
2072 init->offset += 2;
2073
2074 for (i = init->offset; i < init->offset + count; i++)
2075 cont("0x%02x ", nv_ro08(bios, i));
2076 cont("\n");
2077
2078 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2079 if (func.func != DCB_GPIO_UNUSED) {
2080 for (i = init->offset; i < init->offset + count; i++) {
2081 if (func.func == nv_ro08(bios, i))
2082 break;
2083 }
2084
2085 trace("\tFUNC[0x%02x]", func.func);
2086 if (i == (init->offset + count)) {
2087 cont(" *");
2088 if (init_exec(init) && gpio && gpio->reset)
2089 gpio->reset(gpio, func.func);
2090 }
2091 cont("\n");
2092 }
2093 }
2094
2095 init->offset += count;
2096}
2097
2098static struct nvbios_init_opcode {
2099 void (*exec)(struct nvbios_init *);
2100} init_opcode[] = {
2101 [0x32] = { init_io_restrict_prog },
2102 [0x33] = { init_repeat },
2103 [0x34] = { init_io_restrict_pll },
2104 [0x36] = { init_end_repeat },
2105 [0x37] = { init_copy },
2106 [0x38] = { init_not },
2107 [0x39] = { init_io_flag_condition },
2108 [0x3a] = { init_dp_condition },
2109 [0x3b] = { init_io_mask_or },
2110 [0x3c] = { init_io_or },
2111 [0x47] = { init_andn_reg },
2112 [0x48] = { init_or_reg },
2113 [0x49] = { init_idx_addr_latched },
2114 [0x4a] = { init_io_restrict_pll2 },
2115 [0x4b] = { init_pll2 },
2116 [0x4c] = { init_i2c_byte },
2117 [0x4d] = { init_zm_i2c_byte },
2118 [0x4e] = { init_zm_i2c },
2119 [0x4f] = { init_tmds },
2120 [0x50] = { init_zm_tmds_group },
2121 [0x51] = { init_cr_idx_adr_latch },
2122 [0x52] = { init_cr },
2123 [0x53] = { init_zm_cr },
2124 [0x54] = { init_zm_cr_group },
2125 [0x56] = { init_condition_time },
2126 [0x57] = { init_ltime },
2127 [0x58] = { init_zm_reg_sequence },
2128 [0x5b] = { init_sub_direct },
2129 [0x5c] = { init_jump },
2130 [0x5e] = { init_i2c_if },
2131 [0x5f] = { init_copy_nv_reg },
2132 [0x62] = { init_zm_index_io },
2133 [0x63] = { init_compute_mem },
2134 [0x65] = { init_reset },
2135 [0x66] = { init_configure_mem },
2136 [0x67] = { init_configure_clk },
2137 [0x68] = { init_configure_preinit },
2138 [0x69] = { init_io },
2139 [0x6b] = { init_sub },
2140 [0x6d] = { init_ram_condition },
2141 [0x6e] = { init_nv_reg },
2142 [0x6f] = { init_macro },
2143 [0x71] = { init_done },
2144 [0x72] = { init_resume },
2145 [0x74] = { init_time },
2146 [0x75] = { init_condition },
2147 [0x76] = { init_io_condition },
2148 [0x78] = { init_index_io },
2149 [0x79] = { init_pll },
2150 [0x7a] = { init_zm_reg },
2151 [0x87] = { init_ram_restrict_pll },
2152 [0x8c] = { init_reserved },
2153 [0x8d] = { init_reserved },
2154 [0x8e] = { init_gpio },
2155 [0x8f] = { init_ram_restrict_zm_reg_group },
2156 [0x90] = { init_copy_zm_reg },
2157 [0x91] = { init_zm_reg_group },
2158 [0x92] = { init_reserved },
2159 [0x96] = { init_xlat },
2160 [0x97] = { init_zm_mask_add },
2161 [0x98] = { init_auxch },
2162 [0x99] = { init_zm_auxch },
2163 [0x9a] = { init_i2c_long_if },
2164 [0xa9] = { init_gpio_ne },
2165 [0xaa] = { init_reserved },
2166};
2167
2168#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2169
2170int
2171nvbios_exec(struct nvbios_init *init)
2172{
2173 init->nested++;
2174 while (init->offset) {
2175 u8 opcode = nv_ro08(init->bios, init->offset);
2176 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2177 error("unknown opcode 0x%02x\n", opcode);
2178 return -EINVAL;
2179 }
2180
2181 init_opcode[opcode].exec(init);
2182 }
2183 init->nested--;
2184 return 0;
2185}
2186
2187int
2188nvbios_init(struct nouveau_subdev *subdev, bool execute)
2189{
2190 struct nouveau_bios *bios = nouveau_bios(subdev);
2191 int ret = 0;
2192 int i = -1;
2193 u16 data;
2194
2195 if (execute)
2196 nv_info(bios, "running init tables\n");
2197 while (!ret && (data = (init_script(bios, ++i)))) {
2198 struct nvbios_init init = {
2199 .subdev = subdev,
2200 .bios = bios,
2201 .offset = data,
2202 .outp = NULL,
2203 .crtc = -1,
2204 .execute = execute ? 1 : 0,
2205 };
2206
2207 ret = nvbios_exec(&init);
2208 }
2209
2210 /* the vbios parser will run this right after the normal init
2211 * tables, whereas the binary driver appears to run it later.
2212 */
2213 if (!ret && (data = init_unknown_script(bios))) {
2214 struct nvbios_init init = {
2215 .subdev = subdev,
2216 .bios = bios,
2217 .offset = data,
2218 .outp = NULL,
2219 .crtc = -1,
2220 .execute = execute ? 1 : 0,
2221 };
2222
2223 ret = nvbios_exec(&init);
2224 }
2225
2226 return ret;
2227}
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 00:17:10 -0500