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path: root/drivers/gpu/drm/nouveau/nv50_mpeg.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_mpeg.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_mpeg.c241
1 files changed, 0 insertions, 241 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_mpeg.c b/drivers/gpu/drm/nouveau/nv50_mpeg.c
deleted file mode 100644
index e11bb540727b..000000000000
--- a/drivers/gpu/drm/nouveau/nv50_mpeg.c
+++ /dev/null
@@ -1,241 +0,0 @@
1/*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <drm/drmP.h>
26#include "nouveau_drv.h"
27#include "nouveau_ramht.h"
28
29struct nv50_mpeg_engine {
30 struct nouveau_exec_engine base;
31};
32
33static inline u32
34CTX_PTR(struct drm_device *dev, u32 offset)
35{
36 struct drm_nouveau_private *dev_priv = dev->dev_private;
37
38 if (dev_priv->chipset == 0x50)
39 offset += 0x0260;
40 else
41 offset += 0x0060;
42
43 return offset;
44}
45
46static int
47nv50_mpeg_context_new(struct nouveau_channel *chan, int engine)
48{
49 struct drm_device *dev = chan->dev;
50 struct drm_nouveau_private *dev_priv = dev->dev_private;
51 struct nouveau_gpuobj *ramin = chan->ramin;
52 struct nouveau_gpuobj *ctx = NULL;
53 int ret;
54
55 NV_DEBUG(dev, "ch%d\n", chan->id);
56
57 ret = nouveau_gpuobj_new(dev, chan, 128 * 4, 0, NVOBJ_FLAG_ZERO_ALLOC |
58 NVOBJ_FLAG_ZERO_FREE, &ctx);
59 if (ret)
60 return ret;
61
62 nv_wo32(ramin, CTX_PTR(dev, 0x00), 0x80190002);
63 nv_wo32(ramin, CTX_PTR(dev, 0x04), ctx->vinst + ctx->size - 1);
64 nv_wo32(ramin, CTX_PTR(dev, 0x08), ctx->vinst);
65 nv_wo32(ramin, CTX_PTR(dev, 0x0c), 0);
66 nv_wo32(ramin, CTX_PTR(dev, 0x10), 0);
67 nv_wo32(ramin, CTX_PTR(dev, 0x14), 0x00010000);
68
69 nv_wo32(ctx, 0x70, 0x00801ec1);
70 nv_wo32(ctx, 0x7c, 0x0000037c);
71 dev_priv->engine.instmem.flush(dev);
72
73 chan->engctx[engine] = ctx;
74 return 0;
75}
76
77static void
78nv50_mpeg_context_del(struct nouveau_channel *chan, int engine)
79{
80 struct nouveau_gpuobj *ctx = chan->engctx[engine];
81 struct drm_device *dev = chan->dev;
82 int i;
83
84 for (i = 0x00; i <= 0x14; i += 4)
85 nv_wo32(chan->ramin, CTX_PTR(dev, i), 0x00000000);
86
87 nouveau_gpuobj_ref(NULL, &ctx);
88 chan->engctx[engine] = NULL;
89}
90
91static int
92nv50_mpeg_object_new(struct nouveau_channel *chan, int engine,
93 u32 handle, u16 class)
94{
95 struct drm_device *dev = chan->dev;
96 struct drm_nouveau_private *dev_priv = dev->dev_private;
97 struct nouveau_gpuobj *obj = NULL;
98 int ret;
99
100 ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
101 if (ret)
102 return ret;
103 obj->engine = 2;
104 obj->class = class;
105
106 nv_wo32(obj, 0x00, class);
107 nv_wo32(obj, 0x04, 0x00000000);
108 nv_wo32(obj, 0x08, 0x00000000);
109 nv_wo32(obj, 0x0c, 0x00000000);
110 dev_priv->engine.instmem.flush(dev);
111
112 ret = nouveau_ramht_insert(chan, handle, obj);
113 nouveau_gpuobj_ref(NULL, &obj);
114 return ret;
115}
116
117static void
118nv50_mpeg_tlb_flush(struct drm_device *dev, int engine)
119{
120 nv50_vm_flush_engine(dev, 0x08);
121}
122
123static int
124nv50_mpeg_init(struct drm_device *dev, int engine)
125{
126 nv_wr32(dev, 0x00b32c, 0x00000000);
127 nv_wr32(dev, 0x00b314, 0x00000100);
128 nv_wr32(dev, 0x00b0e0, 0x0000001a);
129
130 nv_wr32(dev, 0x00b220, 0x00000044);
131 nv_wr32(dev, 0x00b300, 0x00801ec1);
132 nv_wr32(dev, 0x00b390, 0x00000000);
133 nv_wr32(dev, 0x00b394, 0x00000000);
134 nv_wr32(dev, 0x00b398, 0x00000000);
135 nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
136
137 nv_wr32(dev, 0x00b100, 0xffffffff);
138 nv_wr32(dev, 0x00b140, 0xffffffff);
139
140 if (!nv_wait(dev, 0x00b200, 0x00000001, 0x00000000)) {
141 NV_ERROR(dev, "PMPEG init: 0x%08x\n", nv_rd32(dev, 0x00b200));
142 return -EBUSY;
143 }
144
145 return 0;
146}
147
148static int
149nv50_mpeg_fini(struct drm_device *dev, int engine, bool suspend)
150{
151 nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
152 nv_wr32(dev, 0x00b140, 0x00000000);
153 return 0;
154}
155
156static void
157nv50_mpeg_isr(struct drm_device *dev)
158{
159 u32 stat = nv_rd32(dev, 0x00b100);
160 u32 type = nv_rd32(dev, 0x00b230);
161 u32 mthd = nv_rd32(dev, 0x00b234);
162 u32 data = nv_rd32(dev, 0x00b238);
163 u32 show = stat;
164
165 if (stat & 0x01000000) {
166 /* happens on initial binding of the object */
167 if (type == 0x00000020 && mthd == 0x0000) {
168 nv_wr32(dev, 0x00b308, 0x00000100);
169 show &= ~0x01000000;
170 }
171 }
172
173 if (show && nouveau_ratelimit()) {
174 NV_INFO(dev, "PMPEG - 0x%08x 0x%08x 0x%08x 0x%08x\n",
175 stat, type, mthd, data);
176 }
177
178 nv_wr32(dev, 0x00b100, stat);
179 nv_wr32(dev, 0x00b230, 0x00000001);
180 nv50_fb_vm_trap(dev, 1);
181}
182
183static void
184nv50_vpe_isr(struct drm_device *dev)
185{
186 if (nv_rd32(dev, 0x00b100))
187 nv50_mpeg_isr(dev);
188
189 if (nv_rd32(dev, 0x00b800)) {
190 u32 stat = nv_rd32(dev, 0x00b800);
191 NV_INFO(dev, "PMSRCH: 0x%08x\n", stat);
192 nv_wr32(dev, 0xb800, stat);
193 }
194}
195
196static void
197nv50_mpeg_destroy(struct drm_device *dev, int engine)
198{
199 struct nv50_mpeg_engine *pmpeg = nv_engine(dev, engine);
200
201 nouveau_irq_unregister(dev, 0);
202
203 NVOBJ_ENGINE_DEL(dev, MPEG);
204 kfree(pmpeg);
205}
206
207int
208nv50_mpeg_create(struct drm_device *dev)
209{
210 struct drm_nouveau_private *dev_priv = dev->dev_private;
211 struct nv50_mpeg_engine *pmpeg;
212
213 pmpeg = kzalloc(sizeof(*pmpeg), GFP_KERNEL);
214 if (!pmpeg)
215 return -ENOMEM;
216
217 pmpeg->base.destroy = nv50_mpeg_destroy;
218 pmpeg->base.init = nv50_mpeg_init;
219 pmpeg->base.fini = nv50_mpeg_fini;
220 pmpeg->base.context_new = nv50_mpeg_context_new;
221 pmpeg->base.context_del = nv50_mpeg_context_del;
222 pmpeg->base.object_new = nv50_mpeg_object_new;
223 pmpeg->base.tlb_flush = nv50_mpeg_tlb_flush;
224
225 if (dev_priv->chipset == 0x50) {
226 nouveau_irq_register(dev, 0, nv50_vpe_isr);
227 NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
228 NVOBJ_CLASS(dev, 0x3174, MPEG);
229#if 0
230 NVOBJ_ENGINE_ADD(dev, ME, &pme->base);
231 NVOBJ_CLASS(dev, 0x4075, ME);
232#endif
233 } else {
234 nouveau_irq_register(dev, 0, nv50_mpeg_isr);
235 NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
236 NVOBJ_CLASS(dev, 0x8274, MPEG);
237 }
238
239 return 0;
240
241}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 16:41:30 -0500