aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau/nv50_fifo.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_fifo.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fifo.c28
1 files changed, 12 insertions, 16 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index 3bc2a565c20b..3961c8778780 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -193,8 +193,9 @@ just_reset:
193 nv50_fifo_init_context_table(dev); 193 nv50_fifo_init_context_table(dev);
194 nv50_fifo_init_regs__nv(dev); 194 nv50_fifo_init_regs__nv(dev);
195 nv50_fifo_init_regs(dev); 195 nv50_fifo_init_regs(dev);
196 dev_priv->engine.fifo.enable(dev); 196 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
197 dev_priv->engine.fifo.reassign(dev, true); 197 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
198 nv_wr32(dev, NV03_PFIFO_CACHES, 1);
198 199
199 return 0; 200 return 0;
200} 201}
@@ -218,13 +219,6 @@ nv50_fifo_takedown(struct drm_device *dev)
218} 219}
219 220
220int 221int
221nv50_fifo_channel_id(struct drm_device *dev)
222{
223 return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
224 NV50_PFIFO_CACHE1_PUSH1_CHID_MASK;
225}
226
227int
228nv50_fifo_create_context(struct nouveau_channel *chan) 222nv50_fifo_create_context(struct nouveau_channel *chan)
229{ 223{
230 struct drm_device *dev = chan->dev; 224 struct drm_device *dev = chan->dev;
@@ -313,13 +307,16 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
313 NV_DEBUG(dev, "ch%d\n", chan->id); 307 NV_DEBUG(dev, "ch%d\n", chan->id);
314 308
315 spin_lock_irqsave(&dev_priv->context_switch_lock, flags); 309 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
316 pfifo->reassign(dev, false); 310 nv_wr32(dev, NV03_PFIFO_CACHES, 0);
317 311
318 /* Unload the context if it's the currently active one */ 312 /* Unload the context if it's the currently active one */
319 if (pfifo->channel_id(dev) == chan->id) { 313 if ((nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 0x7f) == chan->id) {
320 pfifo->disable(dev); 314 nv_mask(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
315 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
316 nv_mask(dev, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
321 pfifo->unload_context(dev); 317 pfifo->unload_context(dev);
322 pfifo->enable(dev); 318 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
319 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
323 } 320 }
324 321
325 /* This will ensure the channel is seen as disabled. */ 322 /* This will ensure the channel is seen as disabled. */
@@ -332,7 +329,7 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
332 nv50_fifo_channel_disable(dev, 127); 329 nv50_fifo_channel_disable(dev, 127);
333 nv50_fifo_playlist_update(dev); 330 nv50_fifo_playlist_update(dev);
334 331
335 pfifo->reassign(dev, true); 332 nv_wr32(dev, NV03_PFIFO_CACHES, 1);
336 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); 333 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
337 334
338 /* Free the channel resources */ 335 /* Free the channel resources */
@@ -416,14 +413,13 @@ int
416nv50_fifo_unload_context(struct drm_device *dev) 413nv50_fifo_unload_context(struct drm_device *dev)
417{ 414{
418 struct drm_nouveau_private *dev_priv = dev->dev_private; 415 struct drm_nouveau_private *dev_priv = dev->dev_private;
419 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
420 struct nouveau_gpuobj *ramfc, *cache; 416 struct nouveau_gpuobj *ramfc, *cache;
421 struct nouveau_channel *chan = NULL; 417 struct nouveau_channel *chan = NULL;
422 int chid, get, put, ptr; 418 int chid, get, put, ptr;
423 419
424 NV_DEBUG(dev, "\n"); 420 NV_DEBUG(dev, "\n");
425 421
426 chid = pfifo->channel_id(dev); 422 chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 0x7f;
427 if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1) 423 if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1)
428 return 0; 424 return 0;
429 425