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path: root/drivers/gpu/drm/nouveau/nv50_crtc.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_crtc.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_crtc.c790
1 files changed, 790 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
new file mode 100644
index 000000000000..cfabeb974a56
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -0,0 +1,790 @@
1/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "drmP.h"
28#include "drm_mode.h"
29#include "drm_crtc_helper.h"
30
31#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
32#include "nouveau_reg.h"
33#include "nouveau_drv.h"
34#include "nouveau_hw.h"
35#include "nouveau_encoder.h"
36#include "nouveau_crtc.h"
37#include "nouveau_fb.h"
38#include "nouveau_connector.h"
39#include "nv50_display.h"
40
41static void
42nv50_crtc_lut_load(struct drm_crtc *crtc)
43{
44 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
46 int i;
47
48 NV_DEBUG_KMS(crtc->dev, "\n");
49
50 for (i = 0; i < 256; i++) {
51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
52 writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2);
53 writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4);
54 }
55
56 if (nv_crtc->lut.depth == 30) {
57 writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0);
58 writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2);
59 writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4);
60 }
61}
62
63int
64nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
65{
66 struct drm_device *dev = nv_crtc->base.dev;
67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 struct nouveau_channel *evo = dev_priv->evo;
69 int index = nv_crtc->index, ret;
70
71 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
72 NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
73
74 if (blanked) {
75 nv_crtc->cursor.hide(nv_crtc, false);
76
77 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5);
78 if (ret) {
79 NV_ERROR(dev, "no space while blanking crtc\n");
80 return ret;
81 }
82 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
83 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK);
84 OUT_RING(evo, 0);
85 if (dev_priv->chipset != 0x50) {
86 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
87 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE);
88 }
89
90 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
91 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
92 } else {
93 if (nv_crtc->cursor.visible)
94 nv_crtc->cursor.show(nv_crtc, false);
95 else
96 nv_crtc->cursor.hide(nv_crtc, false);
97
98 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8);
99 if (ret) {
100 NV_ERROR(dev, "no space while unblanking crtc\n");
101 return ret;
102 }
103 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
104 OUT_RING(evo, nv_crtc->lut.depth == 8 ?
105 NV50_EVO_CRTC_CLUT_MODE_OFF :
106 NV50_EVO_CRTC_CLUT_MODE_ON);
107 OUT_RING(evo, (nv_crtc->lut.nvbo->bo.mem.mm_node->start <<
108 PAGE_SHIFT) >> 8);
109 if (dev_priv->chipset != 0x50) {
110 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
111 OUT_RING(evo, NvEvoVRAM);
112 }
113
114 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2);
115 OUT_RING(evo, nv_crtc->fb.offset >> 8);
116 OUT_RING(evo, 0);
117 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
118 if (dev_priv->chipset != 0x50)
119 if (nv_crtc->fb.tile_flags == 0x7a00)
120 OUT_RING(evo, NvEvoFB32);
121 else
122 if (nv_crtc->fb.tile_flags == 0x7000)
123 OUT_RING(evo, NvEvoFB16);
124 else
125 OUT_RING(evo, NvEvoVRAM);
126 else
127 OUT_RING(evo, NvEvoVRAM);
128 }
129
130 nv_crtc->fb.blanked = blanked;
131 return 0;
132}
133
134static int
135nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
136{
137 struct drm_device *dev = nv_crtc->base.dev;
138 struct drm_nouveau_private *dev_priv = dev->dev_private;
139 struct nouveau_channel *evo = dev_priv->evo;
140 int ret;
141
142 NV_DEBUG_KMS(dev, "\n");
143
144 ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
145 if (ret) {
146 NV_ERROR(dev, "no space while setting dither\n");
147 return ret;
148 }
149
150 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1);
151 if (on)
152 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_ON);
153 else
154 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_OFF);
155
156 if (update) {
157 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
158 OUT_RING(evo, 0);
159 FIRE_RING(evo);
160 }
161
162 return 0;
163}
164
165struct nouveau_connector *
166nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
167{
168 struct drm_device *dev = nv_crtc->base.dev;
169 struct drm_connector *connector;
170 struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
171
172 /* The safest approach is to find an encoder with the right crtc, that
173 * is also linked to a connector. */
174 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
175 if (connector->encoder)
176 if (connector->encoder->crtc == crtc)
177 return nouveau_connector(connector);
178 }
179
180 return NULL;
181}
182
183static int
184nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
185{
186 struct nouveau_connector *nv_connector =
187 nouveau_crtc_connector_get(nv_crtc);
188 struct drm_device *dev = nv_crtc->base.dev;
189 struct drm_nouveau_private *dev_priv = dev->dev_private;
190 struct nouveau_channel *evo = dev_priv->evo;
191 struct drm_display_mode *native_mode = NULL;
192 struct drm_display_mode *mode = &nv_crtc->base.mode;
193 uint32_t outX, outY, horiz, vert;
194 int ret;
195
196 NV_DEBUG_KMS(dev, "\n");
197
198 switch (scaling_mode) {
199 case DRM_MODE_SCALE_NONE:
200 break;
201 default:
202 if (!nv_connector || !nv_connector->native_mode) {
203 NV_ERROR(dev, "No native mode, forcing panel scaling\n");
204 scaling_mode = DRM_MODE_SCALE_NONE;
205 } else {
206 native_mode = nv_connector->native_mode;
207 }
208 break;
209 }
210
211 switch (scaling_mode) {
212 case DRM_MODE_SCALE_ASPECT:
213 horiz = (native_mode->hdisplay << 19) / mode->hdisplay;
214 vert = (native_mode->vdisplay << 19) / mode->vdisplay;
215
216 if (vert > horiz) {
217 outX = (mode->hdisplay * horiz) >> 19;
218 outY = (mode->vdisplay * horiz) >> 19;
219 } else {
220 outX = (mode->hdisplay * vert) >> 19;
221 outY = (mode->vdisplay * vert) >> 19;
222 }
223 break;
224 case DRM_MODE_SCALE_FULLSCREEN:
225 outX = native_mode->hdisplay;
226 outY = native_mode->vdisplay;
227 break;
228 case DRM_MODE_SCALE_CENTER:
229 case DRM_MODE_SCALE_NONE:
230 default:
231 outX = mode->hdisplay;
232 outY = mode->vdisplay;
233 break;
234 }
235
236 ret = RING_SPACE(evo, update ? 7 : 5);
237 if (ret)
238 return ret;
239
240 /* Got a better name for SCALER_ACTIVE? */
241 /* One day i've got to really figure out why this is needed. */
242 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1);
243 if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ||
244 (mode->flags & DRM_MODE_FLAG_INTERLACE) ||
245 mode->hdisplay != outX || mode->vdisplay != outY) {
246 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_ACTIVE);
247 } else {
248 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_INACTIVE);
249 }
250
251 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2);
252 OUT_RING(evo, outY << 16 | outX);
253 OUT_RING(evo, outY << 16 | outX);
254
255 if (update) {
256 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
257 OUT_RING(evo, 0);
258 FIRE_RING(evo);
259 }
260
261 return 0;
262}
263
264int
265nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
266{
267 uint32_t pll_reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);
268 struct nouveau_pll_vals pll;
269 struct pll_lims limits;
270 uint32_t reg1, reg2;
271 int ret;
272
273 ret = get_pll_limits(dev, pll_reg, &limits);
274 if (ret)
275 return ret;
276
277 ret = nouveau_calc_pll_mnp(dev, &limits, pclk, &pll);
278 if (ret <= 0)
279 return ret;
280
281 if (limits.vco2.maxfreq) {
282 reg1 = nv_rd32(dev, pll_reg + 4) & 0xff00ff00;
283 reg2 = nv_rd32(dev, pll_reg + 8) & 0x8000ff00;
284 nv_wr32(dev, pll_reg, 0x10000611);
285 nv_wr32(dev, pll_reg + 4, reg1 | (pll.M1 << 16) | pll.N1);
286 nv_wr32(dev, pll_reg + 8,
287 reg2 | (pll.log2P << 28) | (pll.M2 << 16) | pll.N2);
288 } else {
289 reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000;
290 nv_wr32(dev, pll_reg, 0x50000610);
291 nv_wr32(dev, pll_reg + 4, reg1 |
292 (pll.log2P << 16) | (pll.M1 << 8) | pll.N1);
293 }
294
295 return 0;
296}
297
298static void
299nv50_crtc_destroy(struct drm_crtc *crtc)
300{
301 struct drm_device *dev;
302 struct nouveau_crtc *nv_crtc;
303
304 if (!crtc)
305 return;
306
307 dev = crtc->dev;
308 nv_crtc = nouveau_crtc(crtc);
309
310 NV_DEBUG_KMS(dev, "\n");
311
312 drm_crtc_cleanup(&nv_crtc->base);
313
314 nv50_cursor_fini(nv_crtc);
315
316 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
317 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
318 kfree(nv_crtc->mode);
319 kfree(nv_crtc);
320}
321
322int
323nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
324 uint32_t buffer_handle, uint32_t width, uint32_t height)
325{
326 struct drm_device *dev = crtc->dev;
327 struct drm_nouveau_private *dev_priv = dev->dev_private;
328 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
329 struct nouveau_bo *cursor = NULL;
330 struct drm_gem_object *gem;
331 int ret = 0, i;
332
333 if (width != 64 || height != 64)
334 return -EINVAL;
335
336 if (!buffer_handle) {
337 nv_crtc->cursor.hide(nv_crtc, true);
338 return 0;
339 }
340
341 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
342 if (!gem)
343 return -EINVAL;
344 cursor = nouveau_gem_object(gem);
345
346 ret = nouveau_bo_map(cursor);
347 if (ret)
348 goto out;
349
350 /* The simple will do for now. */
351 for (i = 0; i < 64 * 64; i++)
352 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i));
353
354 nouveau_bo_unmap(cursor);
355
356 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset -
357 dev_priv->vm_vram_base);
358 nv_crtc->cursor.show(nv_crtc, true);
359
360out:
361 drm_gem_object_unreference_unlocked(gem);
362 return ret;
363}
364
365int
366nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
367{
368 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
369
370 nv_crtc->cursor.set_pos(nv_crtc, x, y);
371 return 0;
372}
373
374static void
375nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
376 uint32_t size)
377{
378 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
379 int i;
380
381 if (size != 256)
382 return;
383
384 for (i = 0; i < 256; i++) {
385 nv_crtc->lut.r[i] = r[i];
386 nv_crtc->lut.g[i] = g[i];
387 nv_crtc->lut.b[i] = b[i];
388 }
389
390 /* We need to know the depth before we upload, but it's possible to
391 * get called before a framebuffer is bound. If this is the case,
392 * mark the lut values as dirty by setting depth==0, and it'll be
393 * uploaded on the first mode_set_base()
394 */
395 if (!nv_crtc->base.fb) {
396 nv_crtc->lut.depth = 0;
397 return;
398 }
399
400 nv50_crtc_lut_load(crtc);
401}
402
403static void
404nv50_crtc_save(struct drm_crtc *crtc)
405{
406 NV_ERROR(crtc->dev, "!!\n");
407}
408
409static void
410nv50_crtc_restore(struct drm_crtc *crtc)
411{
412 NV_ERROR(crtc->dev, "!!\n");
413}
414
415static const struct drm_crtc_funcs nv50_crtc_funcs = {
416 .save = nv50_crtc_save,
417 .restore = nv50_crtc_restore,
418 .cursor_set = nv50_crtc_cursor_set,
419 .cursor_move = nv50_crtc_cursor_move,
420 .gamma_set = nv50_crtc_gamma_set,
421 .set_config = drm_crtc_helper_set_config,
422 .destroy = nv50_crtc_destroy,
423};
424
425static void
426nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
427{
428}
429
430static void
431nv50_crtc_prepare(struct drm_crtc *crtc)
432{
433 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
434 struct drm_device *dev = crtc->dev;
435 struct drm_encoder *encoder;
436 uint32_t dac = 0, sor = 0;
437
438 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
439
440 /* Disconnect all unused encoders. */
441 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
442 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
443
444 if (!drm_helper_encoder_in_use(encoder))
445 continue;
446
447 if (nv_encoder->dcb->type == OUTPUT_ANALOG ||
448 nv_encoder->dcb->type == OUTPUT_TV)
449 dac |= (1 << nv_encoder->or);
450 else
451 sor |= (1 << nv_encoder->or);
452 }
453
454 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
455 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
456
457 if (nv_encoder->dcb->type == OUTPUT_ANALOG ||
458 nv_encoder->dcb->type == OUTPUT_TV) {
459 if (dac & (1 << nv_encoder->or))
460 continue;
461 } else {
462 if (sor & (1 << nv_encoder->or))
463 continue;
464 }
465
466 nv_encoder->disconnect(nv_encoder);
467 }
468
469 nv50_crtc_blank(nv_crtc, true);
470}
471
472static void
473nv50_crtc_commit(struct drm_crtc *crtc)
474{
475 struct drm_crtc *crtc2;
476 struct drm_device *dev = crtc->dev;
477 struct drm_nouveau_private *dev_priv = dev->dev_private;
478 struct nouveau_channel *evo = dev_priv->evo;
479 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
480 int ret;
481
482 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
483
484 nv50_crtc_blank(nv_crtc, false);
485
486 /* Explicitly blank all unused crtc's. */
487 list_for_each_entry(crtc2, &dev->mode_config.crtc_list, head) {
488 if (!drm_helper_crtc_in_use(crtc2))
489 nv50_crtc_blank(nouveau_crtc(crtc2), true);
490 }
491
492 ret = RING_SPACE(evo, 2);
493 if (ret) {
494 NV_ERROR(dev, "no space while committing crtc\n");
495 return;
496 }
497 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
498 OUT_RING(evo, 0);
499 FIRE_RING(evo);
500}
501
502static bool
503nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
504 struct drm_display_mode *adjusted_mode)
505{
506 return true;
507}
508
509static int
510nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, int x, int y,
511 struct drm_framebuffer *old_fb, bool update)
512{
513 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
514 struct drm_device *dev = nv_crtc->base.dev;
515 struct drm_nouveau_private *dev_priv = dev->dev_private;
516 struct nouveau_channel *evo = dev_priv->evo;
517 struct drm_framebuffer *drm_fb = nv_crtc->base.fb;
518 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
519 int ret, format;
520
521 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
522
523 switch (drm_fb->depth) {
524 case 8:
525 format = NV50_EVO_CRTC_FB_DEPTH_8;
526 break;
527 case 15:
528 format = NV50_EVO_CRTC_FB_DEPTH_15;
529 break;
530 case 16:
531 format = NV50_EVO_CRTC_FB_DEPTH_16;
532 break;
533 case 24:
534 case 32:
535 format = NV50_EVO_CRTC_FB_DEPTH_24;
536 break;
537 case 30:
538 format = NV50_EVO_CRTC_FB_DEPTH_30;
539 break;
540 default:
541 NV_ERROR(dev, "unknown depth %d\n", drm_fb->depth);
542 return -EINVAL;
543 }
544
545 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
546 if (ret)
547 return ret;
548
549 if (old_fb) {
550 struct nouveau_framebuffer *ofb = nouveau_framebuffer(old_fb);
551 nouveau_bo_unpin(ofb->nvbo);
552 }
553
554 nv_crtc->fb.offset = fb->nvbo->bo.offset - dev_priv->vm_vram_base;
555 nv_crtc->fb.tile_flags = fb->nvbo->tile_flags;
556 nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
557 if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) {
558 ret = RING_SPACE(evo, 2);
559 if (ret)
560 return ret;
561
562 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1);
563 if (nv_crtc->fb.tile_flags == 0x7a00)
564 OUT_RING(evo, NvEvoFB32);
565 else
566 if (nv_crtc->fb.tile_flags == 0x7000)
567 OUT_RING(evo, NvEvoFB16);
568 else
569 OUT_RING(evo, NvEvoVRAM);
570 }
571
572 ret = RING_SPACE(evo, 12);
573 if (ret)
574 return ret;
575
576 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5);
577 OUT_RING(evo, nv_crtc->fb.offset >> 8);
578 OUT_RING(evo, 0);
579 OUT_RING(evo, (drm_fb->height << 16) | drm_fb->width);
580 if (!nv_crtc->fb.tile_flags) {
581 OUT_RING(evo, drm_fb->pitch | (1 << 20));
582 } else {
583 OUT_RING(evo, ((drm_fb->pitch / 4) << 4) |
584 fb->nvbo->tile_mode);
585 }
586 if (dev_priv->chipset == 0x50)
587 OUT_RING(evo, (fb->nvbo->tile_flags << 8) | format);
588 else
589 OUT_RING(evo, format);
590
591 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1);
592 OUT_RING(evo, fb->base.depth == 8 ?
593 NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON);
594
595 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
596 OUT_RING(evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR);
597 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1);
598 OUT_RING(evo, (y << 16) | x);
599
600 if (nv_crtc->lut.depth != fb->base.depth) {
601 nv_crtc->lut.depth = fb->base.depth;
602 nv50_crtc_lut_load(crtc);
603 }
604
605 if (update) {
606 ret = RING_SPACE(evo, 2);
607 if (ret)
608 return ret;
609 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
610 OUT_RING(evo, 0);
611 FIRE_RING(evo);
612 }
613
614 return 0;
615}
616
617static int
618nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
619 struct drm_display_mode *adjusted_mode, int x, int y,
620 struct drm_framebuffer *old_fb)
621{
622 struct drm_device *dev = crtc->dev;
623 struct drm_nouveau_private *dev_priv = dev->dev_private;
624 struct nouveau_channel *evo = dev_priv->evo;
625 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
626 struct nouveau_connector *nv_connector = NULL;
627 uint32_t hsync_dur, vsync_dur, hsync_start_to_end, vsync_start_to_end;
628 uint32_t hunk1, vunk1, vunk2a, vunk2b;
629 int ret;
630
631 /* Find the connector attached to this CRTC */
632 nv_connector = nouveau_crtc_connector_get(nv_crtc);
633
634 *nv_crtc->mode = *adjusted_mode;
635
636 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
637
638 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
639 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
640 hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start;
641 vsync_start_to_end = adjusted_mode->vtotal - adjusted_mode->vsync_start;
642 /* I can't give this a proper name, anyone else can? */
643 hunk1 = adjusted_mode->htotal -
644 adjusted_mode->hsync_start + adjusted_mode->hdisplay;
645 vunk1 = adjusted_mode->vtotal -
646 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
647 /* Another strange value, this time only for interlaced adjusted_modes. */
648 vunk2a = 2 * adjusted_mode->vtotal -
649 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
650 vunk2b = adjusted_mode->vtotal -
651 adjusted_mode->vsync_start + adjusted_mode->vtotal;
652
653 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
654 vsync_dur /= 2;
655 vsync_start_to_end /= 2;
656 vunk1 /= 2;
657 vunk2a /= 2;
658 vunk2b /= 2;
659 /* magic */
660 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
661 vsync_start_to_end -= 1;
662 vunk1 -= 1;
663 vunk2a -= 1;
664 vunk2b -= 1;
665 }
666 }
667
668 ret = RING_SPACE(evo, 17);
669 if (ret)
670 return ret;
671
672 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2);
673 OUT_RING(evo, adjusted_mode->clock | 0x800000);
674 OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0);
675
676 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5);
677 OUT_RING(evo, 0);
678 OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal);
679 OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1));
680 OUT_RING(evo, (vsync_start_to_end - 1) << 16 |
681 (hsync_start_to_end - 1));
682 OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1));
683
684 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
685 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1);
686 OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1));
687 } else {
688 OUT_RING(evo, 0);
689 OUT_RING(evo, 0);
690 }
691
692 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1);
693 OUT_RING(evo, 0);
694
695 /* This is the actual resolution of the mode. */
696 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1);
697 OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay);
698 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1);
699 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0));
700
701 nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false);
702 nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false);
703
704 return nv50_crtc_do_mode_set_base(crtc, x, y, old_fb, false);
705}
706
707static int
708nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
709 struct drm_framebuffer *old_fb)
710{
711 return nv50_crtc_do_mode_set_base(crtc, x, y, old_fb, true);
712}
713
714static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
715 .dpms = nv50_crtc_dpms,
716 .prepare = nv50_crtc_prepare,
717 .commit = nv50_crtc_commit,
718 .mode_fixup = nv50_crtc_mode_fixup,
719 .mode_set = nv50_crtc_mode_set,
720 .mode_set_base = nv50_crtc_mode_set_base,
721 .load_lut = nv50_crtc_lut_load,
722};
723
724int
725nv50_crtc_create(struct drm_device *dev, int index)
726{
727 struct nouveau_crtc *nv_crtc = NULL;
728 int ret, i;
729
730 NV_DEBUG_KMS(dev, "\n");
731
732 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
733 if (!nv_crtc)
734 return -ENOMEM;
735
736 nv_crtc->mode = kzalloc(sizeof(*nv_crtc->mode), GFP_KERNEL);
737 if (!nv_crtc->mode) {
738 kfree(nv_crtc);
739 return -ENOMEM;
740 }
741
742 /* Default CLUT parameters, will be activated on the hw upon
743 * first mode set.
744 */
745 for (i = 0; i < 256; i++) {
746 nv_crtc->lut.r[i] = i << 8;
747 nv_crtc->lut.g[i] = i << 8;
748 nv_crtc->lut.b[i] = i << 8;
749 }
750 nv_crtc->lut.depth = 0;
751
752 ret = nouveau_bo_new(dev, NULL, 4096, 0x100, TTM_PL_FLAG_VRAM,
753 0, 0x0000, false, true, &nv_crtc->lut.nvbo);
754 if (!ret) {
755 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
756 if (!ret)
757 ret = nouveau_bo_map(nv_crtc->lut.nvbo);
758 if (ret)
759 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
760 }
761
762 if (ret) {
763 kfree(nv_crtc->mode);
764 kfree(nv_crtc);
765 return ret;
766 }
767
768 nv_crtc->index = index;
769
770 /* set function pointers */
771 nv_crtc->set_dither = nv50_crtc_set_dither;
772 nv_crtc->set_scale = nv50_crtc_set_scale;
773
774 drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs);
775 drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs);
776 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
777
778 ret = nouveau_bo_new(dev, NULL, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
779 0, 0x0000, false, true, &nv_crtc->cursor.nvbo);
780 if (!ret) {
781 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
782 if (!ret)
783 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
784 if (ret)
785 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
786 }
787
788 nv50_cursor_init(nv_crtc);
789 return 0;
790}
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-24 14:56:28 -0400