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path: root/drivers/gpu/drm/nouveau/nv40_graph.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv40_graph.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c427
1 files changed, 427 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
new file mode 100644
index 000000000000..0616c96e4b67
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -0,0 +1,427 @@
1/*
2 * Copyright (C) 2007 Ben Skeggs.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "drmP.h"
28#include "drm.h"
29#include "nouveau_drv.h"
30#include "nouveau_grctx.h"
31
32struct nouveau_channel *
33nv40_graph_channel(struct drm_device *dev)
34{
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 uint32_t inst;
37 int i;
38
39 inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
40 if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
41 return NULL;
42 inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
43
44 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
45 struct nouveau_channel *chan = dev_priv->fifos[i];
46
47 if (chan && chan->ramin_grctx &&
48 chan->ramin_grctx->instance == inst)
49 return chan;
50 }
51
52 return NULL;
53}
54
55int
56nv40_graph_create_context(struct nouveau_channel *chan)
57{
58 struct drm_device *dev = chan->dev;
59 struct drm_nouveau_private *dev_priv = dev->dev_private;
60 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
61 int ret;
62
63 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
64 16, NVOBJ_FLAG_ZERO_ALLOC,
65 &chan->ramin_grctx);
66 if (ret)
67 return ret;
68
69 /* Initialise default context values */
70 dev_priv->engine.instmem.prepare_access(dev, true);
71 if (!pgraph->ctxprog) {
72 struct nouveau_grctx ctx = {};
73
74 ctx.dev = chan->dev;
75 ctx.mode = NOUVEAU_GRCTX_VALS;
76 ctx.data = chan->ramin_grctx->gpuobj;
77 nv40_grctx_init(&ctx);
78 } else {
79 nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
80 }
81 nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
82 chan->ramin_grctx->gpuobj->im_pramin->start);
83 dev_priv->engine.instmem.finish_access(dev);
84 return 0;
85}
86
87void
88nv40_graph_destroy_context(struct nouveau_channel *chan)
89{
90 nouveau_gpuobj_ref_del(chan->dev, &chan->ramin_grctx);
91}
92
93static int
94nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
95{
96 uint32_t old_cp, tv = 1000, tmp;
97 int i;
98
99 old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
100 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
101
102 tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
103 tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
104 NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
105 nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
106
107 tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
108 tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
109 nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
110
111 nouveau_wait_for_idle(dev);
112
113 for (i = 0; i < tv; i++) {
114 if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
115 break;
116 }
117
118 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
119
120 if (i == tv) {
121 uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
122 NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
123 NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
124 ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
125 ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
126 NV_ERROR(dev, "0x40030C = 0x%08x\n",
127 nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
128 return -EBUSY;
129 }
130
131 return 0;
132}
133
134/* Restore the context for a specific channel into PGRAPH */
135int
136nv40_graph_load_context(struct nouveau_channel *chan)
137{
138 struct drm_device *dev = chan->dev;
139 uint32_t inst;
140 int ret;
141
142 if (!chan->ramin_grctx)
143 return -EINVAL;
144 inst = chan->ramin_grctx->instance >> 4;
145
146 ret = nv40_graph_transfer_context(dev, inst, 0);
147 if (ret)
148 return ret;
149
150 /* 0x40032C, no idea of it's exact function. Could simply be a
151 * record of the currently active PGRAPH context. It's currently
152 * unknown as to what bit 24 does. The nv ddx has it set, so we will
153 * set it here too.
154 */
155 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
156 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
157 (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
158 NV40_PGRAPH_CTXCTL_CUR_LOADED);
159 /* 0x32E0 records the instance address of the active FIFO's PGRAPH
160 * context. If at any time this doesn't match 0x40032C, you will
161 * recieve PGRAPH_INTR_CONTEXT_SWITCH
162 */
163 nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
164 return 0;
165}
166
167int
168nv40_graph_unload_context(struct drm_device *dev)
169{
170 uint32_t inst;
171 int ret;
172
173 inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
174 if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
175 return 0;
176 inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
177
178 ret = nv40_graph_transfer_context(dev, inst, 1);
179
180 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
181 return ret;
182}
183
184void
185nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
186 uint32_t size, uint32_t pitch)
187{
188 struct drm_nouveau_private *dev_priv = dev->dev_private;
189 uint32_t limit = max(1u, addr + size) - 1;
190
191 if (pitch)
192 addr |= 1;
193
194 switch (dev_priv->chipset) {
195 case 0x44:
196 case 0x4a:
197 case 0x4e:
198 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
199 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
200 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
201 break;
202
203 case 0x46:
204 case 0x47:
205 case 0x49:
206 case 0x4b:
207 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
208 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
209 nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
210 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
211 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
212 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
213 break;
214
215 default:
216 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
217 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
218 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
219 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
220 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
221 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
222 break;
223 }
224}
225
226/*
227 * G70 0x47
228 * G71 0x49
229 * NV45 0x48
230 * G72[M] 0x46
231 * G73 0x4b
232 * C51_G7X 0x4c
233 * C51 0x4e
234 */
235int
236nv40_graph_init(struct drm_device *dev)
237{
238 struct drm_nouveau_private *dev_priv =
239 (struct drm_nouveau_private *)dev->dev_private;
240 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
241 uint32_t vramsz;
242 int i, j;
243
244 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
245 ~NV_PMC_ENABLE_PGRAPH);
246 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
247 NV_PMC_ENABLE_PGRAPH);
248
249 if (nouveau_ctxfw) {
250 nouveau_grctx_prog_load(dev);
251 dev_priv->engine.graph.grctx_size = 175 * 1024;
252 }
253
254 if (!dev_priv->engine.graph.ctxprog) {
255 struct nouveau_grctx ctx = {};
256 uint32_t cp[256];
257
258 ctx.dev = dev;
259 ctx.mode = NOUVEAU_GRCTX_PROG;
260 ctx.data = cp;
261 ctx.ctxprog_max = 256;
262 nv40_grctx_init(&ctx);
263 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
264
265 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
266 for (i = 0; i < ctx.ctxprog_len; i++)
267 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
268 }
269
270 /* No context present currently */
271 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
272
273 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
274 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
275
276 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
277 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
278 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
279 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
280 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
281 nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
282
283 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
284 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
285
286 j = nv_rd32(dev, 0x1540) & 0xff;
287 if (j) {
288 for (i = 0; !(j & 1); j >>= 1, i++)
289 ;
290 nv_wr32(dev, 0x405000, i);
291 }
292
293 if (dev_priv->chipset == 0x40) {
294 nv_wr32(dev, 0x4009b0, 0x83280fff);
295 nv_wr32(dev, 0x4009b4, 0x000000a0);
296 } else {
297 nv_wr32(dev, 0x400820, 0x83280eff);
298 nv_wr32(dev, 0x400824, 0x000000a0);
299 }
300
301 switch (dev_priv->chipset) {
302 case 0x40:
303 case 0x45:
304 nv_wr32(dev, 0x4009b8, 0x0078e366);
305 nv_wr32(dev, 0x4009bc, 0x0000014c);
306 break;
307 case 0x41:
308 case 0x42: /* pciid also 0x00Cx */
309 /* case 0x0120: XXX (pciid) */
310 nv_wr32(dev, 0x400828, 0x007596ff);
311 nv_wr32(dev, 0x40082c, 0x00000108);
312 break;
313 case 0x43:
314 nv_wr32(dev, 0x400828, 0x0072cb77);
315 nv_wr32(dev, 0x40082c, 0x00000108);
316 break;
317 case 0x44:
318 case 0x46: /* G72 */
319 case 0x4a:
320 case 0x4c: /* G7x-based C51 */
321 case 0x4e:
322 nv_wr32(dev, 0x400860, 0);
323 nv_wr32(dev, 0x400864, 0);
324 break;
325 case 0x47: /* G70 */
326 case 0x49: /* G71 */
327 case 0x4b: /* G73 */
328 nv_wr32(dev, 0x400828, 0x07830610);
329 nv_wr32(dev, 0x40082c, 0x0000016A);
330 break;
331 default:
332 break;
333 }
334
335 nv_wr32(dev, 0x400b38, 0x2ffff800);
336 nv_wr32(dev, 0x400b3c, 0x00006000);
337
338 /* Tiling related stuff. */
339 switch (dev_priv->chipset) {
340 case 0x44:
341 case 0x4a:
342 nv_wr32(dev, 0x400bc4, 0x1003d888);
343 nv_wr32(dev, 0x400bbc, 0xb7a7b500);
344 break;
345 case 0x46:
346 nv_wr32(dev, 0x400bc4, 0x0000e024);
347 nv_wr32(dev, 0x400bbc, 0xb7a7b520);
348 break;
349 case 0x4c:
350 case 0x4e:
351 case 0x67:
352 nv_wr32(dev, 0x400bc4, 0x1003d888);
353 nv_wr32(dev, 0x400bbc, 0xb7a7b540);
354 break;
355 default:
356 break;
357 }
358
359 /* Turn all the tiling regions off. */
360 for (i = 0; i < pfb->num_tiles; i++)
361 nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
362
363 /* begin RAM config */
364 vramsz = drm_get_resource_len(dev, 0) - 1;
365 switch (dev_priv->chipset) {
366 case 0x40:
367 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
368 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
369 nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
370 nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
371 nv_wr32(dev, 0x400820, 0);
372 nv_wr32(dev, 0x400824, 0);
373 nv_wr32(dev, 0x400864, vramsz);
374 nv_wr32(dev, 0x400868, vramsz);
375 break;
376 default:
377 switch (dev_priv->chipset) {
378 case 0x46:
379 case 0x47:
380 case 0x49:
381 case 0x4b:
382 nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
383 nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
384 break;
385 default:
386 nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
387 nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
388 break;
389 }
390 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
391 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
392 nv_wr32(dev, 0x400840, 0);
393 nv_wr32(dev, 0x400844, 0);
394 nv_wr32(dev, 0x4008A0, vramsz);
395 nv_wr32(dev, 0x4008A4, vramsz);
396 break;
397 }
398
399 return 0;
400}
401
402void nv40_graph_takedown(struct drm_device *dev)
403{
404 nouveau_grctx_fini(dev);
405}
406
407struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
408 { 0x0030, false, NULL }, /* null */
409 { 0x0039, false, NULL }, /* m2mf */
410 { 0x004a, false, NULL }, /* gdirect */
411 { 0x009f, false, NULL }, /* imageblit (nv12) */
412 { 0x008a, false, NULL }, /* ifc */
413 { 0x0089, false, NULL }, /* sifm */
414 { 0x3089, false, NULL }, /* sifm (nv40) */
415 { 0x0062, false, NULL }, /* surf2d */
416 { 0x3062, false, NULL }, /* surf2d (nv40) */
417 { 0x0043, false, NULL }, /* rop */
418 { 0x0012, false, NULL }, /* beta1 */
419 { 0x0072, false, NULL }, /* beta4 */
420 { 0x0019, false, NULL }, /* cliprect */
421 { 0x0044, false, NULL }, /* pattern */
422 { 0x309e, false, NULL }, /* swzsurf */
423 { 0x4097, false, NULL }, /* curie (nv40) */
424 { 0x4497, false, NULL }, /* curie (nv44) */
425 {}
426};
427
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-13 00:39:20 -0400