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path: root/drivers/gpu/drm/nouveau/nv40_fb.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv40_fb.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv40_fb.c163
1 files changed, 0 insertions, 163 deletions
diff --git a/drivers/gpu/drm/nouveau/nv40_fb.c b/drivers/gpu/drm/nouveau/nv40_fb.c
deleted file mode 100644
index 7fbcb334c096..000000000000
--- a/drivers/gpu/drm/nouveau/nv40_fb.c
+++ /dev/null
@@ -1,163 +0,0 @@
1#include "drmP.h"
2#include "drm.h"
3#include "nouveau_drv.h"
4#include "nouveau_drm.h"
5
6void
7nv40_fb_set_tile_region(struct drm_device *dev, int i)
8{
9 struct drm_nouveau_private *dev_priv = dev->dev_private;
10 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
11
12 switch (dev_priv->chipset) {
13 case 0x40:
14 nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
15 nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
16 nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
17 break;
18
19 default:
20 nv_wr32(dev, NV40_PFB_TLIMIT(i), tile->limit);
21 nv_wr32(dev, NV40_PFB_TSIZE(i), tile->pitch);
22 nv_wr32(dev, NV40_PFB_TILE(i), tile->addr);
23 break;
24 }
25}
26
27static void
28nv40_fb_init_gart(struct drm_device *dev)
29{
30 struct drm_nouveau_private *dev_priv = dev->dev_private;
31 struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
32
33 if (dev_priv->gart_info.type != NOUVEAU_GART_HW) {
34 nv_wr32(dev, 0x100800, 0x00000001);
35 return;
36 }
37
38 nv_wr32(dev, 0x100800, gart->pinst | 0x00000002);
39 nv_mask(dev, 0x10008c, 0x00000100, 0x00000100);
40 nv_wr32(dev, 0x100820, 0x00000000);
41}
42
43static void
44nv44_fb_init_gart(struct drm_device *dev)
45{
46 struct drm_nouveau_private *dev_priv = dev->dev_private;
47 struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
48 u32 vinst;
49
50 if (dev_priv->gart_info.type != NOUVEAU_GART_HW) {
51 nv_wr32(dev, 0x100850, 0x80000000);
52 nv_wr32(dev, 0x100800, 0x00000001);
53 return;
54 }
55
56 /* calculate vram address of this PRAMIN block, object
57 * must be allocated on 512KiB alignment, and not exceed
58 * a total size of 512KiB for this to work correctly
59 */
60 vinst = nv_rd32(dev, 0x10020c);
61 vinst -= ((gart->pinst >> 19) + 1) << 19;
62
63 nv_wr32(dev, 0x100850, 0x80000000);
64 nv_wr32(dev, 0x100818, dev_priv->gart_info.dummy.addr);
65
66 nv_wr32(dev, 0x100804, dev_priv->gart_info.aper_size);
67 nv_wr32(dev, 0x100850, 0x00008000);
68 nv_mask(dev, 0x10008c, 0x00000200, 0x00000200);
69 nv_wr32(dev, 0x100820, 0x00000000);
70 nv_wr32(dev, 0x10082c, 0x00000001);
71 nv_wr32(dev, 0x100800, vinst | 0x00000010);
72}
73
74int
75nv40_fb_vram_init(struct drm_device *dev)
76{
77 struct drm_nouveau_private *dev_priv = dev->dev_private;
78
79 /* 0x001218 is actually present on a few other NV4X I looked at,
80 * and even contains sane values matching 0x100474. From looking
81 * at various vbios images however, this isn't the case everywhere.
82 * So, I chose to use the same regs I've seen NVIDIA reading around
83 * the memory detection, hopefully that'll get us the right numbers
84 */
85 if (dev_priv->chipset == 0x40) {
86 u32 pbus1218 = nv_rd32(dev, 0x001218);
87 switch (pbus1218 & 0x00000300) {
88 case 0x00000000: dev_priv->vram_type = NV_MEM_TYPE_SDRAM; break;
89 case 0x00000100: dev_priv->vram_type = NV_MEM_TYPE_DDR1; break;
90 case 0x00000200: dev_priv->vram_type = NV_MEM_TYPE_GDDR3; break;
91 case 0x00000300: dev_priv->vram_type = NV_MEM_TYPE_DDR2; break;
92 }
93 } else
94 if (dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) {
95 u32 pfb914 = nv_rd32(dev, 0x100914);
96 switch (pfb914 & 0x00000003) {
97 case 0x00000000: dev_priv->vram_type = NV_MEM_TYPE_DDR1; break;
98 case 0x00000001: dev_priv->vram_type = NV_MEM_TYPE_DDR2; break;
99 case 0x00000002: dev_priv->vram_type = NV_MEM_TYPE_GDDR3; break;
100 case 0x00000003: break;
101 }
102 } else
103 if (dev_priv->chipset != 0x4e) {
104 u32 pfb474 = nv_rd32(dev, 0x100474);
105 if (pfb474 & 0x00000004)
106 dev_priv->vram_type = NV_MEM_TYPE_GDDR3;
107 if (pfb474 & 0x00000002)
108 dev_priv->vram_type = NV_MEM_TYPE_DDR2;
109 if (pfb474 & 0x00000001)
110 dev_priv->vram_type = NV_MEM_TYPE_DDR1;
111 } else {
112 dev_priv->vram_type = NV_MEM_TYPE_STOLEN;
113 }
114
115 dev_priv->vram_size = nv_rd32(dev, 0x10020c) & 0xff000000;
116 return 0;
117}
118
119int
120nv40_fb_init(struct drm_device *dev)
121{
122 struct drm_nouveau_private *dev_priv = dev->dev_private;
123 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
124 uint32_t tmp;
125 int i;
126
127 if (dev_priv->chipset != 0x40 && dev_priv->chipset != 0x45) {
128 if (nv44_graph_class(dev))
129 nv44_fb_init_gart(dev);
130 else
131 nv40_fb_init_gart(dev);
132 }
133
134 switch (dev_priv->chipset) {
135 case 0x40:
136 case 0x45:
137 tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2);
138 nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15));
139 pfb->num_tiles = NV10_PFB_TILE__SIZE;
140 break;
141 case 0x46: /* G72 */
142 case 0x47: /* G70 */
143 case 0x49: /* G71 */
144 case 0x4b: /* G73 */
145 case 0x4c: /* C51 (G7X version) */
146 pfb->num_tiles = NV40_PFB_TILE__SIZE_1;
147 break;
148 default:
149 pfb->num_tiles = NV40_PFB_TILE__SIZE_0;
150 break;
151 }
152
153 /* Turn all the tiling regions off. */
154 for (i = 0; i < pfb->num_tiles; i++)
155 pfb->set_tile_region(dev, i);
156
157 return 0;
158}
159
160void
161nv40_fb_takedown(struct drm_device *dev)
162{
163}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 21:46:14 -0400