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path: root/drivers/gpu/drm/nouveau/nv10_graph.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv10_graph.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv10_graph.c13
1 files changed, 4 insertions, 9 deletions
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index 7255e4a4d3f3..fb1d88a951de 100644
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -759,7 +759,6 @@ static int
759nv10_graph_unload_context(struct drm_device *dev) 759nv10_graph_unload_context(struct drm_device *dev)
760{ 760{
761 struct drm_nouveau_private *dev_priv = dev->dev_private; 761 struct drm_nouveau_private *dev_priv = dev->dev_private;
762 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
763 struct nouveau_channel *chan; 762 struct nouveau_channel *chan;
764 struct graph_state *ctx; 763 struct graph_state *ctx;
765 uint32_t tmp; 764 uint32_t tmp;
@@ -782,7 +781,7 @@ nv10_graph_unload_context(struct drm_device *dev)
782 781
783 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000); 782 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
784 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff; 783 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
785 tmp |= (pfifo->channels - 1) << 24; 784 tmp |= 31 << 24;
786 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp); 785 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
787 return 0; 786 return 0;
788} 787}
@@ -822,12 +821,12 @@ struct nouveau_channel *
822nv10_graph_channel(struct drm_device *dev) 821nv10_graph_channel(struct drm_device *dev)
823{ 822{
824 struct drm_nouveau_private *dev_priv = dev->dev_private; 823 struct drm_nouveau_private *dev_priv = dev->dev_private;
825 int chid = dev_priv->engine.fifo.channels; 824 int chid = 31;
826 825
827 if (nv_rd32(dev, NV10_PGRAPH_CTX_CONTROL) & 0x00010000) 826 if (nv_rd32(dev, NV10_PGRAPH_CTX_CONTROL) & 0x00010000)
828 chid = nv_rd32(dev, NV10_PGRAPH_CTX_USER) >> 24; 827 chid = nv_rd32(dev, NV10_PGRAPH_CTX_USER) >> 24;
829 828
830 if (chid >= dev_priv->engine.fifo.channels) 829 if (chid >= 31)
831 return NULL; 830 return NULL;
832 831
833 return dev_priv->channels.ptr[chid]; 832 return dev_priv->channels.ptr[chid];
@@ -948,7 +947,7 @@ nv10_graph_init(struct drm_device *dev, int engine)
948 nv_wr32(dev, NV10_PGRAPH_STATE, 0xFFFFFFFF); 947 nv_wr32(dev, NV10_PGRAPH_STATE, 0xFFFFFFFF);
949 948
950 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff; 949 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
951 tmp |= (dev_priv->engine.fifo.channels - 1) << 24; 950 tmp |= 31 << 24;
952 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp); 951 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
953 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 952 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
954 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); 953 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2, 0x08000000);
@@ -1153,10 +1152,6 @@ nv10_graph_create(struct drm_device *dev)
1153 NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base); 1152 NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
1154 nouveau_irq_register(dev, 12, nv10_graph_isr); 1153 nouveau_irq_register(dev, 12, nv10_graph_isr);
1155 1154
1156 /* nvsw */
1157 NVOBJ_CLASS(dev, 0x506e, SW);
1158 NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
1159
1160 NVOBJ_CLASS(dev, 0x0030, GR); /* null */ 1155 NVOBJ_CLASS(dev, 0x0030, GR); /* null */
1161 NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */ 1156 NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
1162 NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */ 1157 NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */