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path: root/drivers/gpu/drm/nouveau/nv10_fifo.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv10_fifo.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv10_fifo.c272
1 files changed, 85 insertions, 187 deletions
diff --git a/drivers/gpu/drm/nouveau/nv10_fifo.c b/drivers/gpu/drm/nouveau/nv10_fifo.c
index 476451c6f961..f1fe7d758241 100644
--- a/drivers/gpu/drm/nouveau/nv10_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv10_fifo.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2007 Ben Skeggs. 2 * Copyright (C) 2012 Ben Skeggs.
3 * All Rights Reserved. 3 * All Rights Reserved.
4 * 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining 5 * Permission is hereby granted, free of charge, to any person obtaining
@@ -27,214 +27,112 @@
27#include "drmP.h" 27#include "drmP.h"
28#include "drm.h" 28#include "drm.h"
29#include "nouveau_drv.h" 29#include "nouveau_drv.h"
30#include "nouveau_fifo.h"
31#include "nouveau_util.h"
30#include "nouveau_ramht.h" 32#include "nouveau_ramht.h"
31 33
32#define NV10_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV10_RAMFC__SIZE)) 34static struct ramfc_desc {
33#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32) 35 unsigned bits:6;
34 36 unsigned ctxs:5;
35int 37 unsigned ctxp:8;
36nv10_fifo_create_context(struct nouveau_channel *chan) 38 unsigned regs:5;
39 unsigned regp;
40} nv10_ramfc[] = {
41 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
42 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
43 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
44 { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
45 { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
46 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE },
47 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
48 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE },
49 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 },
50 {}
51};
52
53struct nv10_fifo_priv {
54 struct nouveau_fifo_priv base;
55 struct ramfc_desc *ramfc_desc;
56};
57
58struct nv10_fifo_chan {
59 struct nouveau_fifo_chan base;
60 struct nouveau_gpuobj *ramfc;
61};
62
63static int
64nv10_fifo_context_new(struct nouveau_channel *chan, int engine)
37{ 65{
38 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
39 struct drm_device *dev = chan->dev; 66 struct drm_device *dev = chan->dev;
40 uint32_t fc = NV10_RAMFC(chan->id); 67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 struct nv10_fifo_priv *priv = nv_engine(dev, engine);
69 struct nv10_fifo_chan *fctx;
70 unsigned long flags;
41 int ret; 71 int ret;
42 72
43 ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0, 73 fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
44 NV10_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | 74 if (!fctx)
45 NVOBJ_FLAG_ZERO_FREE, &chan->ramfc); 75 return -ENOMEM;
46 if (ret)
47 return ret;
48 76
77 /* map channel control registers */
49 chan->user = ioremap(pci_resource_start(dev->pdev, 0) + 78 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
50 NV03_USER(chan->id), PAGE_SIZE); 79 NV03_USER(chan->id), PAGE_SIZE);
51 if (!chan->user) 80 if (!chan->user) {
52 return -ENOMEM; 81 ret = -ENOMEM;
82 goto error;
83 }
53 84
54 /* Fill entries that are seen filled in dumps of nvidia driver just 85 /* initialise default fifo context */
55 * after channel's is put into DMA mode 86 ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramfc->pinst +
56 */ 87 chan->id * 32, ~0, 32,
57 nv_wi32(dev, fc + 0, chan->pushbuf_base); 88 NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
58 nv_wi32(dev, fc + 4, chan->pushbuf_base); 89 if (ret)
59 nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4); 90 goto error;
60 nv_wi32(dev, fc + 20, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | 91
61 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | 92 nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base);
62 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | 93 nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base);
94 nv_wo32(fctx->ramfc, 0x08, 0x00000000);
95 nv_wo32(fctx->ramfc, 0x0c, chan->pushbuf->pinst >> 4);
96 nv_wo32(fctx->ramfc, 0x10, 0x00000000);
97 nv_wo32(fctx->ramfc, 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
98 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
63#ifdef __BIG_ENDIAN 99#ifdef __BIG_ENDIAN
64 NV_PFIFO_CACHE1_BIG_ENDIAN | 100 NV_PFIFO_CACHE1_BIG_ENDIAN |
65#endif 101#endif
66 0); 102 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
67 103 nv_wo32(fctx->ramfc, 0x18, 0x00000000);
68 /* enable the fifo dma operation */ 104 nv_wo32(fctx->ramfc, 0x1c, 0x00000000);
69 nv_wr32(dev, NV04_PFIFO_MODE,
70 nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
71 return 0;
72}
73
74static void
75nv10_fifo_do_load_context(struct drm_device *dev, int chid)
76{
77 struct drm_nouveau_private *dev_priv = dev->dev_private;
78 uint32_t fc = NV10_RAMFC(chid), tmp;
79
80 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
81 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
82 nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));
83 105
84 tmp = nv_ri32(dev, fc + 12); 106 /* enable dma mode on the channel */
85 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF); 107 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
86 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16); 108 nv_mask(dev, NV04_PFIFO_MODE, (1 << chan->id), (1 << chan->id));
109 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
87 110
88 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 16)); 111error:
89 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 20)); 112 if (ret)
90 nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 24)); 113 priv->base.base.context_del(chan, engine);
91 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 28)); 114 return ret;
92
93 if (dev_priv->chipset < 0x17)
94 goto out;
95
96 nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 32));
97 tmp = nv_ri32(dev, fc + 36);
98 nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
99 nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 40));
100 nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 44));
101 nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 48));
102
103out:
104 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
105 nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
106}
107
108int
109nv10_fifo_load_context(struct nouveau_channel *chan)
110{
111 struct drm_device *dev = chan->dev;
112 uint32_t tmp;
113
114 nv10_fifo_do_load_context(dev, chan->id);
115
116 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
117 NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
118 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
119
120 /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
121 tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
122 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
123
124 return 0;
125} 115}
126 116
127int 117int
128nv10_fifo_unload_context(struct drm_device *dev) 118nv10_fifo_create(struct drm_device *dev)
129{ 119{
130 struct drm_nouveau_private *dev_priv = dev->dev_private; 120 struct drm_nouveau_private *dev_priv = dev->dev_private;
131 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; 121 struct nv10_fifo_priv *priv;
132 uint32_t fc, tmp;
133 int chid;
134
135 chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 0x1f;
136 if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
137 return 0;
138 fc = NV10_RAMFC(chid);
139 122
140 nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT)); 123 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
141 nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET)); 124 if (!priv)
142 nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT)); 125 return -ENOMEM;
143 tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
144 tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
145 nv_wi32(dev, fc + 12, tmp);
146 nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
147 nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
148 nv_wi32(dev, fc + 24, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
149 nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
150
151 if (dev_priv->chipset < 0x17)
152 goto out;
153
154 nv_wi32(dev, fc + 32, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
155 tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
156 nv_wi32(dev, fc + 36, tmp);
157 nv_wi32(dev, fc + 40, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
158 nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
159 nv_wi32(dev, fc + 48, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
160
161out:
162 nv10_fifo_do_load_context(dev, pfifo->channels - 1);
163 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
164 return 0;
165}
166
167static void
168nv10_fifo_init_reset(struct drm_device *dev)
169{
170 nv_wr32(dev, NV03_PMC_ENABLE,
171 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
172 nv_wr32(dev, NV03_PMC_ENABLE,
173 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO);
174
175 nv_wr32(dev, 0x003224, 0x000f0078);
176 nv_wr32(dev, 0x002044, 0x0101ffff);
177 nv_wr32(dev, 0x002040, 0x000000ff);
178 nv_wr32(dev, 0x002500, 0x00000000);
179 nv_wr32(dev, 0x003000, 0x00000000);
180 nv_wr32(dev, 0x003050, 0x00000000);
181
182 nv_wr32(dev, 0x003258, 0x00000000);
183 nv_wr32(dev, 0x003210, 0x00000000);
184 nv_wr32(dev, 0x003270, 0x00000000);
185}
186
187static void
188nv10_fifo_init_ramxx(struct drm_device *dev)
189{
190 struct drm_nouveau_private *dev_priv = dev->dev_private;
191 126
192 nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | 127 priv->base.base.destroy = nv04_fifo_destroy;
193 ((dev_priv->ramht->bits - 9) << 16) | 128 priv->base.base.init = nv04_fifo_init;
194 (dev_priv->ramht->gpuobj->pinst >> 8)); 129 priv->base.base.fini = nv04_fifo_fini;
195 nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8); 130 priv->base.base.context_new = nv10_fifo_context_new;
131 priv->base.base.context_del = nv04_fifo_context_del;
132 priv->base.channels = 31;
133 priv->ramfc_desc = nv10_ramfc;
134 dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;
196 135
197 if (dev_priv->chipset < 0x17) {
198 nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);
199 } else {
200 nv_wr32(dev, NV03_PFIFO_RAMFC, (dev_priv->ramfc->pinst >> 8) |
201 (1 << 16) /* 64 Bytes entry*/);
202 /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
203 }
204}
205
206static void
207nv10_fifo_init_intr(struct drm_device *dev)
208{
209 nouveau_irq_register(dev, 8, nv04_fifo_isr); 136 nouveau_irq_register(dev, 8, nv04_fifo_isr);
210 nv_wr32(dev, 0x002100, 0xffffffff);
211 nv_wr32(dev, 0x002140, 0xffffffff);
212}
213
214int
215nv10_fifo_init(struct drm_device *dev)
216{
217 struct drm_nouveau_private *dev_priv = dev->dev_private;
218 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
219 int i;
220
221 nv10_fifo_init_reset(dev);
222 nv10_fifo_init_ramxx(dev);
223
224 nv10_fifo_do_load_context(dev, pfifo->channels - 1);
225 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
226
227 nv10_fifo_init_intr(dev);
228 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
229 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
230 nv_wr32(dev, NV03_PFIFO_CACHES, 1);
231
232 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
233 if (dev_priv->channels.ptr[i]) {
234 uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
235 nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
236 }
237 }
238
239 return 0; 137 return 0;
240} 138}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 03:40:32 -0500