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path: root/drivers/gpu/drm/nouveau/nv10_fb.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv10_fb.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv10_fb.c44
1 files changed, 44 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv10_fb.c b/drivers/gpu/drm/nouveau/nv10_fb.c
new file mode 100644
index 000000000000..cc5cda44e501
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv10_fb.c
@@ -0,0 +1,44 @@
1#include "drmP.h"
2#include "drm.h"
3#include "nouveau_drv.h"
4#include "nouveau_drm.h"
5
6void
7nv10_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
8 uint32_t size, uint32_t pitch)
9{
10 struct drm_nouveau_private *dev_priv = dev->dev_private;
11 uint32_t limit = max(1u, addr + size) - 1;
12
13 if (pitch) {
14 if (dev_priv->card_type >= NV_20)
15 addr |= 1;
16 else
17 addr |= 1 << 31;
18 }
19
20 nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
21 nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
22 nv_wr32(dev, NV10_PFB_TILE(i), addr);
23}
24
25int
26nv10_fb_init(struct drm_device *dev)
27{
28 struct drm_nouveau_private *dev_priv = dev->dev_private;
29 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
30 int i;
31
32 pfb->num_tiles = NV10_PFB_TILE__SIZE;
33
34 /* Turn all the tiling regions off. */
35 for (i = 0; i < pfb->num_tiles; i++)
36 pfb->set_region_tiling(dev, i, 0, 0, 0);
37
38 return 0;
39}
40
41void
42nv10_fb_takedown(struct drm_device *dev)
43{
44}