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path: root/drivers/gpu/drm/nouveau/nouveau_state.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_state.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c212
1 files changed, 92 insertions, 120 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 915fbce89595..38ea662568c1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -65,14 +65,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
65 engine->timer.takedown = nv04_timer_takedown; 65 engine->timer.takedown = nv04_timer_takedown;
66 engine->fb.init = nv04_fb_init; 66 engine->fb.init = nv04_fb_init;
67 engine->fb.takedown = nv04_fb_takedown; 67 engine->fb.takedown = nv04_fb_takedown;
68 engine->graph.init = nv04_graph_init;
69 engine->graph.takedown = nv04_graph_takedown;
70 engine->graph.fifo_access = nv04_graph_fifo_access;
71 engine->graph.channel = nv04_graph_channel;
72 engine->graph.create_context = nv04_graph_create_context;
73 engine->graph.destroy_context = nv04_graph_destroy_context;
74 engine->graph.load_context = nv04_graph_load_context;
75 engine->graph.unload_context = nv04_graph_unload_context;
76 engine->fifo.channels = 16; 68 engine->fifo.channels = 16;
77 engine->fifo.init = nv04_fifo_init; 69 engine->fifo.init = nv04_fifo_init;
78 engine->fifo.takedown = nv04_fifo_fini; 70 engine->fifo.takedown = nv04_fifo_fini;
@@ -98,8 +90,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
98 engine->pm.clock_get = nv04_pm_clock_get; 90 engine->pm.clock_get = nv04_pm_clock_get;
99 engine->pm.clock_pre = nv04_pm_clock_pre; 91 engine->pm.clock_pre = nv04_pm_clock_pre;
100 engine->pm.clock_set = nv04_pm_clock_set; 92 engine->pm.clock_set = nv04_pm_clock_set;
101 engine->crypt.init = nouveau_stub_init;
102 engine->crypt.takedown = nouveau_stub_takedown;
103 engine->vram.init = nouveau_mem_detect; 93 engine->vram.init = nouveau_mem_detect;
104 engine->vram.flags_valid = nouveau_mem_flags_valid; 94 engine->vram.flags_valid = nouveau_mem_flags_valid;
105 break; 95 break;
@@ -123,15 +113,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
123 engine->fb.init_tile_region = nv10_fb_init_tile_region; 113 engine->fb.init_tile_region = nv10_fb_init_tile_region;
124 engine->fb.set_tile_region = nv10_fb_set_tile_region; 114 engine->fb.set_tile_region = nv10_fb_set_tile_region;
125 engine->fb.free_tile_region = nv10_fb_free_tile_region; 115 engine->fb.free_tile_region = nv10_fb_free_tile_region;
126 engine->graph.init = nv10_graph_init;
127 engine->graph.takedown = nv10_graph_takedown;
128 engine->graph.channel = nv10_graph_channel;
129 engine->graph.create_context = nv10_graph_create_context;
130 engine->graph.destroy_context = nv10_graph_destroy_context;
131 engine->graph.fifo_access = nv04_graph_fifo_access;
132 engine->graph.load_context = nv10_graph_load_context;
133 engine->graph.unload_context = nv10_graph_unload_context;
134 engine->graph.set_tile_region = nv10_graph_set_tile_region;
135 engine->fifo.channels = 32; 116 engine->fifo.channels = 32;
136 engine->fifo.init = nv10_fifo_init; 117 engine->fifo.init = nv10_fifo_init;
137 engine->fifo.takedown = nv04_fifo_fini; 118 engine->fifo.takedown = nv04_fifo_fini;
@@ -157,8 +138,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
157 engine->pm.clock_get = nv04_pm_clock_get; 138 engine->pm.clock_get = nv04_pm_clock_get;
158 engine->pm.clock_pre = nv04_pm_clock_pre; 139 engine->pm.clock_pre = nv04_pm_clock_pre;
159 engine->pm.clock_set = nv04_pm_clock_set; 140 engine->pm.clock_set = nv04_pm_clock_set;
160 engine->crypt.init = nouveau_stub_init;
161 engine->crypt.takedown = nouveau_stub_takedown;
162 engine->vram.init = nouveau_mem_detect; 141 engine->vram.init = nouveau_mem_detect;
163 engine->vram.flags_valid = nouveau_mem_flags_valid; 142 engine->vram.flags_valid = nouveau_mem_flags_valid;
164 break; 143 break;
@@ -182,15 +161,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
182 engine->fb.init_tile_region = nv10_fb_init_tile_region; 161 engine->fb.init_tile_region = nv10_fb_init_tile_region;
183 engine->fb.set_tile_region = nv10_fb_set_tile_region; 162 engine->fb.set_tile_region = nv10_fb_set_tile_region;
184 engine->fb.free_tile_region = nv10_fb_free_tile_region; 163 engine->fb.free_tile_region = nv10_fb_free_tile_region;
185 engine->graph.init = nv20_graph_init;
186 engine->graph.takedown = nv20_graph_takedown;
187 engine->graph.channel = nv10_graph_channel;
188 engine->graph.create_context = nv20_graph_create_context;
189 engine->graph.destroy_context = nv20_graph_destroy_context;
190 engine->graph.fifo_access = nv04_graph_fifo_access;
191 engine->graph.load_context = nv20_graph_load_context;
192 engine->graph.unload_context = nv20_graph_unload_context;
193 engine->graph.set_tile_region = nv20_graph_set_tile_region;
194 engine->fifo.channels = 32; 164 engine->fifo.channels = 32;
195 engine->fifo.init = nv10_fifo_init; 165 engine->fifo.init = nv10_fifo_init;
196 engine->fifo.takedown = nv04_fifo_fini; 166 engine->fifo.takedown = nv04_fifo_fini;
@@ -216,8 +186,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
216 engine->pm.clock_get = nv04_pm_clock_get; 186 engine->pm.clock_get = nv04_pm_clock_get;
217 engine->pm.clock_pre = nv04_pm_clock_pre; 187 engine->pm.clock_pre = nv04_pm_clock_pre;
218 engine->pm.clock_set = nv04_pm_clock_set; 188 engine->pm.clock_set = nv04_pm_clock_set;
219 engine->crypt.init = nouveau_stub_init;
220 engine->crypt.takedown = nouveau_stub_takedown;
221 engine->vram.init = nouveau_mem_detect; 189 engine->vram.init = nouveau_mem_detect;
222 engine->vram.flags_valid = nouveau_mem_flags_valid; 190 engine->vram.flags_valid = nouveau_mem_flags_valid;
223 break; 191 break;
@@ -241,15 +209,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
241 engine->fb.init_tile_region = nv30_fb_init_tile_region; 209 engine->fb.init_tile_region = nv30_fb_init_tile_region;
242 engine->fb.set_tile_region = nv10_fb_set_tile_region; 210 engine->fb.set_tile_region = nv10_fb_set_tile_region;
243 engine->fb.free_tile_region = nv30_fb_free_tile_region; 211 engine->fb.free_tile_region = nv30_fb_free_tile_region;
244 engine->graph.init = nv30_graph_init;
245 engine->graph.takedown = nv20_graph_takedown;
246 engine->graph.fifo_access = nv04_graph_fifo_access;
247 engine->graph.channel = nv10_graph_channel;
248 engine->graph.create_context = nv20_graph_create_context;
249 engine->graph.destroy_context = nv20_graph_destroy_context;
250 engine->graph.load_context = nv20_graph_load_context;
251 engine->graph.unload_context = nv20_graph_unload_context;
252 engine->graph.set_tile_region = nv20_graph_set_tile_region;
253 engine->fifo.channels = 32; 212 engine->fifo.channels = 32;
254 engine->fifo.init = nv10_fifo_init; 213 engine->fifo.init = nv10_fifo_init;
255 engine->fifo.takedown = nv04_fifo_fini; 214 engine->fifo.takedown = nv04_fifo_fini;
@@ -277,8 +236,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
277 engine->pm.clock_set = nv04_pm_clock_set; 236 engine->pm.clock_set = nv04_pm_clock_set;
278 engine->pm.voltage_get = nouveau_voltage_gpio_get; 237 engine->pm.voltage_get = nouveau_voltage_gpio_get;
279 engine->pm.voltage_set = nouveau_voltage_gpio_set; 238 engine->pm.voltage_set = nouveau_voltage_gpio_set;
280 engine->crypt.init = nouveau_stub_init;
281 engine->crypt.takedown = nouveau_stub_takedown;
282 engine->vram.init = nouveau_mem_detect; 239 engine->vram.init = nouveau_mem_detect;
283 engine->vram.flags_valid = nouveau_mem_flags_valid; 240 engine->vram.flags_valid = nouveau_mem_flags_valid;
284 break; 241 break;
@@ -303,15 +260,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
303 engine->fb.init_tile_region = nv30_fb_init_tile_region; 260 engine->fb.init_tile_region = nv30_fb_init_tile_region;
304 engine->fb.set_tile_region = nv40_fb_set_tile_region; 261 engine->fb.set_tile_region = nv40_fb_set_tile_region;
305 engine->fb.free_tile_region = nv30_fb_free_tile_region; 262 engine->fb.free_tile_region = nv30_fb_free_tile_region;
306 engine->graph.init = nv40_graph_init;
307 engine->graph.takedown = nv40_graph_takedown;
308 engine->graph.fifo_access = nv04_graph_fifo_access;
309 engine->graph.channel = nv40_graph_channel;
310 engine->graph.create_context = nv40_graph_create_context;
311 engine->graph.destroy_context = nv40_graph_destroy_context;
312 engine->graph.load_context = nv40_graph_load_context;
313 engine->graph.unload_context = nv40_graph_unload_context;
314 engine->graph.set_tile_region = nv40_graph_set_tile_region;
315 engine->fifo.channels = 32; 263 engine->fifo.channels = 32;
316 engine->fifo.init = nv40_fifo_init; 264 engine->fifo.init = nv40_fifo_init;
317 engine->fifo.takedown = nv04_fifo_fini; 265 engine->fifo.takedown = nv04_fifo_fini;
@@ -340,8 +288,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
340 engine->pm.voltage_get = nouveau_voltage_gpio_get; 288 engine->pm.voltage_get = nouveau_voltage_gpio_get;
341 engine->pm.voltage_set = nouveau_voltage_gpio_set; 289 engine->pm.voltage_set = nouveau_voltage_gpio_set;
342 engine->pm.temp_get = nv40_temp_get; 290 engine->pm.temp_get = nv40_temp_get;
343 engine->crypt.init = nouveau_stub_init;
344 engine->crypt.takedown = nouveau_stub_takedown;
345 engine->vram.init = nouveau_mem_detect; 291 engine->vram.init = nouveau_mem_detect;
346 engine->vram.flags_valid = nouveau_mem_flags_valid; 292 engine->vram.flags_valid = nouveau_mem_flags_valid;
347 break; 293 break;
@@ -368,19 +314,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
368 engine->timer.takedown = nv04_timer_takedown; 314 engine->timer.takedown = nv04_timer_takedown;
369 engine->fb.init = nv50_fb_init; 315 engine->fb.init = nv50_fb_init;
370 engine->fb.takedown = nv50_fb_takedown; 316 engine->fb.takedown = nv50_fb_takedown;
371 engine->graph.init = nv50_graph_init;
372 engine->graph.takedown = nv50_graph_takedown;
373 engine->graph.fifo_access = nv50_graph_fifo_access;
374 engine->graph.channel = nv50_graph_channel;
375 engine->graph.create_context = nv50_graph_create_context;
376 engine->graph.destroy_context = nv50_graph_destroy_context;
377 engine->graph.load_context = nv50_graph_load_context;
378 engine->graph.unload_context = nv50_graph_unload_context;
379 if (dev_priv->chipset == 0x50 ||
380 dev_priv->chipset == 0xac)
381 engine->graph.tlb_flush = nv50_graph_tlb_flush;
382 else
383 engine->graph.tlb_flush = nv84_graph_tlb_flush;
384 engine->fifo.channels = 128; 317 engine->fifo.channels = 128;
385 engine->fifo.init = nv50_fifo_init; 318 engine->fifo.init = nv50_fifo_init;
386 engine->fifo.takedown = nv50_fifo_takedown; 319 engine->fifo.takedown = nv50_fifo_takedown;
@@ -432,24 +365,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
432 engine->pm.temp_get = nv84_temp_get; 365 engine->pm.temp_get = nv84_temp_get;
433 else 366 else
434 engine->pm.temp_get = nv40_temp_get; 367 engine->pm.temp_get = nv40_temp_get;
435 switch (dev_priv->chipset) {
436 case 0x84:
437 case 0x86:
438 case 0x92:
439 case 0x94:
440 case 0x96:
441 case 0xa0:
442 engine->crypt.init = nv84_crypt_init;
443 engine->crypt.takedown = nv84_crypt_fini;
444 engine->crypt.create_context = nv84_crypt_create_context;
445 engine->crypt.destroy_context = nv84_crypt_destroy_context;
446 engine->crypt.tlb_flush = nv84_crypt_tlb_flush;
447 break;
448 default:
449 engine->crypt.init = nouveau_stub_init;
450 engine->crypt.takedown = nouveau_stub_takedown;
451 break;
452 }
453 engine->vram.init = nv50_vram_init; 368 engine->vram.init = nv50_vram_init;
454 engine->vram.get = nv50_vram_new; 369 engine->vram.get = nv50_vram_new;
455 engine->vram.put = nv50_vram_del; 370 engine->vram.put = nv50_vram_del;
@@ -472,14 +387,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
472 engine->timer.takedown = nv04_timer_takedown; 387 engine->timer.takedown = nv04_timer_takedown;
473 engine->fb.init = nvc0_fb_init; 388 engine->fb.init = nvc0_fb_init;
474 engine->fb.takedown = nvc0_fb_takedown; 389 engine->fb.takedown = nvc0_fb_takedown;
475 engine->graph.init = nvc0_graph_init;
476 engine->graph.takedown = nvc0_graph_takedown;
477 engine->graph.fifo_access = nvc0_graph_fifo_access;
478 engine->graph.channel = nvc0_graph_channel;
479 engine->graph.create_context = nvc0_graph_create_context;
480 engine->graph.destroy_context = nvc0_graph_destroy_context;
481 engine->graph.load_context = nvc0_graph_load_context;
482 engine->graph.unload_context = nvc0_graph_unload_context;
483 engine->fifo.channels = 128; 390 engine->fifo.channels = 128;
484 engine->fifo.init = nvc0_fifo_init; 391 engine->fifo.init = nvc0_fifo_init;
485 engine->fifo.takedown = nvc0_fifo_takedown; 392 engine->fifo.takedown = nvc0_fifo_takedown;
@@ -503,8 +410,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
503 engine->gpio.irq_register = nv50_gpio_irq_register; 410 engine->gpio.irq_register = nv50_gpio_irq_register;
504 engine->gpio.irq_unregister = nv50_gpio_irq_unregister; 411 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
505 engine->gpio.irq_enable = nv50_gpio_irq_enable; 412 engine->gpio.irq_enable = nv50_gpio_irq_enable;
506 engine->crypt.init = nouveau_stub_init;
507 engine->crypt.takedown = nouveau_stub_takedown;
508 engine->vram.init = nvc0_vram_init; 413 engine->vram.init = nvc0_vram_init;
509 engine->vram.get = nvc0_vram_new; 414 engine->vram.get = nvc0_vram_new;
510 engine->vram.put = nv50_vram_del; 415 engine->vram.put = nv50_vram_del;
@@ -593,7 +498,7 @@ nouveau_card_init(struct drm_device *dev)
593{ 498{
594 struct drm_nouveau_private *dev_priv = dev->dev_private; 499 struct drm_nouveau_private *dev_priv = dev->dev_private;
595 struct nouveau_engine *engine; 500 struct nouveau_engine *engine;
596 int ret; 501 int ret, e = 0;
597 502
598 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); 503 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
599 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state, 504 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
@@ -658,23 +563,80 @@ nouveau_card_init(struct drm_device *dev)
658 if (ret) 563 if (ret)
659 goto out_timer; 564 goto out_timer;
660 565
661 if (nouveau_noaccel) 566 switch (dev_priv->card_type) {
662 engine->graph.accel_blocked = true; 567 case NV_04:
663 else { 568 nv04_graph_create(dev);
664 /* PGRAPH */ 569 break;
665 ret = engine->graph.init(dev); 570 case NV_10:
666 if (ret) 571 nv10_graph_create(dev);
667 goto out_fb; 572 break;
573 case NV_20:
574 case NV_30:
575 nv20_graph_create(dev);
576 break;
577 case NV_40:
578 nv40_graph_create(dev);
579 break;
580 case NV_50:
581 nv50_graph_create(dev);
582 break;
583 case NV_C0:
584 nvc0_graph_create(dev);
585 break;
586 default:
587 break;
588 }
668 589
669 /* PCRYPT */ 590 switch (dev_priv->chipset) {
670 ret = engine->crypt.init(dev); 591 case 0x84:
671 if (ret) 592 case 0x86:
672 goto out_graph; 593 case 0x92:
594 case 0x94:
595 case 0x96:
596 case 0xa0:
597 nv84_crypt_create(dev);
598 break;
599 }
600
601 switch (dev_priv->card_type) {
602 case NV_50:
603 switch (dev_priv->chipset) {
604 case 0xa3:
605 case 0xa5:
606 case 0xa8:
607 case 0xaf:
608 nva3_copy_create(dev);
609 break;
610 }
611 break;
612 case NV_C0:
613 nvc0_copy_create(dev, 0);
614 nvc0_copy_create(dev, 1);
615 break;
616 default:
617 break;
618 }
619
620 if (dev_priv->card_type == NV_40)
621 nv40_mpeg_create(dev);
622 else
623 if (dev_priv->card_type == NV_50 &&
624 (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
625 nv50_mpeg_create(dev);
626
627 if (!nouveau_noaccel) {
628 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
629 if (dev_priv->eng[e]) {
630 ret = dev_priv->eng[e]->init(dev, e);
631 if (ret)
632 goto out_engine;
633 }
634 }
673 635
674 /* PFIFO */ 636 /* PFIFO */
675 ret = engine->fifo.init(dev); 637 ret = engine->fifo.init(dev);
676 if (ret) 638 if (ret)
677 goto out_crypt; 639 goto out_engine;
678 } 640 }
679 641
680 ret = engine->display.create(dev); 642 ret = engine->display.create(dev);
@@ -691,7 +653,7 @@ nouveau_card_init(struct drm_device *dev)
691 653
692 /* what about PVIDEO/PCRTC/PRAMDAC etc? */ 654 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
693 655
694 if (!engine->graph.accel_blocked) { 656 if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
695 ret = nouveau_fence_init(dev); 657 ret = nouveau_fence_init(dev);
696 if (ret) 658 if (ret)
697 goto out_irq; 659 goto out_irq;
@@ -715,13 +677,16 @@ out_vblank:
715out_fifo: 677out_fifo:
716 if (!nouveau_noaccel) 678 if (!nouveau_noaccel)
717 engine->fifo.takedown(dev); 679 engine->fifo.takedown(dev);
718out_crypt: 680out_engine:
719 if (!nouveau_noaccel) 681 if (!nouveau_noaccel) {
720 engine->crypt.takedown(dev); 682 for (e = e - 1; e >= 0; e--) {
721out_graph: 683 if (!dev_priv->eng[e])
722 if (!nouveau_noaccel) 684 continue;
723 engine->graph.takedown(dev); 685 dev_priv->eng[e]->fini(dev, e);
724out_fb: 686 dev_priv->eng[e]->destroy(dev,e );
687 }
688 }
689
725 engine->fb.takedown(dev); 690 engine->fb.takedown(dev);
726out_timer: 691out_timer:
727 engine->timer.takedown(dev); 692 engine->timer.takedown(dev);
@@ -751,16 +716,21 @@ static void nouveau_card_takedown(struct drm_device *dev)
751{ 716{
752 struct drm_nouveau_private *dev_priv = dev->dev_private; 717 struct drm_nouveau_private *dev_priv = dev->dev_private;
753 struct nouveau_engine *engine = &dev_priv->engine; 718 struct nouveau_engine *engine = &dev_priv->engine;
719 int e;
754 720
755 if (!engine->graph.accel_blocked) { 721 if (dev_priv->channel) {
756 nouveau_fence_fini(dev); 722 nouveau_fence_fini(dev);
757 nouveau_channel_put_unlocked(&dev_priv->channel); 723 nouveau_channel_put_unlocked(&dev_priv->channel);
758 } 724 }
759 725
760 if (!nouveau_noaccel) { 726 if (!nouveau_noaccel) {
761 engine->fifo.takedown(dev); 727 engine->fifo.takedown(dev);
762 engine->crypt.takedown(dev); 728 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
763 engine->graph.takedown(dev); 729 if (dev_priv->eng[e]) {
730 dev_priv->eng[e]->fini(dev, e);
731 dev_priv->eng[e]->destroy(dev,e );
732 }
733 }
764 } 734 }
765 engine->fb.takedown(dev); 735 engine->fb.takedown(dev);
766 engine->timer.takedown(dev); 736 engine->timer.takedown(dev);
@@ -866,7 +836,7 @@ static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
866#ifdef CONFIG_X86 836#ifdef CONFIG_X86
867 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 837 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
868#endif 838#endif
869 839
870 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary); 840 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
871 return 0; 841 return 0;
872} 842}
@@ -918,11 +888,13 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
918 888
919 /* Time to determine the card architecture */ 889 /* Time to determine the card architecture */
920 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); 890 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
891 dev_priv->stepping = 0; /* XXX: add stepping for pre-NV10? */
921 892
922 /* We're dealing with >=NV10 */ 893 /* We're dealing with >=NV10 */
923 if ((reg0 & 0x0f000000) > 0) { 894 if ((reg0 & 0x0f000000) > 0) {
924 /* Bit 27-20 contain the architecture in hex */ 895 /* Bit 27-20 contain the architecture in hex */
925 dev_priv->chipset = (reg0 & 0xff00000) >> 20; 896 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
897 dev_priv->stepping = (reg0 & 0xff);
926 /* NV04 or NV05 */ 898 /* NV04 or NV05 */
927 } else if ((reg0 & 0xff00fff0) == 0x20004000) { 899 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
928 if (reg0 & 0x00f00000) 900 if (reg0 & 0x00f00000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-09 16:22:25 -0400