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path: root/drivers/gpu/drm/nouveau/nouveau_state.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_state.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c232
1 files changed, 118 insertions, 114 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index f80c5e0762ff..9c144fb8bbba 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -87,7 +87,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
87 engine->pm.clocks_get = nv04_pm_clocks_get; 87 engine->pm.clocks_get = nv04_pm_clocks_get;
88 engine->pm.clocks_pre = nv04_pm_clocks_pre; 88 engine->pm.clocks_pre = nv04_pm_clocks_pre;
89 engine->pm.clocks_set = nv04_pm_clocks_set; 89 engine->pm.clocks_set = nv04_pm_clocks_set;
90 engine->vram.init = nouveau_mem_detect; 90 engine->vram.init = nv04_fb_vram_init;
91 engine->vram.takedown = nouveau_stub_takedown; 91 engine->vram.takedown = nouveau_stub_takedown;
92 engine->vram.flags_valid = nouveau_mem_flags_valid; 92 engine->vram.flags_valid = nouveau_mem_flags_valid;
93 break; 93 break;
@@ -134,7 +134,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
134 engine->pm.clocks_get = nv04_pm_clocks_get; 134 engine->pm.clocks_get = nv04_pm_clocks_get;
135 engine->pm.clocks_pre = nv04_pm_clocks_pre; 135 engine->pm.clocks_pre = nv04_pm_clocks_pre;
136 engine->pm.clocks_set = nv04_pm_clocks_set; 136 engine->pm.clocks_set = nv04_pm_clocks_set;
137 engine->vram.init = nouveau_mem_detect; 137 if (dev_priv->chipset == 0x1a ||
138 dev_priv->chipset == 0x1f)
139 engine->vram.init = nv1a_fb_vram_init;
140 else
141 engine->vram.init = nv10_fb_vram_init;
138 engine->vram.takedown = nouveau_stub_takedown; 142 engine->vram.takedown = nouveau_stub_takedown;
139 engine->vram.flags_valid = nouveau_mem_flags_valid; 143 engine->vram.flags_valid = nouveau_mem_flags_valid;
140 break; 144 break;
@@ -153,11 +157,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
153 engine->timer.init = nv04_timer_init; 157 engine->timer.init = nv04_timer_init;
154 engine->timer.read = nv04_timer_read; 158 engine->timer.read = nv04_timer_read;
155 engine->timer.takedown = nv04_timer_takedown; 159 engine->timer.takedown = nv04_timer_takedown;
156 engine->fb.init = nv10_fb_init; 160 engine->fb.init = nv20_fb_init;
157 engine->fb.takedown = nv10_fb_takedown; 161 engine->fb.takedown = nv20_fb_takedown;
158 engine->fb.init_tile_region = nv10_fb_init_tile_region; 162 engine->fb.init_tile_region = nv20_fb_init_tile_region;
159 engine->fb.set_tile_region = nv10_fb_set_tile_region; 163 engine->fb.set_tile_region = nv20_fb_set_tile_region;
160 engine->fb.free_tile_region = nv10_fb_free_tile_region; 164 engine->fb.free_tile_region = nv20_fb_free_tile_region;
161 engine->fifo.channels = 32; 165 engine->fifo.channels = 32;
162 engine->fifo.init = nv10_fifo_init; 166 engine->fifo.init = nv10_fifo_init;
163 engine->fifo.takedown = nv04_fifo_fini; 167 engine->fifo.takedown = nv04_fifo_fini;
@@ -181,7 +185,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
181 engine->pm.clocks_get = nv04_pm_clocks_get; 185 engine->pm.clocks_get = nv04_pm_clocks_get;
182 engine->pm.clocks_pre = nv04_pm_clocks_pre; 186 engine->pm.clocks_pre = nv04_pm_clocks_pre;
183 engine->pm.clocks_set = nv04_pm_clocks_set; 187 engine->pm.clocks_set = nv04_pm_clocks_set;
184 engine->vram.init = nouveau_mem_detect; 188 engine->vram.init = nv20_fb_vram_init;
185 engine->vram.takedown = nouveau_stub_takedown; 189 engine->vram.takedown = nouveau_stub_takedown;
186 engine->vram.flags_valid = nouveau_mem_flags_valid; 190 engine->vram.flags_valid = nouveau_mem_flags_valid;
187 break; 191 break;
@@ -230,7 +234,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
230 engine->pm.clocks_set = nv04_pm_clocks_set; 234 engine->pm.clocks_set = nv04_pm_clocks_set;
231 engine->pm.voltage_get = nouveau_voltage_gpio_get; 235 engine->pm.voltage_get = nouveau_voltage_gpio_get;
232 engine->pm.voltage_set = nouveau_voltage_gpio_set; 236 engine->pm.voltage_set = nouveau_voltage_gpio_set;
233 engine->vram.init = nouveau_mem_detect; 237 engine->vram.init = nv20_fb_vram_init;
234 engine->vram.takedown = nouveau_stub_takedown; 238 engine->vram.takedown = nouveau_stub_takedown;
235 engine->vram.flags_valid = nouveau_mem_flags_valid; 239 engine->vram.flags_valid = nouveau_mem_flags_valid;
236 break; 240 break;
@@ -286,7 +290,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
286 engine->pm.temp_get = nv40_temp_get; 290 engine->pm.temp_get = nv40_temp_get;
287 engine->pm.pwm_get = nv40_pm_pwm_get; 291 engine->pm.pwm_get = nv40_pm_pwm_get;
288 engine->pm.pwm_set = nv40_pm_pwm_set; 292 engine->pm.pwm_set = nv40_pm_pwm_set;
289 engine->vram.init = nouveau_mem_detect; 293 engine->vram.init = nv40_fb_vram_init;
290 engine->vram.takedown = nouveau_stub_takedown; 294 engine->vram.takedown = nouveau_stub_takedown;
291 engine->vram.flags_valid = nouveau_mem_flags_valid; 295 engine->vram.flags_valid = nouveau_mem_flags_valid;
292 break; 296 break;
@@ -588,47 +592,45 @@ nouveau_card_init(struct drm_device *dev)
588 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000); 592 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
589 } 593 }
590 594
591 nouveau_pm_init(dev); 595 /* PMC */
592 596 ret = engine->mc.init(dev);
593 ret = engine->vram.init(dev);
594 if (ret) 597 if (ret)
595 goto out_bios; 598 goto out_bios;
596 599
597 ret = nouveau_gpuobj_init(dev); 600 /* PTIMER */
601 ret = engine->timer.init(dev);
598 if (ret) 602 if (ret)
599 goto out_vram; 603 goto out_mc;
600 604
601 ret = engine->instmem.init(dev); 605 /* PFB */
606 ret = engine->fb.init(dev);
602 if (ret) 607 if (ret)
603 goto out_gpuobj; 608 goto out_timer;
604 609
605 ret = nouveau_mem_vram_init(dev); 610 ret = engine->vram.init(dev);
606 if (ret) 611 if (ret)
607 goto out_instmem; 612 goto out_fb;
608 613
609 ret = nouveau_mem_gart_init(dev); 614 /* PGPIO */
615 ret = nouveau_gpio_create(dev);
610 if (ret) 616 if (ret)
611 goto out_ttmvram; 617 goto out_vram;
612 618
613 /* PMC */ 619 ret = nouveau_gpuobj_init(dev);
614 ret = engine->mc.init(dev);
615 if (ret) 620 if (ret)
616 goto out_gart; 621 goto out_gpio;
617 622
618 /* PGPIO */ 623 ret = engine->instmem.init(dev);
619 ret = nouveau_gpio_create(dev);
620 if (ret) 624 if (ret)
621 goto out_mc; 625 goto out_gpuobj;
622 626
623 /* PTIMER */ 627 ret = nouveau_mem_vram_init(dev);
624 ret = engine->timer.init(dev);
625 if (ret) 628 if (ret)
626 goto out_gpio; 629 goto out_instmem;
627 630
628 /* PFB */ 631 ret = nouveau_mem_gart_init(dev);
629 ret = engine->fb.init(dev);
630 if (ret) 632 if (ret)
631 goto out_timer; 633 goto out_ttmvram;
632 634
633 if (!dev_priv->noaccel) { 635 if (!dev_priv->noaccel) {
634 switch (dev_priv->card_type) { 636 switch (dev_priv->card_type) {
@@ -734,11 +736,12 @@ nouveau_card_init(struct drm_device *dev)
734 goto out_irq; 736 goto out_irq;
735 737
736 nouveau_backlight_init(dev); 738 nouveau_backlight_init(dev);
739 nouveau_pm_init(dev);
737 740
738 if (dev_priv->eng[NVOBJ_ENGINE_GR]) { 741 if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
739 ret = nouveau_fence_init(dev); 742 ret = nouveau_fence_init(dev);
740 if (ret) 743 if (ret)
741 goto out_disp; 744 goto out_pm;
742 745
743 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL, 746 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
744 NvDmaFB, NvDmaTT); 747 NvDmaFB, NvDmaTT);
@@ -762,7 +765,8 @@ out_chan:
762 nouveau_channel_put_unlocked(&dev_priv->channel); 765 nouveau_channel_put_unlocked(&dev_priv->channel);
763out_fence: 766out_fence:
764 nouveau_fence_fini(dev); 767 nouveau_fence_fini(dev);
765out_disp: 768out_pm:
769 nouveau_pm_fini(dev);
766 nouveau_backlight_exit(dev); 770 nouveau_backlight_exit(dev);
767 nouveau_display_destroy(dev); 771 nouveau_display_destroy(dev);
768out_irq: 772out_irq:
@@ -779,15 +783,6 @@ out_engine:
779 dev_priv->eng[e]->destroy(dev,e ); 783 dev_priv->eng[e]->destroy(dev,e );
780 } 784 }
781 } 785 }
782
783 engine->fb.takedown(dev);
784out_timer:
785 engine->timer.takedown(dev);
786out_gpio:
787 nouveau_gpio_destroy(dev);
788out_mc:
789 engine->mc.takedown(dev);
790out_gart:
791 nouveau_mem_gart_fini(dev); 786 nouveau_mem_gart_fini(dev);
792out_ttmvram: 787out_ttmvram:
793 nouveau_mem_vram_fini(dev); 788 nouveau_mem_vram_fini(dev);
@@ -795,10 +790,17 @@ out_instmem:
795 engine->instmem.takedown(dev); 790 engine->instmem.takedown(dev);
796out_gpuobj: 791out_gpuobj:
797 nouveau_gpuobj_takedown(dev); 792 nouveau_gpuobj_takedown(dev);
793out_gpio:
794 nouveau_gpio_destroy(dev);
798out_vram: 795out_vram:
799 engine->vram.takedown(dev); 796 engine->vram.takedown(dev);
797out_fb:
798 engine->fb.takedown(dev);
799out_timer:
800 engine->timer.takedown(dev);
801out_mc:
802 engine->mc.takedown(dev);
800out_bios: 803out_bios:
801 nouveau_pm_fini(dev);
802 nouveau_bios_takedown(dev); 804 nouveau_bios_takedown(dev);
803out_display_early: 805out_display_early:
804 engine->display.late_takedown(dev); 806 engine->display.late_takedown(dev);
@@ -823,6 +825,7 @@ static void nouveau_card_takedown(struct drm_device *dev)
823 nouveau_fence_fini(dev); 825 nouveau_fence_fini(dev);
824 } 826 }
825 827
828 nouveau_pm_fini(dev);
826 nouveau_backlight_exit(dev); 829 nouveau_backlight_exit(dev);
827 nouveau_display_destroy(dev); 830 nouveau_display_destroy(dev);
828 831
@@ -835,11 +838,6 @@ static void nouveau_card_takedown(struct drm_device *dev)
835 } 838 }
836 } 839 }
837 } 840 }
838 engine->fb.takedown(dev);
839 engine->timer.takedown(dev);
840 nouveau_gpio_destroy(dev);
841 engine->mc.takedown(dev);
842 engine->display.late_takedown(dev);
843 841
844 if (dev_priv->vga_ram) { 842 if (dev_priv->vga_ram) {
845 nouveau_bo_unpin(dev_priv->vga_ram); 843 nouveau_bo_unpin(dev_priv->vga_ram);
@@ -855,12 +853,17 @@ static void nouveau_card_takedown(struct drm_device *dev)
855 853
856 engine->instmem.takedown(dev); 854 engine->instmem.takedown(dev);
857 nouveau_gpuobj_takedown(dev); 855 nouveau_gpuobj_takedown(dev);
858 engine->vram.takedown(dev);
859 856
860 nouveau_irq_fini(dev); 857 nouveau_gpio_destroy(dev);
858 engine->vram.takedown(dev);
859 engine->fb.takedown(dev);
860 engine->timer.takedown(dev);
861 engine->mc.takedown(dev);
861 862
862 nouveau_pm_fini(dev);
863 nouveau_bios_takedown(dev); 863 nouveau_bios_takedown(dev);
864 engine->display.late_takedown(dev);
865
866 nouveau_irq_fini(dev);
864 867
865 vga_client_register(dev->pdev, NULL, NULL, NULL); 868 vga_client_register(dev->pdev, NULL, NULL, NULL);
866} 869}
@@ -990,7 +993,7 @@ static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
990int nouveau_load(struct drm_device *dev, unsigned long flags) 993int nouveau_load(struct drm_device *dev, unsigned long flags)
991{ 994{
992 struct drm_nouveau_private *dev_priv; 995 struct drm_nouveau_private *dev_priv;
993 uint32_t reg0, strap; 996 uint32_t reg0 = ~0, strap;
994 resource_size_t mmio_start_offs; 997 resource_size_t mmio_start_offs;
995 int ret; 998 int ret;
996 999
@@ -1002,15 +1005,72 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
1002 dev->dev_private = dev_priv; 1005 dev->dev_private = dev_priv;
1003 dev_priv->dev = dev; 1006 dev_priv->dev = dev;
1004 1007
1008 pci_set_master(dev->pdev);
1009
1005 dev_priv->flags = flags & NOUVEAU_FLAGS; 1010 dev_priv->flags = flags & NOUVEAU_FLAGS;
1006 1011
1007 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n", 1012 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1008 dev->pci_vendor, dev->pci_device, dev->pdev->class); 1013 dev->pci_vendor, dev->pci_device, dev->pdev->class);
1009 1014
1010 /* resource 0 is mmio regs */ 1015 /* first up, map the start of mmio and determine the chipset */
1011 /* resource 1 is linear FB */ 1016 dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1012 /* resource 2 is RAMIN (mmio regs + 0x1000000) */ 1017 if (dev_priv->mmio) {
1013 /* resource 6 is bios */ 1018#ifdef __BIG_ENDIAN
1019 /* put the card into big-endian mode if it's not */
1020 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1021 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1022 DRM_MEMORYBARRIER();
1023#endif
1024
1025 /* determine chipset and derive architecture from it */
1026 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1027 if ((reg0 & 0x0f000000) > 0) {
1028 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1029 switch (dev_priv->chipset & 0xf0) {
1030 case 0x10:
1031 case 0x20:
1032 case 0x30:
1033 dev_priv->card_type = dev_priv->chipset & 0xf0;
1034 break;
1035 case 0x40:
1036 case 0x60:
1037 dev_priv->card_type = NV_40;
1038 break;
1039 case 0x50:
1040 case 0x80:
1041 case 0x90:
1042 case 0xa0:
1043 dev_priv->card_type = NV_50;
1044 break;
1045 case 0xc0:
1046 dev_priv->card_type = NV_C0;
1047 break;
1048 case 0xd0:
1049 dev_priv->card_type = NV_D0;
1050 break;
1051 default:
1052 break;
1053 }
1054 } else
1055 if ((reg0 & 0xff00fff0) == 0x20004000) {
1056 if (reg0 & 0x00f00000)
1057 dev_priv->chipset = 0x05;
1058 else
1059 dev_priv->chipset = 0x04;
1060 dev_priv->card_type = NV_04;
1061 }
1062
1063 iounmap(dev_priv->mmio);
1064 }
1065
1066 if (!dev_priv->card_type) {
1067 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1068 ret = -EINVAL;
1069 goto err_priv;
1070 }
1071
1072 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1073 dev_priv->card_type, reg0);
1014 1074
1015 /* map the mmio regs */ 1075 /* map the mmio regs */
1016 mmio_start_offs = pci_resource_start(dev->pdev, 0); 1076 mmio_start_offs = pci_resource_start(dev->pdev, 0);
@@ -1024,62 +1084,6 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
1024 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", 1084 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
1025 (unsigned long long)mmio_start_offs); 1085 (unsigned long long)mmio_start_offs);
1026 1086
1027#ifdef __BIG_ENDIAN
1028 /* Put the card in BE mode if it's not */
1029 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1030 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1031
1032 DRM_MEMORYBARRIER();
1033#endif
1034
1035 /* Time to determine the card architecture */
1036 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1037
1038 /* We're dealing with >=NV10 */
1039 if ((reg0 & 0x0f000000) > 0) {
1040 /* Bit 27-20 contain the architecture in hex */
1041 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1042 /* NV04 or NV05 */
1043 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
1044 if (reg0 & 0x00f00000)
1045 dev_priv->chipset = 0x05;
1046 else
1047 dev_priv->chipset = 0x04;
1048 } else
1049 dev_priv->chipset = 0xff;
1050
1051 switch (dev_priv->chipset & 0xf0) {
1052 case 0x00:
1053 case 0x10:
1054 case 0x20:
1055 case 0x30:
1056 dev_priv->card_type = dev_priv->chipset & 0xf0;
1057 break;
1058 case 0x40:
1059 case 0x60:
1060 dev_priv->card_type = NV_40;
1061 break;
1062 case 0x50:
1063 case 0x80:
1064 case 0x90:
1065 case 0xa0:
1066 dev_priv->card_type = NV_50;
1067 break;
1068 case 0xc0:
1069 dev_priv->card_type = NV_C0;
1070 break;
1071 case 0xd0:
1072 dev_priv->card_type = NV_D0;
1073 break;
1074 default:
1075 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
1076 ret = -EINVAL;
1077 goto err_mmio;
1078 }
1079
1080 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1081 dev_priv->card_type, reg0);
1082
1083 /* determine frequency of timing crystal */ 1087 /* determine frequency of timing crystal */
1084 strap = nv_rd32(dev, 0x101000); 1088 strap = nv_rd32(dev, 0x101000);
1085 if ( dev_priv->chipset < 0x17 || 1089 if ( dev_priv->chipset < 0x17 ||