1 files changed, 60 insertions, 31 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index 6ca80a3fe70d..9c1056cb8a90 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -1,19 +1,64 @@
+#define NV04_PFB_BOOT_0                                         0x00100000
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT                       0x00000003
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB                  0x00000000
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB                   0x00000001
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB                   0x00000002
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB                  0x00000003
+#       define NV04_PFB_BOOT_0_RAM_WIDTH_128                    0x00000004
+#       define NV04_PFB_BOOT_0_RAM_TYPE                         0x00000028
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT             0x00000000
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT            0x00000008
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK      0x00000010
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT            0x00000018
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT            0x00000020
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16         0x00000028
+#       define NV04_PFB_BOOT_0_UMA_ENABLE                       0x00000100
+#       define NV04_PFB_BOOT_0_UMA_SIZE                         0x0000f000
+#define NV04_PFB_DEBUG_0                                        0x00100080
+#       define NV04_PFB_DEBUG_0_PAGE_MODE                       0x00000001
+#       define NV04_PFB_DEBUG_0_REFRESH_OFF                     0x00000010
+#       define NV04_PFB_DEBUG_0_REFRESH_COUNTX64                0x00003f00
+#       define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK                0x00004000
+#       define NV04_PFB_DEBUG_0_SAFE_MODE                       0x00008000
+#       define NV04_PFB_DEBUG_0_ALOM_ENABLE                     0x00010000
+#       define NV04_PFB_DEBUG_0_CASOE                           0x00100000
+#       define NV04_PFB_DEBUG_0_CKE_INVERT                      0x10000000
+#       define NV04_PFB_DEBUG_0_REFINC                          0x20000000
+#       define NV04_PFB_DEBUG_0_SAVE_POWER_OFF                  0x40000000
+#define NV04_PFB_CFG0                                           0x00100200
+#       define NV04_PFB_CFG0_SCRAMBLE                           0x20000000
+#define NV04_PFB_CFG1                                           0x00100204
+#define NV04_PFB_FIFO_DATA                                      0x0010020c
+#       define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK            0xfff00000
+#       define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT           20
+#define NV10_PFB_REFCTRL                                        0x00100210
+#       define NV10_PFB_REFCTRL_VALID_1                         (1 << 31)
+#define NV04_PFB_PAD                                            0x0010021c
+#       define NV04_PFB_PAD_CKE_NORMAL                          (1 << 0)
+#define NV10_PFB_TILE(i)                              (0x00100240 + (i*16))
+#define NV10_PFB_TILE__SIZE                                     8
+#define NV10_PFB_TLIMIT(i)                            (0x00100244 + (i*16))
+#define NV10_PFB_TSIZE(i)                             (0x00100248 + (i*16))
+#define NV10_PFB_TSTATUS(i)                           (0x0010024c + (i*16))
+#define NV04_PFB_REF                                            0x001002d0
+#       define NV04_PFB_REF_CMD_REFRESH                         (1 << 0)
+#define NV04_PFB_PRE                                            0x001002d4
+#       define NV04_PFB_PRE_CMD_PRECHARGE                       (1 << 0)
+#define NV10_PFB_CLOSE_PAGE2                                    0x0010033c
+#define NV04_PFB_SCRAMBLE(i)                         (0x00100400 + 4 * (i))
+#define NV40_PFB_TILE(i)                              (0x00100600 + (i*16))
+#define NV40_PFB_TILE__SIZE_0                                   12
+#define NV40_PFB_TILE__SIZE_1                                   15
+#define NV40_PFB_TLIMIT(i)                            (0x00100604 + (i*16))
+#define NV40_PFB_TSIZE(i)                             (0x00100608 + (i*16))
+#define NV40_PFB_TSTATUS(i)                           (0x0010060c + (i*16))
+#define NV40_PFB_UNK_800                                        0x00100800
-#define NV03_BOOT_0                                        0x00100000
+#define NV_PEXTDEV_BOOT_0                                       0x00101000
-#    define NV03_BOOT_0_RAM_AMOUNT                         0x00000003
+#define NV_PEXTDEV_BOOT_0_RAMCFG                                0x0000003c
-#    define NV03_BOOT_0_RAM_AMOUNT_8MB                     0x00000000
+#       define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT           (8 << 12)
-#    define NV03_BOOT_0_RAM_AMOUNT_2MB                     0x00000001
+#define NV_PEXTDEV_BOOT_3                                       0x0010100c
-#    define NV03_BOOT_0_RAM_AMOUNT_4MB                     0x00000002
-#    define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM               0x00000003
-#    define NV04_BOOT_0_RAM_AMOUNT_32MB                    0x00000000
-#    define NV04_BOOT_0_RAM_AMOUNT_4MB                     0x00000001
-#    define NV04_BOOT_0_RAM_AMOUNT_8MB                     0x00000002
-#    define NV04_BOOT_0_RAM_AMOUNT_16MB                    0x00000003
-#define NV04_FIFO_DATA                                     0x0010020c
-#    define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK              0xfff00000
-#    define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT             20
 #define NV_RAMIN                                           0x00700000
@@ -131,23 +176,6 @@
 #define NV04_PTIMER_TIME_1                                 0x00009410
 #define NV04_PTIMER_ALARM_0                                0x00009420
-#define NV04_PFB_CFG0                                      0x00100200
-#define NV04_PFB_CFG1                                      0x00100204
-#define NV40_PFB_020C                                      0x0010020C
-#define NV10_PFB_TILE(i)                                   (0x00100240 + (i*16))
-#define NV10_PFB_TILE__SIZE                                8
-#define NV10_PFB_TLIMIT(i)                                 (0x00100244 + (i*16))
-#define NV10_PFB_TSIZE(i)                                  (0x00100248 + (i*16))
-#define NV10_PFB_TSTATUS(i)                                (0x0010024C + (i*16))
-#define NV10_PFB_CLOSE_PAGE2                               0x0010033C
-#define NV40_PFB_TILE(i)                                   (0x00100600 + (i*16))
-#define NV40_PFB_TILE__SIZE_0                              12
-#define NV40_PFB_TILE__SIZE_1                              15
-#define NV40_PFB_TLIMIT(i)                                 (0x00100604 + (i*16))
-#define NV40_PFB_TSIZE(i)                                  (0x00100608 + (i*16))
-#define NV40_PFB_TSTATUS(i)                                (0x0010060C + (i*16))
-#define NV40_PFB_UNK_800                                        0x00100800
 #define NV04_PGRAPH_DEBUG_0                                0x00400080
 #define NV04_PGRAPH_DEBUG_1                                0x00400084
 #define NV04_PGRAPH_DEBUG_2                                0x00400088
@@ -814,6 +842,7 @@
 #define NV50_PDISPLAY_SOR_BACKLIGHT_ENABLE                           0x80000000
 #define NV50_PDISPLAY_SOR_BACKLIGHT_LEVEL                            0x00000fff
 #define NV50_SOR_DP_CTRL(i,l)            (0x0061c10c + (i) * 0x800 + (l) * 0x80)
+#define NV50_SOR_DP_CTRL_ENABLED                                     0x00000001
 #define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED                      0x00004000
 #define NV50_SOR_DP_CTRL_LANE_MASK                                   0x001f0000
 #define NV50_SOR_DP_CTRL_LANE_0_ENABLED                              0x00010000

diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h index 6ca80a3fe70d..9c1056cb8a90 100644 --- a/drivers/gpu/drm/nouveau/nouveau_reg.h +++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -1,19 +1,64 @@
1		1
		2	#define NV04_PFB_BOOT_0 0x00100000
		3	# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
		4	# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
		5	# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
		6	# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
		7	# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
		8	# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
		9	# define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
		10	# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
		11	# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
		12	# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010
		13	# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018
		14	# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020
		15	# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028
		16	# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100
		17	# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000
		18	#define NV04_PFB_DEBUG_0 0x00100080
		19	# define NV04_PFB_DEBUG_0_PAGE_MODE 0x00000001
		20	# define NV04_PFB_DEBUG_0_REFRESH_OFF 0x00000010
		21	# define NV04_PFB_DEBUG_0_REFRESH_COUNTX64 0x00003f00
		22	# define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK 0x00004000
		23	# define NV04_PFB_DEBUG_0_SAFE_MODE 0x00008000
		24	# define NV04_PFB_DEBUG_0_ALOM_ENABLE 0x00010000
		25	# define NV04_PFB_DEBUG_0_CASOE 0x00100000
		26	# define NV04_PFB_DEBUG_0_CKE_INVERT 0x10000000
		27	# define NV04_PFB_DEBUG_0_REFINC 0x20000000
		28	# define NV04_PFB_DEBUG_0_SAVE_POWER_OFF 0x40000000
		29	#define NV04_PFB_CFG0 0x00100200
		30	# define NV04_PFB_CFG0_SCRAMBLE 0x20000000
		31	#define NV04_PFB_CFG1 0x00100204
		32	#define NV04_PFB_FIFO_DATA 0x0010020c
		33	# define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
		34	# define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
		35	#define NV10_PFB_REFCTRL 0x00100210
		36	# define NV10_PFB_REFCTRL_VALID_1 (1 << 31)
		37	#define NV04_PFB_PAD 0x0010021c
		38	# define NV04_PFB_PAD_CKE_NORMAL (1 << 0)
		39	#define NV10_PFB_TILE(i) (0x00100240 + (i*16))
		40	#define NV10_PFB_TILE__SIZE 8
		41	#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))
		42	#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))
		43	#define NV10_PFB_TSTATUS(i) (0x0010024c + (i*16))
		44	#define NV04_PFB_REF 0x001002d0
		45	# define NV04_PFB_REF_CMD_REFRESH (1 << 0)
		46	#define NV04_PFB_PRE 0x001002d4
		47	# define NV04_PFB_PRE_CMD_PRECHARGE (1 << 0)
		48	#define NV10_PFB_CLOSE_PAGE2 0x0010033c
		49	#define NV04_PFB_SCRAMBLE(i) (0x00100400 + 4 * (i))
		50	#define NV40_PFB_TILE(i) (0x00100600 + (i*16))
		51	#define NV40_PFB_TILE__SIZE_0 12
		52	#define NV40_PFB_TILE__SIZE_1 15
		53	#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))
		54	#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))
		55	#define NV40_PFB_TSTATUS(i) (0x0010060c + (i*16))
		56	#define NV40_PFB_UNK_800 0x00100800
2		57
3	#define NV03_BOOT_0 0x00100000	58	#define NV_PEXTDEV_BOOT_0 0x00101000
4	# define NV03_BOOT_0_RAM_AMOUNT 0x00000003	59	#define NV_PEXTDEV_BOOT_0_RAMCFG 0x0000003c
5	# define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000	60	# define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (8 << 12)
6	# define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001	61	#define NV_PEXTDEV_BOOT_3 0x0010100c
7	# define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002
8	# define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003
9	# define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000
10	# define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001
11	# define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002
12	# define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003
13
14	#define NV04_FIFO_DATA 0x0010020c
15	# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
16	# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
17		62
18	#define NV_RAMIN 0x00700000	63	#define NV_RAMIN 0x00700000
19		64
@@ -131,23 +176,6 @@
131	#define NV04_PTIMER_TIME_1 0x00009410	176	#define NV04_PTIMER_TIME_1 0x00009410
132	#define NV04_PTIMER_ALARM_0 0x00009420	177	#define NV04_PTIMER_ALARM_0 0x00009420
133		178
134	#define NV04_PFB_CFG0 0x00100200
135	#define NV04_PFB_CFG1 0x00100204
136	#define NV40_PFB_020C 0x0010020C
137	#define NV10_PFB_TILE(i) (0x00100240 + (i*16))
138	#define NV10_PFB_TILE__SIZE 8
139	#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))
140	#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))
141	#define NV10_PFB_TSTATUS(i) (0x0010024C + (i*16))
142	#define NV10_PFB_CLOSE_PAGE2 0x0010033C
143	#define NV40_PFB_TILE(i) (0x00100600 + (i*16))
144	#define NV40_PFB_TILE__SIZE_0 12
145	#define NV40_PFB_TILE__SIZE_1 15
146	#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))
147	#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))
148	#define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16))
149	#define NV40_PFB_UNK_800 0x00100800
150
151	#define NV04_PGRAPH_DEBUG_0 0x00400080	179	#define NV04_PGRAPH_DEBUG_0 0x00400080
152	#define NV04_PGRAPH_DEBUG_1 0x00400084	180	#define NV04_PGRAPH_DEBUG_1 0x00400084
153	#define NV04_PGRAPH_DEBUG_2 0x00400088	181	#define NV04_PGRAPH_DEBUG_2 0x00400088
@@ -814,6 +842,7 @@
814	#define NV50_PDISPLAY_SOR_BACKLIGHT_ENABLE 0x80000000	842	#define NV50_PDISPLAY_SOR_BACKLIGHT_ENABLE 0x80000000
815	#define NV50_PDISPLAY_SOR_BACKLIGHT_LEVEL 0x00000fff	843	#define NV50_PDISPLAY_SOR_BACKLIGHT_LEVEL 0x00000fff
816	#define NV50_SOR_DP_CTRL(i,l) (0x0061c10c + (i) * 0x800 + (l) * 0x80)	844	#define NV50_SOR_DP_CTRL(i,l) (0x0061c10c + (i) * 0x800 + (l) * 0x80)
		845	#define NV50_SOR_DP_CTRL_ENABLED 0x00000001
817	#define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED 0x00004000	846	#define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED 0x00004000
818	#define NV50_SOR_DP_CTRL_LANE_MASK 0x001f0000	847	#define NV50_SOR_DP_CTRL_LANE_MASK 0x001f0000
819	#define NV50_SOR_DP_CTRL_LANE_0_ENABLED 0x00010000	848	#define NV50_SOR_DP_CTRL_LANE_0_ENABLED 0x00010000