diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_reg.h')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_reg.h | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h index 21a6e453b975..1b42541ca9e5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_reg.h +++ b/drivers/gpu/drm/nouveau/nouveau_reg.h | |||
| @@ -551,6 +551,8 @@ | |||
| 551 | #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C | 551 | #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C |
| 552 | #define NV03_PFIFO_CACHE1_PULL0 0x00003240 | 552 | #define NV03_PFIFO_CACHE1_PULL0 0x00003240 |
| 553 | #define NV04_PFIFO_CACHE1_PULL0 0x00003250 | 553 | #define NV04_PFIFO_CACHE1_PULL0 0x00003250 |
| 554 | # define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010 | ||
| 555 | # define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000 | ||
| 554 | #define NV03_PFIFO_CACHE1_PULL1 0x00003250 | 556 | #define NV03_PFIFO_CACHE1_PULL1 0x00003250 |
| 555 | #define NV04_PFIFO_CACHE1_PULL1 0x00003254 | 557 | #define NV04_PFIFO_CACHE1_PULL1 0x00003254 |
| 556 | #define NV04_PFIFO_CACHE1_HASH 0x00003258 | 558 | #define NV04_PFIFO_CACHE1_HASH 0x00003258 |
| @@ -785,15 +787,12 @@ | |||
| 785 | #define NV50_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8) | 787 | #define NV50_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8) |
| 786 | #define NV50_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610b70 + (i) * 0x8) | 788 | #define NV50_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610b70 + (i) * 0x8) |
| 787 | #define NV50_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610b74 + (i) * 0x8) | 789 | #define NV50_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610b74 + (i) * 0x8) |
| 790 | #define NV50_PDISPLAY_EXT_MODE_CTRL_P(i) (0x00610b80 + (i) * 0x8) | ||
| 791 | #define NV50_PDISPLAY_EXT_MODE_CTRL_C(i) (0x00610b84 + (i) * 0x8) | ||
| 788 | #define NV50_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610bdc + (i) * 0x8) | 792 | #define NV50_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610bdc + (i) * 0x8) |
| 789 | #define NV50_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610be0 + (i) * 0x8) | 793 | #define NV50_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610be0 + (i) * 0x8) |
| 790 | |||
| 791 | #define NV90_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610794 + (i) * 0x8) | 794 | #define NV90_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610794 + (i) * 0x8) |
| 792 | #define NV90_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610798 + (i) * 0x8) | 795 | #define NV90_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610798 + (i) * 0x8) |
| 793 | #define NV90_PDISPLAY_DAC_MODE_CTRL_P(i) (0x00610b58 + (i) * 0x8) | ||
| 794 | #define NV90_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8) | ||
| 795 | #define NV90_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610b80 + (i) * 0x8) | ||
| 796 | #define NV90_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610b84 + (i) * 0x8) | ||
| 797 | 796 | ||
| 798 | #define NV50_PDISPLAY_CRTC_CLK 0x00614000 | 797 | #define NV50_PDISPLAY_CRTC_CLK 0x00614000 |
| 799 | #define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100) | 798 | #define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100) |