1 files changed, 87 insertions, 0 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 5158a12f7844..fb9bdd6edf1f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -192,6 +192,92 @@ void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
 }
 
 /*
+ * NV10-NV40 tiling helpers
+ */
+
+static void
+nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
+                           uint32_t size, uint32_t pitch)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
+        struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
+        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+        struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
+
+        tile->addr = addr;
+        tile->size = size;
+        tile->used = !!pitch;
+        nouveau_fence_unref((void **)&tile->fence);
+
+        if (!pfifo->cache_flush(dev))
+                return;
+
+        pfifo->reassign(dev, false);
+        pfifo->cache_flush(dev);
+        pfifo->cache_pull(dev, false);
+
+        nouveau_wait_for_idle(dev);
+
+        pgraph->set_region_tiling(dev, i, addr, size, pitch);
+        pfb->set_region_tiling(dev, i, addr, size, pitch);
+
+        pfifo->cache_pull(dev, true);
+        pfifo->reassign(dev, true);
+}
+
+struct nouveau_tile_reg *
+nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
+                    uint32_t pitch)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
+        struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
+        int i;
+
+        spin_lock(&dev_priv->tile.lock);
+
+        for (i = 0; i < pfb->num_tiles; i++) {
+                if (tile[i].used)
+                        /* Tile region in use. */
+                        continue;
+
+                if (tile[i].fence &&
+                    !nouveau_fence_signalled(tile[i].fence, NULL))
+                        /* Pending tile region. */
+                        continue;
+
+                if (max(tile[i].addr, addr) <
+                    min(tile[i].addr + tile[i].size, addr + size))
+                        /* Kill an intersecting tile region. */
+                        nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
+
+                if (pitch && !found) {
+                        /* Free tile region. */
+                        nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
+                        found = &tile[i];
+                }
+        }
+
+        spin_unlock(&dev_priv->tile.lock);
+
+        return found;
+}
+
+void
+nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
+                       struct nouveau_fence *fence)
+{
+        if (fence) {
+                /* Mark it as pending. */
+                tile->fence = fence;
+                nouveau_fence_ref(fence);
+        }
+
+        tile->used = false;
+}
+
+/*
  * NV50 VM helpers
  */
 int
@@ -513,6 +599,7 @@ nouveau_mem_init(struct drm_device *dev)
 
         INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
         spin_lock_init(&dev_priv->ttm.bo_list_lock);
+        spin_lock_init(&dev_priv->tile.lock);
 
         dev_priv->fb_available_size = nouveau_mem_fb_amount(dev);