diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_dma.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_dma.c | 76 |
1 files changed, 47 insertions, 29 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c index 7afbe8b40d51..50d9e67745af 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.c +++ b/drivers/gpu/drm/nouveau/nouveau_dma.c | |||
@@ -126,47 +126,52 @@ OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords) | |||
126 | chan->dma.cur += nr_dwords; | 126 | chan->dma.cur += nr_dwords; |
127 | } | 127 | } |
128 | 128 | ||
129 | static inline bool | 129 | /* Fetch and adjust GPU GET pointer |
130 | READ_GET(struct nouveau_channel *chan, uint32_t *get) | 130 | * |
131 | * Returns: | ||
132 | * value >= 0, the adjusted GET pointer | ||
133 | * -EINVAL if GET pointer currently outside main push buffer | ||
134 | * -EBUSY if timeout exceeded | ||
135 | */ | ||
136 | static inline int | ||
137 | READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout) | ||
131 | { | 138 | { |
132 | uint32_t val; | 139 | uint32_t val; |
133 | 140 | ||
134 | val = nvchan_rd32(chan, chan->user_get); | 141 | val = nvchan_rd32(chan, chan->user_get); |
135 | if (val < chan->pushbuf_base || | 142 | |
136 | val > chan->pushbuf_base + (chan->dma.max << 2)) { | 143 | /* reset counter as long as GET is still advancing, this is |
137 | /* meaningless to dma_wait() except to know whether the | 144 | * to avoid misdetecting a GPU lockup if the GPU happens to |
138 | * GPU has stalled or not | 145 | * just be processing an operation that takes a long time |
139 | */ | 146 | */ |
140 | *get = val; | 147 | if (val != *prev_get) { |
141 | return false; | 148 | *prev_get = val; |
149 | *timeout = 0; | ||
150 | } | ||
151 | |||
152 | if ((++*timeout & 0xff) == 0) { | ||
153 | DRM_UDELAY(1); | ||
154 | if (*timeout > 100000) | ||
155 | return -EBUSY; | ||
142 | } | 156 | } |
143 | 157 | ||
144 | *get = (val - chan->pushbuf_base) >> 2; | 158 | if (val < chan->pushbuf_base || |
145 | return true; | 159 | val > chan->pushbuf_base + (chan->dma.max << 2)) |
160 | return -EINVAL; | ||
161 | |||
162 | return (val - chan->pushbuf_base) >> 2; | ||
146 | } | 163 | } |
147 | 164 | ||
148 | int | 165 | int |
149 | nouveau_dma_wait(struct nouveau_channel *chan, int size) | 166 | nouveau_dma_wait(struct nouveau_channel *chan, int size) |
150 | { | 167 | { |
151 | uint32_t get, prev_get = 0, cnt = 0; | 168 | uint32_t prev_get = 0, cnt = 0; |
152 | bool get_valid; | 169 | int get; |
153 | 170 | ||
154 | while (chan->dma.free < size) { | 171 | while (chan->dma.free < size) { |
155 | /* reset counter as long as GET is still advancing, this is | 172 | get = READ_GET(chan, &prev_get, &cnt); |
156 | * to avoid misdetecting a GPU lockup if the GPU happens to | 173 | if (unlikely(get == -EBUSY)) |
157 | * just be processing an operation that takes a long time | 174 | return -EBUSY; |
158 | */ | ||
159 | get_valid = READ_GET(chan, &get); | ||
160 | if (get != prev_get) { | ||
161 | prev_get = get; | ||
162 | cnt = 0; | ||
163 | } | ||
164 | |||
165 | if ((++cnt & 0xff) == 0) { | ||
166 | DRM_UDELAY(1); | ||
167 | if (cnt > 100000) | ||
168 | return -EBUSY; | ||
169 | } | ||
170 | 175 | ||
171 | /* loop until we have a usable GET pointer. the value | 176 | /* loop until we have a usable GET pointer. the value |
172 | * we read from the GPU may be outside the main ring if | 177 | * we read from the GPU may be outside the main ring if |
@@ -177,7 +182,7 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size) | |||
177 | * from the SKIPS area, so the code below doesn't have to deal | 182 | * from the SKIPS area, so the code below doesn't have to deal |
178 | * with some fun corner cases. | 183 | * with some fun corner cases. |
179 | */ | 184 | */ |
180 | if (!get_valid || get < NOUVEAU_DMA_SKIPS) | 185 | if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS) |
181 | continue; | 186 | continue; |
182 | 187 | ||
183 | if (get <= chan->dma.cur) { | 188 | if (get <= chan->dma.cur) { |
@@ -203,6 +208,19 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size) | |||
203 | * after processing the currently pending commands. | 208 | * after processing the currently pending commands. |
204 | */ | 209 | */ |
205 | OUT_RING(chan, chan->pushbuf_base | 0x20000000); | 210 | OUT_RING(chan, chan->pushbuf_base | 0x20000000); |
211 | |||
212 | /* wait for GET to depart from the skips area. | ||
213 | * prevents writing GET==PUT and causing a race | ||
214 | * condition that causes us to think the GPU is | ||
215 | * idle when it's not. | ||
216 | */ | ||
217 | do { | ||
218 | get = READ_GET(chan, &prev_get, &cnt); | ||
219 | if (unlikely(get == -EBUSY)) | ||
220 | return -EBUSY; | ||
221 | if (unlikely(get == -EINVAL)) | ||
222 | continue; | ||
223 | } while (get <= NOUVEAU_DMA_SKIPS); | ||
206 | WRITE_PUT(NOUVEAU_DMA_SKIPS); | 224 | WRITE_PUT(NOUVEAU_DMA_SKIPS); |
207 | 225 | ||
208 | /* we're now submitting commands at the start of | 226 | /* we're now submitting commands at the start of |