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path: root/drivers/gpu/drm/nouveau/nouveau_bo.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_bo.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c43
1 files changed, 5 insertions, 38 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index a7883e7db344..5a71ca4346c8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -57,42 +57,7 @@ nouveau_bo_fixup_align(struct drm_device *dev,
57{ 57{
58 struct drm_nouveau_private *dev_priv = dev->dev_private; 58 struct drm_nouveau_private *dev_priv = dev->dev_private;
59 59
60 /* 60 if (dev_priv->card_type < NV_50) {
61 * Some of the tile_flags have a periodic structure of N*4096 bytes,
62 * align to to that as well as the page size. Align the size to the
63 * appropriate boundaries. This does imply that sizes are rounded up
64 * 3-7 pages, so be aware of this and do not waste memory by allocating
65 * many small buffers.
66 */
67 if (dev_priv->card_type == NV_50) {
68 uint32_t block_size = dev_priv->vram_size >> 15;
69 int i;
70
71 switch (tile_flags) {
72 case 0x1800:
73 case 0x2800:
74 case 0x4800:
75 case 0x7a00:
76 if (is_power_of_2(block_size)) {
77 for (i = 1; i < 10; i++) {
78 *align = 12 * i * block_size;
79 if (!(*align % 65536))
80 break;
81 }
82 } else {
83 for (i = 1; i < 10; i++) {
84 *align = 8 * i * block_size;
85 if (!(*align % 65536))
86 break;
87 }
88 }
89 *size = roundup(*size, *align);
90 break;
91 default:
92 break;
93 }
94
95 } else {
96 if (tile_mode) { 61 if (tile_mode) {
97 if (dev_priv->chipset >= 0x40) { 62 if (dev_priv->chipset >= 0x40) {
98 *align = 65536; 63 *align = 65536;
@@ -115,7 +80,6 @@ nouveau_bo_fixup_align(struct drm_device *dev,
115 80
116 /* ALIGN works only on powers of two. */ 81 /* ALIGN works only on powers of two. */
117 *size = roundup(*size, PAGE_SIZE); 82 *size = roundup(*size, PAGE_SIZE);
118
119 if (dev_priv->card_type == NV_50) { 83 if (dev_priv->card_type == NV_50) {
120 *size = roundup(*size, 65536); 84 *size = roundup(*size, 65536);
121 *align = max(65536, *align); 85 *align = max(65536, *align);
@@ -422,7 +386,10 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
422 man->default_caching = TTM_PL_FLAG_CACHED; 386 man->default_caching = TTM_PL_FLAG_CACHED;
423 break; 387 break;
424 case TTM_PL_VRAM: 388 case TTM_PL_VRAM:
425 man->func = &ttm_bo_manager_func; 389 if (dev_priv->card_type == NV_50)
390 man->func = &nouveau_vram_manager;
391 else
392 man->func = &ttm_bo_manager_func;
426 man->flags = TTM_MEMTYPE_FLAG_FIXED | 393 man->flags = TTM_MEMTYPE_FLAG_FIXED |
427 TTM_MEMTYPE_FLAG_MAPPABLE; 394 TTM_MEMTYPE_FLAG_MAPPABLE;
428 man->available_caching = TTM_PL_FLAG_UNCACHED | 395 man->available_caching = TTM_PL_FLAG_UNCACHED |