aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c')
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c258
1 files changed, 258 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
new file mode 100644
index 000000000000..edec7bfaa952
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
@@ -0,0 +1,258 @@
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "mdp5_kms.h"
19
20#include "drm_crtc.h"
21#include "drm_crtc_helper.h"
22
23struct mdp5_encoder {
24 struct drm_encoder base;
25 int intf;
26 enum mdp5_intf intf_id;
27 bool enabled;
28 uint32_t bsc;
29};
30#define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
31
32static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
33{
34 struct msm_drm_private *priv = encoder->dev->dev_private;
35 return to_mdp5_kms(to_mdp_kms(priv->kms));
36}
37
38#ifdef CONFIG_MSM_BUS_SCALING
39#include <mach/board.h>
40#include <mach/msm_bus.h>
41#include <mach/msm_bus_board.h>
42#define MDP_BUS_VECTOR_ENTRY(ab_val, ib_val) \
43 { \
44 .src = MSM_BUS_MASTER_MDP_PORT0, \
45 .dst = MSM_BUS_SLAVE_EBI_CH0, \
46 .ab = (ab_val), \
47 .ib = (ib_val), \
48 }
49
50static struct msm_bus_vectors mdp_bus_vectors[] = {
51 MDP_BUS_VECTOR_ENTRY(0, 0),
52 MDP_BUS_VECTOR_ENTRY(2000000000, 2000000000),
53};
54static struct msm_bus_paths mdp_bus_usecases[] = { {
55 .num_paths = 1,
56 .vectors = &mdp_bus_vectors[0],
57}, {
58 .num_paths = 1,
59 .vectors = &mdp_bus_vectors[1],
60} };
61static struct msm_bus_scale_pdata mdp_bus_scale_table = {
62 .usecase = mdp_bus_usecases,
63 .num_usecases = ARRAY_SIZE(mdp_bus_usecases),
64 .name = "mdss_mdp",
65};
66
67static void bs_init(struct mdp5_encoder *mdp5_encoder)
68{
69 mdp5_encoder->bsc = msm_bus_scale_register_client(
70 &mdp_bus_scale_table);
71 DBG("bus scale client: %08x", mdp5_encoder->bsc);
72}
73
74static void bs_fini(struct mdp5_encoder *mdp5_encoder)
75{
76 if (mdp5_encoder->bsc) {
77 msm_bus_scale_unregister_client(mdp5_encoder->bsc);
78 mdp5_encoder->bsc = 0;
79 }
80}
81
82static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx)
83{
84 if (mdp5_encoder->bsc) {
85 DBG("set bus scaling: %d", idx);
86 /* HACK: scaling down, and then immediately back up
87 * seems to leave things broken (underflow).. so
88 * never disable:
89 */
90 idx = 1;
91 msm_bus_scale_client_update_request(mdp5_encoder->bsc, idx);
92 }
93}
94#else
95static void bs_init(struct mdp5_encoder *mdp5_encoder) {}
96static void bs_fini(struct mdp5_encoder *mdp5_encoder) {}
97static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx) {}
98#endif
99
100static void mdp5_encoder_destroy(struct drm_encoder *encoder)
101{
102 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
103 bs_fini(mdp5_encoder);
104 drm_encoder_cleanup(encoder);
105 kfree(mdp5_encoder);
106}
107
108static const struct drm_encoder_funcs mdp5_encoder_funcs = {
109 .destroy = mdp5_encoder_destroy,
110};
111
112static void mdp5_encoder_dpms(struct drm_encoder *encoder, int mode)
113{
114 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
115 struct mdp5_kms *mdp5_kms = get_kms(encoder);
116 int intf = mdp5_encoder->intf;
117 bool enabled = (mode == DRM_MODE_DPMS_ON);
118
119 DBG("mode=%d", mode);
120
121 if (enabled == mdp5_encoder->enabled)
122 return;
123
124 if (enabled) {
125 bs_set(mdp5_encoder, 1);
126 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 1);
127 } else {
128 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 0);
129 bs_set(mdp5_encoder, 0);
130 }
131
132 mdp5_encoder->enabled = enabled;
133}
134
135static bool mdp5_encoder_mode_fixup(struct drm_encoder *encoder,
136 const struct drm_display_mode *mode,
137 struct drm_display_mode *adjusted_mode)
138{
139 return true;
140}
141
142static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
143 struct drm_display_mode *mode,
144 struct drm_display_mode *adjusted_mode)
145{
146 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
147 struct mdp5_kms *mdp5_kms = get_kms(encoder);
148 int intf = mdp5_encoder->intf;
149 uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
150 uint32_t display_v_start, display_v_end;
151 uint32_t hsync_start_x, hsync_end_x;
152 uint32_t format;
153
154 mode = adjusted_mode;
155
156 DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
157 mode->base.id, mode->name,
158 mode->vrefresh, mode->clock,
159 mode->hdisplay, mode->hsync_start,
160 mode->hsync_end, mode->htotal,
161 mode->vdisplay, mode->vsync_start,
162 mode->vsync_end, mode->vtotal,
163 mode->type, mode->flags);
164
165 ctrl_pol = 0;
166 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
167 ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
168 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
169 ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
170 /* probably need to get DATA_EN polarity from panel.. */
171
172 dtv_hsync_skew = 0; /* get this from panel? */
173 format = 0x213f; /* get this from panel? */
174
175 hsync_start_x = (mode->htotal - mode->hsync_start);
176 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
177
178 vsync_period = mode->vtotal * mode->htotal;
179 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
180 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
181 display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
182
183 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf),
184 MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) |
185 MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal));
186 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period);
187 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len);
188 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf),
189 MDP5_INTF_DISPLAY_HCTL_START(hsync_start_x) |
190 MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x));
191 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start);
192 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end);
193 mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0);
194 mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff);
195 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew);
196 mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol);
197 mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf),
198 MDP5_INTF_ACTIVE_HCTL_START(0) |
199 MDP5_INTF_ACTIVE_HCTL_END(0));
200 mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0);
201 mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0);
202 mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format);
203 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3); /* frame+line? */
204}
205
206static void mdp5_encoder_prepare(struct drm_encoder *encoder)
207{
208 mdp5_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
209}
210
211static void mdp5_encoder_commit(struct drm_encoder *encoder)
212{
213 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
214 mdp5_crtc_set_intf(encoder->crtc, mdp5_encoder->intf,
215 mdp5_encoder->intf_id);
216 mdp5_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
217}
218
219static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = {
220 .dpms = mdp5_encoder_dpms,
221 .mode_fixup = mdp5_encoder_mode_fixup,
222 .mode_set = mdp5_encoder_mode_set,
223 .prepare = mdp5_encoder_prepare,
224 .commit = mdp5_encoder_commit,
225};
226
227/* initialize encoder */
228struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, int intf,
229 enum mdp5_intf intf_id)
230{
231 struct drm_encoder *encoder = NULL;
232 struct mdp5_encoder *mdp5_encoder;
233 int ret;
234
235 mdp5_encoder = kzalloc(sizeof(*mdp5_encoder), GFP_KERNEL);
236 if (!mdp5_encoder) {
237 ret = -ENOMEM;
238 goto fail;
239 }
240
241 mdp5_encoder->intf = intf;
242 mdp5_encoder->intf_id = intf_id;
243 encoder = &mdp5_encoder->base;
244
245 drm_encoder_init(dev, encoder, &mdp5_encoder_funcs,
246 DRM_MODE_ENCODER_TMDS);
247 drm_encoder_helper_add(encoder, &mdp5_encoder_helper_funcs);
248
249 bs_init(mdp5_encoder);
250
251 return encoder;
252
253fail:
254 if (encoder)
255 mdp5_encoder_destroy(encoder);
256
257 return ERR_PTR(ret);
258}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-01 02:54:38 -0500