aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/mga
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/mga')
-rw-r--r--drivers/gpu/drm/mga/mga_dma.c4
-rw-r--r--drivers/gpu/drm/mga/mga_drv.c16
-rw-r--r--drivers/gpu/drm/mga/mga_drv.h19
3 files changed, 10 insertions, 29 deletions
diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c
index 08868ac3048a..5ccb65deb83c 100644
--- a/drivers/gpu/drm/mga/mga_dma.c
+++ b/drivers/gpu/drm/mga/mga_dma.c
@@ -426,7 +426,7 @@ int mga_driver_load(struct drm_device *dev, unsigned long flags)
426 * Bootstrap the driver for AGP DMA. 426 * Bootstrap the driver for AGP DMA.
427 * 427 *
428 * \todo 428 * \todo
429 * Investigate whether there is any benifit to storing the WARP microcode in 429 * Investigate whether there is any benefit to storing the WARP microcode in
430 * AGP memory. If not, the microcode may as well always be put in PCI 430 * AGP memory. If not, the microcode may as well always be put in PCI
431 * memory. 431 * memory.
432 * 432 *
@@ -703,7 +703,7 @@ static int mga_do_pci_dma_bootstrap(struct drm_device *dev,
703static int mga_do_dma_bootstrap(struct drm_device *dev, 703static int mga_do_dma_bootstrap(struct drm_device *dev,
704 drm_mga_dma_bootstrap_t *dma_bs) 704 drm_mga_dma_bootstrap_t *dma_bs)
705{ 705{
706 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev); 706 const int is_agp = (dma_bs->agp_mode != 0) && drm_pci_device_is_agp(dev);
707 int err; 707 int err;
708 drm_mga_private_t *const dev_priv = 708 drm_mga_private_t *const dev_priv =
709 (drm_mga_private_t *) dev->dev_private; 709 (drm_mga_private_t *) dev->dev_private;
diff --git a/drivers/gpu/drm/mga/mga_drv.c b/drivers/gpu/drm/mga/mga_drv.c
index 26d0d8ced80d..42d31874edf2 100644
--- a/drivers/gpu/drm/mga/mga_drv.c
+++ b/drivers/gpu/drm/mga/mga_drv.c
@@ -60,8 +60,6 @@ static struct drm_driver driver = {
60 .irq_uninstall = mga_driver_irq_uninstall, 60 .irq_uninstall = mga_driver_irq_uninstall,
61 .irq_handler = mga_driver_irq_handler, 61 .irq_handler = mga_driver_irq_handler,
62 .reclaim_buffers = drm_core_reclaim_buffers, 62 .reclaim_buffers = drm_core_reclaim_buffers,
63 .get_map_ofs = drm_core_get_map_ofs,
64 .get_reg_ofs = drm_core_get_reg_ofs,
65 .ioctls = mga_ioctls, 63 .ioctls = mga_ioctls,
66 .dma_ioctl = mga_dma_buffers, 64 .dma_ioctl = mga_dma_buffers,
67 .fops = { 65 .fops = {
@@ -75,10 +73,7 @@ static struct drm_driver driver = {
75#ifdef CONFIG_COMPAT 73#ifdef CONFIG_COMPAT
76 .compat_ioctl = mga_compat_ioctl, 74 .compat_ioctl = mga_compat_ioctl,
77#endif 75#endif
78 }, 76 .llseek = noop_llseek,
79 .pci_driver = {
80 .name = DRIVER_NAME,
81 .id_table = pciidlist,
82 }, 77 },
83 78
84 .name = DRIVER_NAME, 79 .name = DRIVER_NAME,
@@ -89,15 +84,20 @@ static struct drm_driver driver = {
89 .patchlevel = DRIVER_PATCHLEVEL, 84 .patchlevel = DRIVER_PATCHLEVEL,
90}; 85};
91 86
87static struct pci_driver mga_pci_driver = {
88 .name = DRIVER_NAME,
89 .id_table = pciidlist,
90};
91
92static int __init mga_init(void) 92static int __init mga_init(void)
93{ 93{
94 driver.num_ioctls = mga_max_ioctl; 94 driver.num_ioctls = mga_max_ioctl;
95 return drm_init(&driver); 95 return drm_pci_init(&driver, &mga_pci_driver);
96} 96}
97 97
98static void __exit mga_exit(void) 98static void __exit mga_exit(void)
99{ 99{
100 drm_exit(&driver); 100 drm_pci_exit(&driver, &mga_pci_driver);
101} 101}
102 102
103module_init(mga_init); 103module_init(mga_init);
diff --git a/drivers/gpu/drm/mga/mga_drv.h b/drivers/gpu/drm/mga/mga_drv.h
index 1084fa4d261b..54558a01969a 100644
--- a/drivers/gpu/drm/mga/mga_drv.h
+++ b/drivers/gpu/drm/mga/mga_drv.h
@@ -195,29 +195,10 @@ extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
195 195
196#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() 196#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
197 197
198#if defined(__linux__) && defined(__alpha__)
199#define MGA_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
200#define MGA_ADDR(reg) (MGA_BASE(reg) + reg)
201
202#define MGA_DEREF(reg) (*(volatile u32 *)MGA_ADDR(reg))
203#define MGA_DEREF8(reg) (*(volatile u8 *)MGA_ADDR(reg))
204
205#define MGA_READ(reg) (_MGA_READ((u32 *)MGA_ADDR(reg)))
206#define MGA_READ8(reg) (_MGA_READ((u8 *)MGA_ADDR(reg)))
207#define MGA_WRITE(reg, val) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF(reg) = val; } while (0)
208#define MGA_WRITE8(reg, val) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8(reg) = val; } while (0)
209
210static inline u32 _MGA_READ(u32 *addr)
211{
212 DRM_MEMORYBARRIER();
213 return *(volatile u32 *)addr;
214}
215#else
216#define MGA_READ8(reg) DRM_READ8(dev_priv->mmio, (reg)) 198#define MGA_READ8(reg) DRM_READ8(dev_priv->mmio, (reg))
217#define MGA_READ(reg) DRM_READ32(dev_priv->mmio, (reg)) 199#define MGA_READ(reg) DRM_READ32(dev_priv->mmio, (reg))
218#define MGA_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val)) 200#define MGA_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val))
219#define MGA_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val)) 201#define MGA_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val))
220#endif
221 202
222#define DWGREG0 0x1c00 203#define DWGREG0 0x1c00
223#define DWGREG0_END 0x1dff 204#define DWGREG0_END 0x1dff