aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c3
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c11
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c14
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c2
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c84
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo_regs.h2
7 files changed, 90 insertions, 30 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c9bfd83dde64..61ae104dca8c 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1505,7 +1505,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1505 goto put_gmch; 1505 goto put_gmch;
1506 } 1506 }
1507 1507
1508 i915_kick_out_firmware_fb(dev_priv); 1508 if (drm_core_check_feature(dev, DRIVER_MODESET))
1509 i915_kick_out_firmware_fb(dev_priv);
1509 1510
1510 pci_set_master(dev->pdev); 1511 pci_set_master(dev->pdev);
1511 1512
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index f78061af7045..6345878ae1e7 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -143,7 +143,7 @@ static void intel_crt_dpms(struct drm_connector *connector, int mode)
143 int old_dpms; 143 int old_dpms;
144 144
145 /* PCH platforms and VLV only support on/off. */ 145 /* PCH platforms and VLV only support on/off. */
146 if (INTEL_INFO(dev)->gen < 5 && mode != DRM_MODE_DPMS_ON) 146 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
147 mode = DRM_MODE_DPMS_OFF; 147 mode = DRM_MODE_DPMS_OFF;
148 148
149 if (mode == connector->dpms) 149 if (mode == connector->dpms)
@@ -729,7 +729,7 @@ void intel_crt_init(struct drm_device *dev)
729 729
730 crt->base.type = INTEL_OUTPUT_ANALOG; 730 crt->base.type = INTEL_OUTPUT_ANALOG;
731 crt->base.cloneable = true; 731 crt->base.cloneable = true;
732 if (IS_HASWELL(dev)) 732 if (IS_HASWELL(dev) || IS_I830(dev))
733 crt->base.crtc_mask = (1 << 0); 733 crt->base.crtc_mask = (1 << 0);
734 else 734 else
735 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 735 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 461a637f1ef7..4154bcd7a070 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3841,6 +3841,17 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3841 } 3841 }
3842 } 3842 }
3843 3843
3844 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3845 /* Use VBT settings if we have an eDP panel */
3846 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3847
3848 if (edp_bpc < display_bpc) {
3849 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3850 display_bpc = edp_bpc;
3851 }
3852 continue;
3853 }
3854
3844 /* 3855 /*
3845 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 3856 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3846 * through, clamp it down. (Note: >12bpc will be caught below.) 3857 * through, clamp it down. (Note: >12bpc will be caught below.)
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 495625914e4a..d7bc817f51a0 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -341,9 +341,17 @@ static int intel_overlay_off(struct intel_overlay *overlay)
341 intel_ring_emit(ring, flip_addr); 341 intel_ring_emit(ring, flip_addr);
342 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); 342 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
343 /* turn overlay off */ 343 /* turn overlay off */
344 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF); 344 if (IS_I830(dev)) {
345 intel_ring_emit(ring, flip_addr); 345 /* Workaround: Don't disable the overlay fully, since otherwise
346 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); 346 * it dies on the next OVERLAY_ON cmd. */
347 intel_ring_emit(ring, MI_NOOP);
348 intel_ring_emit(ring, MI_NOOP);
349 intel_ring_emit(ring, MI_NOOP);
350 } else {
351 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
352 intel_ring_emit(ring, flip_addr);
353 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
354 }
347 intel_ring_advance(ring); 355 intel_ring_advance(ring);
348 356
349 return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail); 357 return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index e019b2369861..e2aacd329545 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -435,7 +435,7 @@ int intel_panel_setup_backlight(struct drm_device *dev)
435 props.type = BACKLIGHT_RAW; 435 props.type = BACKLIGHT_RAW;
436 props.max_brightness = _intel_panel_get_max_backlight(dev); 436 props.max_brightness = _intel_panel_get_max_backlight(dev);
437 if (props.max_brightness == 0) { 437 if (props.max_brightness == 0) {
438 DRM_ERROR("Failed to get maximum backlight value\n"); 438 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
439 return -ENODEV; 439 return -ENODEV;
440 } 440 }
441 dev_priv->backlight = 441 dev_priv->backlight =
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index c01d97db0061..c600fb06e25e 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -894,6 +894,45 @@ static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
894} 894}
895#endif 895#endif
896 896
897static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
898 unsigned if_index, uint8_t tx_rate,
899 uint8_t *data, unsigned length)
900{
901 uint8_t set_buf_index[2] = { if_index, 0 };
902 uint8_t hbuf_size, tmp[8];
903 int i;
904
905 if (!intel_sdvo_set_value(intel_sdvo,
906 SDVO_CMD_SET_HBUF_INDEX,
907 set_buf_index, 2))
908 return false;
909
910 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
911 &hbuf_size, 1))
912 return false;
913
914 /* Buffer size is 0 based, hooray! */
915 hbuf_size++;
916
917 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
918 if_index, length, hbuf_size);
919
920 for (i = 0; i < hbuf_size; i += 8) {
921 memset(tmp, 0, 8);
922 if (i < length)
923 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
924
925 if (!intel_sdvo_set_value(intel_sdvo,
926 SDVO_CMD_SET_HBUF_DATA,
927 tmp, 8))
928 return false;
929 }
930
931 return intel_sdvo_set_value(intel_sdvo,
932 SDVO_CMD_SET_HBUF_TXRATE,
933 &tx_rate, 1);
934}
935
897static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo) 936static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
898{ 937{
899 struct dip_infoframe avi_if = { 938 struct dip_infoframe avi_if = {
@@ -901,11 +940,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
901 .ver = DIP_VERSION_AVI, 940 .ver = DIP_VERSION_AVI,
902 .len = DIP_LEN_AVI, 941 .len = DIP_LEN_AVI,
903 }; 942 };
904 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
905 uint8_t set_buf_index[2] = { 1, 0 };
906 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)]; 943 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
907 uint64_t *data = (uint64_t *)sdvo_data;
908 unsigned i;
909 944
910 intel_dip_infoframe_csum(&avi_if); 945 intel_dip_infoframe_csum(&avi_if);
911 946
@@ -915,22 +950,9 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
915 sdvo_data[3] = avi_if.checksum; 950 sdvo_data[3] = avi_if.checksum;
916 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi)); 951 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
917 952
918 if (!intel_sdvo_set_value(intel_sdvo, 953 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
919 SDVO_CMD_SET_HBUF_INDEX, 954 SDVO_HBUF_TX_VSYNC,
920 set_buf_index, 2)) 955 sdvo_data, sizeof(sdvo_data));
921 return false;
922
923 for (i = 0; i < sizeof(sdvo_data); i += 8) {
924 if (!intel_sdvo_set_value(intel_sdvo,
925 SDVO_CMD_SET_HBUF_DATA,
926 data, 8))
927 return false;
928 data++;
929 }
930
931 return intel_sdvo_set_value(intel_sdvo,
932 SDVO_CMD_SET_HBUF_TXRATE,
933 &tx_rate, 1);
934} 956}
935 957
936static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 958static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
@@ -2360,6 +2382,18 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2360 return true; 2382 return true;
2361} 2383}
2362 2384
2385static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2386{
2387 struct drm_device *dev = intel_sdvo->base.base.dev;
2388 struct drm_connector *connector, *tmp;
2389
2390 list_for_each_entry_safe(connector, tmp,
2391 &dev->mode_config.connector_list, head) {
2392 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2393 intel_sdvo_destroy(connector);
2394 }
2395}
2396
2363static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2397static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2364 struct intel_sdvo_connector *intel_sdvo_connector, 2398 struct intel_sdvo_connector *intel_sdvo_connector,
2365 int type) 2399 int type)
@@ -2683,7 +2717,8 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2683 intel_sdvo->caps.output_flags) != true) { 2717 intel_sdvo->caps.output_flags) != true) {
2684 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 2718 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2685 SDVO_NAME(intel_sdvo)); 2719 SDVO_NAME(intel_sdvo));
2686 goto err; 2720 /* Output_setup can leave behind connectors! */
2721 goto err_output;
2687 } 2722 }
2688 2723
2689 /* Only enable the hotplug irq if we need it, to work around noisy 2724 /* Only enable the hotplug irq if we need it, to work around noisy
@@ -2696,12 +2731,12 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2696 2731
2697 /* Set the input timing to the screen. Assume always input 0. */ 2732 /* Set the input timing to the screen. Assume always input 0. */
2698 if (!intel_sdvo_set_target_input(intel_sdvo)) 2733 if (!intel_sdvo_set_target_input(intel_sdvo))
2699 goto err; 2734 goto err_output;
2700 2735
2701 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 2736 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2702 &intel_sdvo->pixel_clock_min, 2737 &intel_sdvo->pixel_clock_min,
2703 &intel_sdvo->pixel_clock_max)) 2738 &intel_sdvo->pixel_clock_max))
2704 goto err; 2739 goto err_output;
2705 2740
2706 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 2741 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2707 "clock range %dMHz - %dMHz, " 2742 "clock range %dMHz - %dMHz, "
@@ -2721,6 +2756,9 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2721 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 2756 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2722 return true; 2757 return true;
2723 2758
2759err_output:
2760 intel_sdvo_output_cleanup(intel_sdvo);
2761
2724err: 2762err:
2725 drm_encoder_cleanup(&intel_encoder->base); 2763 drm_encoder_cleanup(&intel_encoder->base);
2726 i2c_del_adapter(&intel_sdvo->ddc); 2764 i2c_del_adapter(&intel_sdvo->ddc);
diff --git a/drivers/gpu/drm/i915/intel_sdvo_regs.h b/drivers/gpu/drm/i915/intel_sdvo_regs.h
index 9d030142ee43..770bdd6ecd9f 100644
--- a/drivers/gpu/drm/i915/intel_sdvo_regs.h
+++ b/drivers/gpu/drm/i915/intel_sdvo_regs.h
@@ -708,6 +708,8 @@ struct intel_sdvo_enhancements_arg {
708#define SDVO_CMD_SET_AUDIO_STAT 0x91 708#define SDVO_CMD_SET_AUDIO_STAT 0x91
709#define SDVO_CMD_GET_AUDIO_STAT 0x92 709#define SDVO_CMD_GET_AUDIO_STAT 0x92
710#define SDVO_CMD_SET_HBUF_INDEX 0x93 710#define SDVO_CMD_SET_HBUF_INDEX 0x93
711 #define SDVO_HBUF_INDEX_ELD 0
712 #define SDVO_HBUF_INDEX_AVI_IF 1
711#define SDVO_CMD_GET_HBUF_INDEX 0x94 713#define SDVO_CMD_GET_HBUF_INDEX 0x94
712#define SDVO_CMD_GET_HBUF_INFO 0x95 714#define SDVO_CMD_GET_HBUF_INFO 0x95
713#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96 715#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96