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-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c50
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c36
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c66
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h27
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c48
-rw-r--r--drivers/gpu/drm/i915/i915_gem_evict.c9
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c73
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h9
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c36
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c10
-rw-r--r--drivers/gpu/drm/i915/intel_display.c275
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c60
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h10
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c3
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c2
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c9
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c2
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c8
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c74
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c20
20 files changed, 504 insertions, 323 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 92d5605a34d1..5e43d7076789 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -31,6 +31,7 @@
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include "drmP.h" 32#include "drmP.h"
33#include "drm.h" 33#include "drm.h"
34#include "intel_drv.h"
34#include "i915_drm.h" 35#include "i915_drm.h"
35#include "i915_drv.h" 36#include "i915_drv.h"
36 37
@@ -121,6 +122,54 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data)
121 return 0; 122 return 0;
122} 123}
123 124
125static int i915_gem_pageflip_info(struct seq_file *m, void *data)
126{
127 struct drm_info_node *node = (struct drm_info_node *) m->private;
128 struct drm_device *dev = node->minor->dev;
129 unsigned long flags;
130 struct intel_crtc *crtc;
131
132 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
133 const char *pipe = crtc->pipe ? "B" : "A";
134 const char *plane = crtc->plane ? "B" : "A";
135 struct intel_unpin_work *work;
136
137 spin_lock_irqsave(&dev->event_lock, flags);
138 work = crtc->unpin_work;
139 if (work == NULL) {
140 seq_printf(m, "No flip due on pipe %s (plane %s)\n",
141 pipe, plane);
142 } else {
143 if (!work->pending) {
144 seq_printf(m, "Flip queued on pipe %s (plane %s)\n",
145 pipe, plane);
146 } else {
147 seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",
148 pipe, plane);
149 }
150 if (work->enable_stall_check)
151 seq_printf(m, "Stall check enabled, ");
152 else
153 seq_printf(m, "Stall check waiting for page flip ioctl, ");
154 seq_printf(m, "%d prepares\n", work->pending);
155
156 if (work->old_fb_obj) {
157 struct drm_i915_gem_object *obj_priv = to_intel_bo(work->old_fb_obj);
158 if(obj_priv)
159 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
160 }
161 if (work->pending_flip_obj) {
162 struct drm_i915_gem_object *obj_priv = to_intel_bo(work->pending_flip_obj);
163 if(obj_priv)
164 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
165 }
166 }
167 spin_unlock_irqrestore(&dev->event_lock, flags);
168 }
169
170 return 0;
171}
172
124static int i915_gem_request_info(struct seq_file *m, void *data) 173static int i915_gem_request_info(struct seq_file *m, void *data)
125{ 174{
126 struct drm_info_node *node = (struct drm_info_node *) m->private; 175 struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -777,6 +826,7 @@ static struct drm_info_list i915_debugfs_list[] = {
777 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, 826 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
778 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, 827 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
779 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, 828 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
829 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
780 {"i915_gem_request", i915_gem_request_info, 0}, 830 {"i915_gem_request", i915_gem_request_info, 0},
781 {"i915_gem_seqno", i915_gem_seqno_info, 0}, 831 {"i915_gem_seqno", i915_gem_seqno_info, 0},
782 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, 832 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a7ec93e62f81..9d67b4853030 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -620,8 +620,10 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
620 ret = copy_from_user(cliprects, batch->cliprects, 620 ret = copy_from_user(cliprects, batch->cliprects,
621 batch->num_cliprects * 621 batch->num_cliprects *
622 sizeof(struct drm_clip_rect)); 622 sizeof(struct drm_clip_rect));
623 if (ret != 0) 623 if (ret != 0) {
624 ret = -EFAULT;
624 goto fail_free; 625 goto fail_free;
626 }
625 } 627 }
626 628
627 mutex_lock(&dev->struct_mutex); 629 mutex_lock(&dev->struct_mutex);
@@ -662,8 +664,10 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
662 return -ENOMEM; 664 return -ENOMEM;
663 665
664 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); 666 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
665 if (ret != 0) 667 if (ret != 0) {
668 ret = -EFAULT;
666 goto fail_batch_free; 669 goto fail_batch_free;
670 }
667 671
668 if (cmdbuf->num_cliprects) { 672 if (cmdbuf->num_cliprects) {
669 cliprects = kcalloc(cmdbuf->num_cliprects, 673 cliprects = kcalloc(cmdbuf->num_cliprects,
@@ -676,8 +680,10 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
676 ret = copy_from_user(cliprects, cmdbuf->cliprects, 680 ret = copy_from_user(cliprects, cmdbuf->cliprects,
677 cmdbuf->num_cliprects * 681 cmdbuf->num_cliprects *
678 sizeof(struct drm_clip_rect)); 682 sizeof(struct drm_clip_rect));
679 if (ret != 0) 683 if (ret != 0) {
684 ret = -EFAULT;
680 goto fail_clip_free; 685 goto fail_clip_free;
686 }
681 } 687 }
682 688
683 mutex_lock(&dev->struct_mutex); 689 mutex_lock(&dev->struct_mutex);
@@ -885,7 +891,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
885 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 891 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
886 u32 temp_lo, temp_hi = 0; 892 u32 temp_lo, temp_hi = 0;
887 u64 mchbar_addr; 893 u64 mchbar_addr;
888 int ret = 0; 894 int ret;
889 895
890 if (IS_I965G(dev)) 896 if (IS_I965G(dev))
891 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 897 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
@@ -895,22 +901,23 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
895 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 901 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
896#ifdef CONFIG_PNP 902#ifdef CONFIG_PNP
897 if (mchbar_addr && 903 if (mchbar_addr &&
898 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { 904 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
899 ret = 0; 905 return 0;
900 goto out;
901 }
902#endif 906#endif
903 907
904 /* Get some space for it */ 908 /* Get some space for it */
905 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, 909 dev_priv->mch_res.name = "i915 MCHBAR";
910 dev_priv->mch_res.flags = IORESOURCE_MEM;
911 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
912 &dev_priv->mch_res,
906 MCHBAR_SIZE, MCHBAR_SIZE, 913 MCHBAR_SIZE, MCHBAR_SIZE,
907 PCIBIOS_MIN_MEM, 914 PCIBIOS_MIN_MEM,
908 0, pcibios_align_resource, 915 0, pcibios_align_resource,
909 dev_priv->bridge_dev); 916 dev_priv->bridge_dev);
910 if (ret) { 917 if (ret) {
911 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); 918 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
912 dev_priv->mch_res.start = 0; 919 dev_priv->mch_res.start = 0;
913 goto out; 920 return ret;
914 } 921 }
915 922
916 if (IS_I965G(dev)) 923 if (IS_I965G(dev))
@@ -919,8 +926,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
919 926
920 pci_write_config_dword(dev_priv->bridge_dev, reg, 927 pci_write_config_dword(dev_priv->bridge_dev, reg,
921 lower_32_bits(dev_priv->mch_res.start)); 928 lower_32_bits(dev_priv->mch_res.start));
922out: 929 return 0;
923 return ret;
924} 930}
925 931
926/* Setup MCHBAR if possible, return true if we should disable it again */ 932/* Setup MCHBAR if possible, return true if we should disable it again */
@@ -2082,6 +2088,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2082 goto free_priv; 2088 goto free_priv;
2083 } 2089 }
2084 2090
2091 /* overlay on gen2 is broken and can't address above 1G */
2092 if (IS_GEN2(dev))
2093 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
2094
2085 dev_priv->regs = ioremap(base, size); 2095 dev_priv->regs = ioremap(base, size);
2086 if (!dev_priv->regs) { 2096 if (!dev_priv->regs) {
2087 DRM_ERROR("failed to map registers\n"); 2097 DRM_ERROR("failed to map registers\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e6afa68775b0..9ed9d23caf14 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -61,91 +61,86 @@ extern int intel_agp_enabled;
61 .driver_data = (unsigned long) info } 61 .driver_data = (unsigned long) info }
62 62
63static const struct intel_device_info intel_i830_info = { 63static const struct intel_device_info intel_i830_info = {
64 .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1, 64 .gen = 2, .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
65}; 65};
66 66
67static const struct intel_device_info intel_845g_info = { 67static const struct intel_device_info intel_845g_info = {
68 .is_i8xx = 1, 68 .gen = 2, .is_i8xx = 1,
69}; 69};
70 70
71static const struct intel_device_info intel_i85x_info = { 71static const struct intel_device_info intel_i85x_info = {
72 .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1, 72 .gen = 2, .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,
73 .cursor_needs_physical = 1, 73 .cursor_needs_physical = 1,
74}; 74};
75 75
76static const struct intel_device_info intel_i865g_info = { 76static const struct intel_device_info intel_i865g_info = {
77 .is_i8xx = 1, 77 .gen = 2, .is_i8xx = 1,
78}; 78};
79 79
80static const struct intel_device_info intel_i915g_info = { 80static const struct intel_device_info intel_i915g_info = {
81 .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1, 81 .gen = 3, .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
82}; 82};
83static const struct intel_device_info intel_i915gm_info = { 83static const struct intel_device_info intel_i915gm_info = {
84 .is_i9xx = 1, .is_mobile = 1, 84 .gen = 3, .is_i9xx = 1, .is_mobile = 1,
85 .cursor_needs_physical = 1, 85 .cursor_needs_physical = 1,
86}; 86};
87static const struct intel_device_info intel_i945g_info = { 87static const struct intel_device_info intel_i945g_info = {
88 .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1, 88 .gen = 3, .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
89}; 89};
90static const struct intel_device_info intel_i945gm_info = { 90static const struct intel_device_info intel_i945gm_info = {
91 .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, 91 .gen = 3, .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
92 .has_hotplug = 1, .cursor_needs_physical = 1, 92 .has_hotplug = 1, .cursor_needs_physical = 1,
93}; 93};
94 94
95static const struct intel_device_info intel_i965g_info = { 95static const struct intel_device_info intel_i965g_info = {
96 .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1, 96 .gen = 4, .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1,
97 .has_hotplug = 1,
97}; 98};
98 99
99static const struct intel_device_info intel_i965gm_info = { 100static const struct intel_device_info intel_i965gm_info = {
100 .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1, 101 .gen = 4, .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
101 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, 102 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
102 .has_hotplug = 1,
103}; 103};
104 104
105static const struct intel_device_info intel_g33_info = { 105static const struct intel_device_info intel_g33_info = {
106 .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1, 106 .gen = 3, .is_g33 = 1, .is_i9xx = 1,
107 .has_hotplug = 1, 107 .need_gfx_hws = 1, .has_hotplug = 1,
108}; 108};
109 109
110static const struct intel_device_info intel_g45_info = { 110static const struct intel_device_info intel_g45_info = {
111 .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1, 111 .gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
112 .has_pipe_cxsr = 1, 112 .has_pipe_cxsr = 1, .has_hotplug = 1,
113 .has_hotplug = 1,
114}; 113};
115 114
116static const struct intel_device_info intel_gm45_info = { 115static const struct intel_device_info intel_gm45_info = {
117 .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, 116 .gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1,
118 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, 117 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
119 .has_pipe_cxsr = 1, 118 .has_pipe_cxsr = 1, .has_hotplug = 1,
120 .has_hotplug = 1,
121}; 119};
122 120
123static const struct intel_device_info intel_pineview_info = { 121static const struct intel_device_info intel_pineview_info = {
124 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1, 122 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
125 .need_gfx_hws = 1, 123 .need_gfx_hws = 1, .has_hotplug = 1,
126 .has_hotplug = 1,
127}; 124};
128 125
129static const struct intel_device_info intel_ironlake_d_info = { 126static const struct intel_device_info intel_ironlake_d_info = {
130 .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, 127 .gen = 5, .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1,
131 .has_pipe_cxsr = 1, 128 .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
132 .has_hotplug = 1,
133}; 129};
134 130
135static const struct intel_device_info intel_ironlake_m_info = { 131static const struct intel_device_info intel_ironlake_m_info = {
136 .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1, 132 .gen = 5, .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
137 .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, 133 .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
138 .has_hotplug = 1,
139}; 134};
140 135
141static const struct intel_device_info intel_sandybridge_d_info = { 136static const struct intel_device_info intel_sandybridge_d_info = {
142 .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, 137 .gen = 6, .is_i965g = 1, .is_i9xx = 1,
143 .has_hotplug = 1, .is_gen6 = 1, 138 .need_gfx_hws = 1, .has_hotplug = 1,
144}; 139};
145 140
146static const struct intel_device_info intel_sandybridge_m_info = { 141static const struct intel_device_info intel_sandybridge_m_info = {
147 .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1, 142 .gen = 6, .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1,
148 .has_hotplug = 1, .is_gen6 = 1, 143 .need_gfx_hws = 1, .has_hotplug = 1,
149}; 144};
150 145
151static const struct pci_device_id pciidlist[] = { /* aka */ 146static const struct pci_device_id pciidlist[] = { /* aka */
@@ -175,13 +170,18 @@ static const struct pci_device_id pciidlist[] = { /* aka */
175 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ 170 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
176 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ 171 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
177 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ 172 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
173 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
178 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), 174 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
179 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), 175 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
180 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), 176 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
181 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), 177 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
182 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), 178 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
179 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
180 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
183 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), 181 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
182 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
184 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), 183 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
184 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
185 {0, 0, 0} 185 {0, 0, 0}
186}; 186};
187 187
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 047cd7ce7e1b..af4a263cf257 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -191,6 +191,7 @@ struct drm_i915_display_funcs {
191}; 191};
192 192
193struct intel_device_info { 193struct intel_device_info {
194 u8 gen;
194 u8 is_mobile : 1; 195 u8 is_mobile : 1;
195 u8 is_i8xx : 1; 196 u8 is_i8xx : 1;
196 u8 is_i85x : 1; 197 u8 is_i85x : 1;
@@ -206,7 +207,6 @@ struct intel_device_info {
206 u8 is_broadwater : 1; 207 u8 is_broadwater : 1;
207 u8 is_crestline : 1; 208 u8 is_crestline : 1;
208 u8 is_ironlake : 1; 209 u8 is_ironlake : 1;
209 u8 is_gen6 : 1;
210 u8 has_fbc : 1; 210 u8 has_fbc : 1;
211 u8 has_rc6 : 1; 211 u8 has_rc6 : 1;
212 u8 has_pipe_cxsr : 1; 212 u8 has_pipe_cxsr : 1;
@@ -1162,7 +1162,6 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
1162#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1162#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1163#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1163#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1164#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1164#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1165#define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1166#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1165#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1167#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1166#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1168#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1167#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
@@ -1181,27 +1180,13 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
1181#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1180#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1182#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) 1181#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1183#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) 1182#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1184#define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1185#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1183#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1186 1184
1187#define IS_GEN3(dev) (IS_I915G(dev) || \ 1185#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1188 IS_I915GM(dev) || \ 1186#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1189 IS_I945G(dev) || \ 1187#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1190 IS_I945GM(dev) || \ 1188#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1191 IS_G33(dev) || \ 1189#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1192 IS_PINEVIEW(dev))
1193#define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1194 (dev)->pci_device == 0x2982 || \
1195 (dev)->pci_device == 0x2992 || \
1196 (dev)->pci_device == 0x29A2 || \
1197 (dev)->pci_device == 0x2A02 || \
1198 (dev)->pci_device == 0x2A12 || \
1199 (dev)->pci_device == 0x2E02 || \
1200 (dev)->pci_device == 0x2E12 || \
1201 (dev)->pci_device == 0x2E22 || \
1202 (dev)->pci_device == 0x2E32 || \
1203 (dev)->pci_device == 0x2A42 || \
1204 (dev)->pci_device == 0x2E42)
1205 1190
1206#define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev)) 1191#define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev))
1207#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1192#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index df5a7135c261..cf4ffbee1c00 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -34,6 +34,7 @@
34#include <linux/slab.h> 34#include <linux/slab.h>
35#include <linux/swap.h> 35#include <linux/swap.h>
36#include <linux/pci.h> 36#include <linux/pci.h>
37#include <linux/intel-gtt.h>
37 38
38static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); 39static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
39static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); 40static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
@@ -135,12 +136,15 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
135 return -ENOMEM; 136 return -ENOMEM;
136 137
137 ret = drm_gem_handle_create(file_priv, obj, &handle); 138 ret = drm_gem_handle_create(file_priv, obj, &handle);
138 drm_gem_object_unreference_unlocked(obj); 139 if (ret) {
139 if (ret) 140 drm_gem_object_unreference_unlocked(obj);
140 return ret; 141 return ret;
142 }
141 143
142 args->handle = handle; 144 /* Sink the floating reference from kref_init(handlecount) */
145 drm_gem_object_handle_unreference_unlocked(obj);
143 146
147 args->handle = handle;
144 return 0; 148 return 0;
145} 149}
146 150
@@ -2347,14 +2351,21 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2347 2351
2348 reg->obj = obj; 2352 reg->obj = obj;
2349 2353
2350 if (IS_GEN6(dev)) 2354 switch (INTEL_INFO(dev)->gen) {
2355 case 6:
2351 sandybridge_write_fence_reg(reg); 2356 sandybridge_write_fence_reg(reg);
2352 else if (IS_I965G(dev)) 2357 break;
2358 case 5:
2359 case 4:
2353 i965_write_fence_reg(reg); 2360 i965_write_fence_reg(reg);
2354 else if (IS_I9XX(dev)) 2361 break;
2362 case 3:
2355 i915_write_fence_reg(reg); 2363 i915_write_fence_reg(reg);
2356 else 2364 break;
2365 case 2:
2357 i830_write_fence_reg(reg); 2366 i830_write_fence_reg(reg);
2367 break;
2368 }
2358 2369
2359 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, 2370 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2360 obj_priv->tiling_mode); 2371 obj_priv->tiling_mode);
@@ -2377,22 +2388,26 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2377 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); 2388 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2378 struct drm_i915_fence_reg *reg = 2389 struct drm_i915_fence_reg *reg =
2379 &dev_priv->fence_regs[obj_priv->fence_reg]; 2390 &dev_priv->fence_regs[obj_priv->fence_reg];
2391 uint32_t fence_reg;
2380 2392
2381 if (IS_GEN6(dev)) { 2393 switch (INTEL_INFO(dev)->gen) {
2394 case 6:
2382 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + 2395 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2383 (obj_priv->fence_reg * 8), 0); 2396 (obj_priv->fence_reg * 8), 0);
2384 } else if (IS_I965G(dev)) { 2397 break;
2398 case 5:
2399 case 4:
2385 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); 2400 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2386 } else { 2401 break;
2387 uint32_t fence_reg; 2402 case 3:
2388 2403 if (obj_priv->fence_reg > 8)
2389 if (obj_priv->fence_reg < 8) 2404 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2390 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2391 else 2405 else
2392 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 2406 case 2:
2393 8) * 4; 2407 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2394 2408
2395 I915_WRITE(fence_reg, 0); 2409 I915_WRITE(fence_reg, 0);
2410 break;
2396 } 2411 }
2397 2412
2398 reg->obj = NULL; 2413 reg->obj = NULL;
@@ -3585,6 +3600,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3585 if (ret != 0) { 3600 if (ret != 0) {
3586 DRM_ERROR("copy %d cliprects failed: %d\n", 3601 DRM_ERROR("copy %d cliprects failed: %d\n",
3587 args->num_cliprects, ret); 3602 args->num_cliprects, ret);
3603 ret = -EFAULT;
3588 goto pre_mutex_err; 3604 goto pre_mutex_err;
3589 } 3605 }
3590 } 3606 }
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index 72cae3cccad8..e85246ef691c 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -79,6 +79,7 @@ mark_free(struct drm_i915_gem_object *obj_priv,
79 struct list_head *unwind) 79 struct list_head *unwind)
80{ 80{
81 list_add(&obj_priv->evict_list, unwind); 81 list_add(&obj_priv->evict_list, unwind);
82 drm_gem_object_reference(&obj_priv->base);
82 return drm_mm_scan_add_block(obj_priv->gtt_space); 83 return drm_mm_scan_add_block(obj_priv->gtt_space);
83} 84}
84 85
@@ -165,6 +166,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignmen
165 list_for_each_entry(obj_priv, &unwind_list, evict_list) { 166 list_for_each_entry(obj_priv, &unwind_list, evict_list) {
166 ret = drm_mm_scan_remove_block(obj_priv->gtt_space); 167 ret = drm_mm_scan_remove_block(obj_priv->gtt_space);
167 BUG_ON(ret); 168 BUG_ON(ret);
169 drm_gem_object_unreference(&obj_priv->base);
168 } 170 }
169 171
170 /* We expect the caller to unpin, evict all and try again, or give up. 172 /* We expect the caller to unpin, evict all and try again, or give up.
@@ -181,18 +183,21 @@ found:
181 * scanning, therefore store to be evicted objects on a 183 * scanning, therefore store to be evicted objects on a
182 * temporary list. */ 184 * temporary list. */
183 list_move(&obj_priv->evict_list, &eviction_list); 185 list_move(&obj_priv->evict_list, &eviction_list);
184 } 186 } else
187 drm_gem_object_unreference(&obj_priv->base);
185 } 188 }
186 189
187 /* Unbinding will emit any required flushes */ 190 /* Unbinding will emit any required flushes */
188 list_for_each_entry_safe(obj_priv, tmp_obj_priv, 191 list_for_each_entry_safe(obj_priv, tmp_obj_priv,
189 &eviction_list, evict_list) { 192 &eviction_list, evict_list) {
190#if WATCH_LRU 193#if WATCH_LRU
191 DRM_INFO("%s: evicting %p\n", __func__, obj); 194 DRM_INFO("%s: evicting %p\n", __func__, &obj_priv->base);
192#endif 195#endif
193 ret = i915_gem_object_unbind(&obj_priv->base); 196 ret = i915_gem_object_unbind(&obj_priv->base);
194 if (ret) 197 if (ret)
195 return ret; 198 return ret;
199
200 drm_gem_object_unreference(&obj_priv->base);
196 } 201 }
197 202
198 /* The just created free hole should be on the top of the free stack 203 /* The just created free hole should be on the top of the free stack
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 16861b800fee..744225ebb4b2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -887,6 +887,49 @@ static void i915_handle_error(struct drm_device *dev, bool wedged)
887 queue_work(dev_priv->wq, &dev_priv->error_work); 887 queue_work(dev_priv->wq, &dev_priv->error_work);
888} 888}
889 889
890static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
891{
892 drm_i915_private_t *dev_priv = dev->dev_private;
893 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
895 struct drm_i915_gem_object *obj_priv;
896 struct intel_unpin_work *work;
897 unsigned long flags;
898 bool stall_detected;
899
900 /* Ignore early vblank irqs */
901 if (intel_crtc == NULL)
902 return;
903
904 spin_lock_irqsave(&dev->event_lock, flags);
905 work = intel_crtc->unpin_work;
906
907 if (work == NULL || work->pending || !work->enable_stall_check) {
908 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
909 spin_unlock_irqrestore(&dev->event_lock, flags);
910 return;
911 }
912
913 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
914 obj_priv = to_intel_bo(work->pending_flip_obj);
915 if(IS_I965G(dev)) {
916 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
917 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
918 } else {
919 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
920 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
921 crtc->y * crtc->fb->pitch +
922 crtc->x * crtc->fb->bits_per_pixel/8);
923 }
924
925 spin_unlock_irqrestore(&dev->event_lock, flags);
926
927 if (stall_detected) {
928 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
929 intel_prepare_page_flip(dev, intel_crtc->plane);
930 }
931}
932
890irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 933irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
891{ 934{
892 struct drm_device *dev = (struct drm_device *) arg; 935 struct drm_device *dev = (struct drm_device *) arg;
@@ -1004,15 +1047,19 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1004 if (pipea_stats & vblank_status) { 1047 if (pipea_stats & vblank_status) {
1005 vblank++; 1048 vblank++;
1006 drm_handle_vblank(dev, 0); 1049 drm_handle_vblank(dev, 0);
1007 if (!dev_priv->flip_pending_is_done) 1050 if (!dev_priv->flip_pending_is_done) {
1051 i915_pageflip_stall_check(dev, 0);
1008 intel_finish_page_flip(dev, 0); 1052 intel_finish_page_flip(dev, 0);
1053 }
1009 } 1054 }
1010 1055
1011 if (pipeb_stats & vblank_status) { 1056 if (pipeb_stats & vblank_status) {
1012 vblank++; 1057 vblank++;
1013 drm_handle_vblank(dev, 1); 1058 drm_handle_vblank(dev, 1);
1014 if (!dev_priv->flip_pending_is_done) 1059 if (!dev_priv->flip_pending_is_done) {
1060 i915_pageflip_stall_check(dev, 1);
1015 intel_finish_page_flip(dev, 1); 1061 intel_finish_page_flip(dev, 1);
1062 }
1016 } 1063 }
1017 1064
1018 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || 1065 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
@@ -1303,17 +1350,25 @@ void i915_hangcheck_elapsed(unsigned long data)
1303 i915_seqno_passed(i915_get_gem_seqno(dev, 1350 i915_seqno_passed(i915_get_gem_seqno(dev,
1304 &dev_priv->render_ring), 1351 &dev_priv->render_ring),
1305 i915_get_tail_request(dev)->seqno)) { 1352 i915_get_tail_request(dev)->seqno)) {
1353 bool missed_wakeup = false;
1354
1306 dev_priv->hangcheck_count = 0; 1355 dev_priv->hangcheck_count = 0;
1307 1356
1308 /* Issue a wake-up to catch stuck h/w. */ 1357 /* Issue a wake-up to catch stuck h/w. */
1309 if (dev_priv->render_ring.waiting_gem_seqno | 1358 if (dev_priv->render_ring.waiting_gem_seqno &&
1310 dev_priv->bsd_ring.waiting_gem_seqno) { 1359 waitqueue_active(&dev_priv->render_ring.irq_queue)) {
1311 DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n"); 1360 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1312 if (dev_priv->render_ring.waiting_gem_seqno) 1361 missed_wakeup = true;
1313 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1314 if (dev_priv->bsd_ring.waiting_gem_seqno)
1315 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1316 } 1362 }
1363
1364 if (dev_priv->bsd_ring.waiting_gem_seqno &&
1365 waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
1366 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1367 missed_wakeup = true;
1368 }
1369
1370 if (missed_wakeup)
1371 DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1317 return; 1372 return;
1318 } 1373 }
1319 1374
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67e3ec1a6af9..4f5e15577e89 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -319,6 +319,7 @@
319 319
320#define MI_MODE 0x0209c 320#define MI_MODE 0x0209c
321# define VS_TIMER_DISPATCH (1 << 6) 321# define VS_TIMER_DISPATCH (1 << 6)
322# define MI_FLUSH_ENABLE (1 << 11)
322 323
323#define SCPD0 0x0209c /* 915+ only */ 324#define SCPD0 0x0209c /* 915+ only */
324#define IER 0x020a0 325#define IER 0x020a0
@@ -2205,9 +2206,17 @@
2205#define WM1_LP_SR_EN (1<<31) 2206#define WM1_LP_SR_EN (1<<31)
2206#define WM1_LP_LATENCY_SHIFT 24 2207#define WM1_LP_LATENCY_SHIFT 24
2207#define WM1_LP_LATENCY_MASK (0x7f<<24) 2208#define WM1_LP_LATENCY_MASK (0x7f<<24)
2209#define WM1_LP_FBC_LP1_MASK (0xf<<20)
2210#define WM1_LP_FBC_LP1_SHIFT 20
2208#define WM1_LP_SR_MASK (0x1ff<<8) 2211#define WM1_LP_SR_MASK (0x1ff<<8)
2209#define WM1_LP_SR_SHIFT 8 2212#define WM1_LP_SR_SHIFT 8
2210#define WM1_LP_CURSOR_MASK (0x3f) 2213#define WM1_LP_CURSOR_MASK (0x3f)
2214#define WM2_LP_ILK 0x4510c
2215#define WM2_LP_EN (1<<31)
2216#define WM3_LP_ILK 0x45110
2217#define WM3_LP_EN (1<<31)
2218#define WM1S_LP_ILK 0x45120
2219#define WM1S_LP_EN (1<<31)
2211 2220
2212/* Memory latency timer register */ 2221/* Memory latency timer register */
2213#define MLTR_ILK 0x11222 2222#define MLTR_ILK 0x11222
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 2c6b98f2440e..31f08581e93a 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -789,16 +789,25 @@ int i915_save_state(struct drm_device *dev)
789 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); 789 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
790 790
791 /* Fences */ 791 /* Fences */
792 if (IS_I965G(dev)) { 792 switch (INTEL_INFO(dev)->gen) {
793 case 6:
794 for (i = 0; i < 16; i++)
795 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
796 break;
797 case 5:
798 case 4:
793 for (i = 0; i < 16; i++) 799 for (i = 0; i < 16; i++)
794 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 800 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
795 } else { 801 break;
796 for (i = 0; i < 8; i++) 802 case 3:
797 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
798
799 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 803 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
800 for (i = 0; i < 8; i++) 804 for (i = 0; i < 8; i++)
801 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 805 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
806 case 2:
807 for (i = 0; i < 8; i++)
808 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
809 break;
810
802 } 811 }
803 812
804 return 0; 813 return 0;
@@ -815,15 +824,24 @@ int i915_restore_state(struct drm_device *dev)
815 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 824 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
816 825
817 /* Fences */ 826 /* Fences */
818 if (IS_I965G(dev)) { 827 switch (INTEL_INFO(dev)->gen) {
828 case 6:
829 for (i = 0; i < 16; i++)
830 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
831 break;
832 case 5:
833 case 4:
819 for (i = 0; i < 16; i++) 834 for (i = 0; i < 16; i++)
820 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]); 835 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
821 } else { 836 break;
822 for (i = 0; i < 8; i++) 837 case 3:
823 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]); 838 case 2:
824 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 839 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
825 for (i = 0; i < 8; i++) 840 for (i = 0; i < 8; i++)
826 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]); 841 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
842 for (i = 0; i < 8; i++)
843 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
844 break;
827 } 845 }
828 846
829 i915_restore_display(dev); 847 i915_restore_display(dev);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 4b7735196cd5..197d4f32585a 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -188,7 +188,7 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
188 188
189 if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 189 if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
190 1000, 1)) 190 1000, 1))
191 DRM_ERROR("timed out waiting for FORCE_TRIGGER"); 191 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
192 192
193 if (turn_off_dac) { 193 if (turn_off_dac) {
194 I915_WRITE(PCH_ADPA, temp); 194 I915_WRITE(PCH_ADPA, temp);
@@ -245,7 +245,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
245 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 245 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
246 CRT_HOTPLUG_FORCE_DETECT) == 0, 246 CRT_HOTPLUG_FORCE_DETECT) == 0,
247 1000, 1)) 247 1000, 1))
248 DRM_ERROR("timed out waiting for FORCE_DETECT to go off"); 248 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
249 } 249 }
250 250
251 stat = I915_READ(PORT_HOTPLUG_STAT); 251 stat = I915_READ(PORT_HOTPLUG_STAT);
@@ -400,7 +400,8 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder
400 return status; 400 return status;
401} 401}
402 402
403static enum drm_connector_status intel_crt_detect(struct drm_connector *connector) 403static enum drm_connector_status
404intel_crt_detect(struct drm_connector *connector, bool force)
404{ 405{
405 struct drm_device *dev = connector->dev; 406 struct drm_device *dev = connector->dev;
406 struct drm_encoder *encoder = intel_attached_encoder(connector); 407 struct drm_encoder *encoder = intel_attached_encoder(connector);
@@ -419,6 +420,9 @@ static enum drm_connector_status intel_crt_detect(struct drm_connector *connecto
419 if (intel_crt_detect_ddc(encoder)) 420 if (intel_crt_detect_ddc(encoder))
420 return connector_status_connected; 421 return connector_status_connected;
421 422
423 if (!force)
424 return connector->status;
425
422 /* for pre-945g platforms use load detect */ 426 /* for pre-945g platforms use load detect */
423 if (encoder->crtc && encoder->crtc->enabled) { 427 if (encoder->crtc && encoder->crtc->enabled) {
424 status = intel_crt_load_detect(encoder->crtc, intel_encoder); 428 status = intel_crt_load_detect(encoder->crtc, intel_encoder);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 11a3394f5fe1..b5bf51a4502d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -990,6 +990,22 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
990 struct drm_i915_private *dev_priv = dev->dev_private; 990 struct drm_i915_private *dev_priv = dev->dev_private;
991 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); 991 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
992 992
993 /* Clear existing vblank status. Note this will clear any other
994 * sticky status fields as well.
995 *
996 * This races with i915_driver_irq_handler() with the result
997 * that either function could miss a vblank event. Here it is not
998 * fatal, as we will either wait upon the next vblank interrupt or
999 * timeout. Generally speaking intel_wait_for_vblank() is only
1000 * called during modeset at which time the GPU should be idle and
1001 * should *not* be performing page flips and thus not waiting on
1002 * vblanks...
1003 * Currently, the result of us stealing a vblank from the irq
1004 * handler is that a single frame will be skipped during swapbuffers.
1005 */
1006 I915_WRITE(pipestat_reg,
1007 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
993 /* Wait for vblank interrupt bit to set */ 1009 /* Wait for vblank interrupt bit to set */
994 if (wait_for((I915_READ(pipestat_reg) & 1010 if (wait_for((I915_READ(pipestat_reg) &
995 PIPE_VBLANK_INTERRUPT_STATUS), 1011 PIPE_VBLANK_INTERRUPT_STATUS),
@@ -1486,7 +1502,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1486 dspcntr &= ~DISPPLANE_TILED; 1502 dspcntr &= ~DISPPLANE_TILED;
1487 } 1503 }
1488 1504
1489 if (IS_IRONLAKE(dev)) 1505 if (HAS_PCH_SPLIT(dev))
1490 /* must disable */ 1506 /* must disable */
1491 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 1507 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1492 1508
@@ -1495,20 +1511,19 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1495 Start = obj_priv->gtt_offset; 1511 Start = obj_priv->gtt_offset;
1496 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); 1512 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1497 1513
1498 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); 1514 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1515 Start, Offset, x, y, fb->pitch);
1499 I915_WRITE(dspstride, fb->pitch); 1516 I915_WRITE(dspstride, fb->pitch);
1500 if (IS_I965G(dev)) { 1517 if (IS_I965G(dev)) {
1501 I915_WRITE(dspbase, Offset);
1502 I915_READ(dspbase);
1503 I915_WRITE(dspsurf, Start); 1518 I915_WRITE(dspsurf, Start);
1504 I915_READ(dspsurf);
1505 I915_WRITE(dsptileoff, (y << 16) | x); 1519 I915_WRITE(dsptileoff, (y << 16) | x);
1520 I915_WRITE(dspbase, Offset);
1506 } else { 1521 } else {
1507 I915_WRITE(dspbase, Start + Offset); 1522 I915_WRITE(dspbase, Start + Offset);
1508 I915_READ(dspbase);
1509 } 1523 }
1524 POSTING_READ(dspbase);
1510 1525
1511 if ((IS_I965G(dev) || plane == 0)) 1526 if (IS_I965G(dev) || plane == 0)
1512 intel_update_fbc(crtc, &crtc->mode); 1527 intel_update_fbc(crtc, &crtc->mode);
1513 1528
1514 intel_wait_for_vblank(dev, intel_crtc->pipe); 1529 intel_wait_for_vblank(dev, intel_crtc->pipe);
@@ -1522,7 +1537,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1522 struct drm_framebuffer *old_fb) 1537 struct drm_framebuffer *old_fb)
1523{ 1538{
1524 struct drm_device *dev = crtc->dev; 1539 struct drm_device *dev = crtc->dev;
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1526 struct drm_i915_master_private *master_priv; 1540 struct drm_i915_master_private *master_priv;
1527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1528 struct intel_framebuffer *intel_fb; 1542 struct intel_framebuffer *intel_fb;
@@ -1530,13 +1544,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1530 struct drm_gem_object *obj; 1544 struct drm_gem_object *obj;
1531 int pipe = intel_crtc->pipe; 1545 int pipe = intel_crtc->pipe;
1532 int plane = intel_crtc->plane; 1546 int plane = intel_crtc->plane;
1533 unsigned long Start, Offset;
1534 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1535 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1536 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1537 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1538 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1539 u32 dspcntr;
1540 int ret; 1547 int ret;
1541 1548
1542 /* no fb bound */ 1549 /* no fb bound */
@@ -1572,71 +1579,18 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1572 return ret; 1579 return ret;
1573 } 1580 }
1574 1581
1575 dspcntr = I915_READ(dspcntr_reg); 1582 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1576 /* Mask out pixel format bits in case we change it */ 1583 if (ret) {
1577 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1578 switch (crtc->fb->bits_per_pixel) {
1579 case 8:
1580 dspcntr |= DISPPLANE_8BPP;
1581 break;
1582 case 16:
1583 if (crtc->fb->depth == 15)
1584 dspcntr |= DISPPLANE_15_16BPP;
1585 else
1586 dspcntr |= DISPPLANE_16BPP;
1587 break;
1588 case 24:
1589 case 32:
1590 if (crtc->fb->depth == 30)
1591 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1592 else
1593 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1594 break;
1595 default:
1596 DRM_ERROR("Unknown color depth\n");
1597 i915_gem_object_unpin(obj); 1584 i915_gem_object_unpin(obj);
1598 mutex_unlock(&dev->struct_mutex); 1585 mutex_unlock(&dev->struct_mutex);
1599 return -EINVAL; 1586 return ret;
1600 }
1601 if (IS_I965G(dev)) {
1602 if (obj_priv->tiling_mode != I915_TILING_NONE)
1603 dspcntr |= DISPPLANE_TILED;
1604 else
1605 dspcntr &= ~DISPPLANE_TILED;
1606 }
1607
1608 if (HAS_PCH_SPLIT(dev))
1609 /* must disable */
1610 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1611
1612 I915_WRITE(dspcntr_reg, dspcntr);
1613
1614 Start = obj_priv->gtt_offset;
1615 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1616
1617 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1618 Start, Offset, x, y, crtc->fb->pitch);
1619 I915_WRITE(dspstride, crtc->fb->pitch);
1620 if (IS_I965G(dev)) {
1621 I915_WRITE(dspsurf, Start);
1622 I915_WRITE(dsptileoff, (y << 16) | x);
1623 I915_WRITE(dspbase, Offset);
1624 } else {
1625 I915_WRITE(dspbase, Start + Offset);
1626 } 1587 }
1627 POSTING_READ(dspbase);
1628
1629 if ((IS_I965G(dev) || plane == 0))
1630 intel_update_fbc(crtc, &crtc->mode);
1631
1632 intel_wait_for_vblank(dev, pipe);
1633 1588
1634 if (old_fb) { 1589 if (old_fb) {
1635 intel_fb = to_intel_framebuffer(old_fb); 1590 intel_fb = to_intel_framebuffer(old_fb);
1636 obj_priv = to_intel_bo(intel_fb->obj); 1591 obj_priv = to_intel_bo(intel_fb->obj);
1637 i915_gem_object_unpin(intel_fb->obj); 1592 i915_gem_object_unpin(intel_fb->obj);
1638 } 1593 }
1639 intel_increase_pllclock(crtc, true);
1640 1594
1641 mutex_unlock(&dev->struct_mutex); 1595 mutex_unlock(&dev->struct_mutex);
1642 1596
@@ -1911,9 +1865,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1911 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; 1865 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1912 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; 1866 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1913 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; 1867 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1914 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1915 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1916 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1917 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; 1868 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1918 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; 1869 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1919 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; 1870 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
@@ -1982,15 +1933,19 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1982 } 1933 }
1983 1934
1984 /* Enable panel fitting for LVDS */ 1935 /* Enable panel fitting for LVDS */
1985 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) 1936 if (dev_priv->pch_pf_size &&
1986 || HAS_eDP || intel_pch_has_edp(crtc)) { 1937 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1987 if (dev_priv->pch_pf_size) { 1938 || HAS_eDP || intel_pch_has_edp(crtc))) {
1988 temp = I915_READ(pf_ctl_reg); 1939 /* Force use of hard-coded filter coefficients
1989 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); 1940 * as some pre-programmed values are broken,
1990 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos); 1941 * e.g. x201.
1991 I915_WRITE(pf_win_size, dev_priv->pch_pf_size); 1942 */
1992 } else 1943 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1993 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE); 1944 PF_ENABLE | PF_FILTER_MED_3x3);
1945 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1946 dev_priv->pch_pf_pos);
1947 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1948 dev_priv->pch_pf_size);
1994 } 1949 }
1995 1950
1996 /* Enable CPU pipe */ 1951 /* Enable CPU pipe */
@@ -2115,7 +2070,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2115 I915_WRITE(transconf_reg, temp | TRANS_ENABLE); 2070 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2116 I915_READ(transconf_reg); 2071 I915_READ(transconf_reg);
2117 2072
2118 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 10, 0)) 2073 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100, 1))
2119 DRM_ERROR("failed to enable transcoder\n"); 2074 DRM_ERROR("failed to enable transcoder\n");
2120 } 2075 }
2121 2076
@@ -2155,14 +2110,8 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2155 udelay(100); 2110 udelay(100);
2156 2111
2157 /* Disable PF */ 2112 /* Disable PF */
2158 temp = I915_READ(pf_ctl_reg); 2113 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2159 if ((temp & PF_ENABLE) != 0) { 2114 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2160 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2161 I915_READ(pf_ctl_reg);
2162 }
2163 I915_WRITE(pf_win_size, 0);
2164 POSTING_READ(pf_win_size);
2165
2166 2115
2167 /* disable CPU FDI tx and PCH FDI rx */ 2116 /* disable CPU FDI tx and PCH FDI rx */
2168 temp = I915_READ(fdi_tx_reg); 2117 temp = I915_READ(fdi_tx_reg);
@@ -2421,6 +2370,9 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2421 int pipe = intel_crtc->pipe; 2370 int pipe = intel_crtc->pipe;
2422 bool enabled; 2371 bool enabled;
2423 2372
2373 if (intel_crtc->dpms_mode == mode)
2374 return;
2375
2424 intel_crtc->dpms_mode = mode; 2376 intel_crtc->dpms_mode = mode;
2425 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON; 2377 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2426 2378
@@ -2511,11 +2463,19 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2511 struct drm_display_mode *adjusted_mode) 2463 struct drm_display_mode *adjusted_mode)
2512{ 2464{
2513 struct drm_device *dev = crtc->dev; 2465 struct drm_device *dev = crtc->dev;
2466
2514 if (HAS_PCH_SPLIT(dev)) { 2467 if (HAS_PCH_SPLIT(dev)) {
2515 /* FDI link clock is fixed at 2.7G */ 2468 /* FDI link clock is fixed at 2.7G */
2516 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) 2469 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2517 return false; 2470 return false;
2518 } 2471 }
2472
2473 /* XXX some encoders set the crtcinfo, others don't.
2474 * Obviously we need some form of conflict resolution here...
2475 */
2476 if (adjusted_mode->crtc_htotal == 0)
2477 drm_mode_set_crtcinfo(adjusted_mode, 0);
2478
2519 return true; 2479 return true;
2520} 2480}
2521 2481
@@ -2815,14 +2775,8 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2815 /* Don't promote wm_size to unsigned... */ 2775 /* Don't promote wm_size to unsigned... */
2816 if (wm_size > (long)wm->max_wm) 2776 if (wm_size > (long)wm->max_wm)
2817 wm_size = wm->max_wm; 2777 wm_size = wm->max_wm;
2818 if (wm_size <= 0) { 2778 if (wm_size <= 0)
2819 wm_size = wm->default_wm; 2779 wm_size = wm->default_wm;
2820 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2821 " entries required = %ld, available = %lu.\n",
2822 entries_required + wm->guard_size,
2823 wm->fifo_size);
2824 }
2825
2826 return wm_size; 2780 return wm_size;
2827} 2781}
2828 2782
@@ -3436,8 +3390,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3436 reg_value = I915_READ(WM1_LP_ILK); 3390 reg_value = I915_READ(WM1_LP_ILK);
3437 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK | 3391 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3438 WM1_LP_CURSOR_MASK); 3392 WM1_LP_CURSOR_MASK);
3439 reg_value |= WM1_LP_SR_EN | 3393 reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3440 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3441 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm; 3394 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3442 3395
3443 I915_WRITE(WM1_LP_ILK, reg_value); 3396 I915_WRITE(WM1_LP_ILK, reg_value);
@@ -3554,10 +3507,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3554 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; 3507 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3555 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 3508 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3556 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3509 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3557 bool is_edp = false; 3510 struct intel_encoder *has_edp_encoder = NULL;
3558 struct drm_mode_config *mode_config = &dev->mode_config; 3511 struct drm_mode_config *mode_config = &dev->mode_config;
3559 struct drm_encoder *encoder; 3512 struct drm_encoder *encoder;
3560 struct intel_encoder *intel_encoder = NULL;
3561 const intel_limit_t *limit; 3513 const intel_limit_t *limit;
3562 int ret; 3514 int ret;
3563 struct fdi_m_n m_n = {0}; 3515 struct fdi_m_n m_n = {0};
@@ -3578,12 +3530,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3578 drm_vblank_pre_modeset(dev, pipe); 3530 drm_vblank_pre_modeset(dev, pipe);
3579 3531
3580 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 3532 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3533 struct intel_encoder *intel_encoder;
3581 3534
3582 if (!encoder || encoder->crtc != crtc) 3535 if (encoder->crtc != crtc)
3583 continue; 3536 continue;
3584 3537
3585 intel_encoder = enc_to_intel_encoder(encoder); 3538 intel_encoder = enc_to_intel_encoder(encoder);
3586
3587 switch (intel_encoder->type) { 3539 switch (intel_encoder->type) {
3588 case INTEL_OUTPUT_LVDS: 3540 case INTEL_OUTPUT_LVDS:
3589 is_lvds = true; 3541 is_lvds = true;
@@ -3607,7 +3559,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3607 is_dp = true; 3559 is_dp = true;
3608 break; 3560 break;
3609 case INTEL_OUTPUT_EDP: 3561 case INTEL_OUTPUT_EDP:
3610 is_edp = true; 3562 has_edp_encoder = intel_encoder;
3611 break; 3563 break;
3612 } 3564 }
3613 3565
@@ -3685,10 +3637,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3685 int lane = 0, link_bw, bpp; 3637 int lane = 0, link_bw, bpp;
3686 /* eDP doesn't require FDI link, so just set DP M/N 3638 /* eDP doesn't require FDI link, so just set DP M/N
3687 according to current link config */ 3639 according to current link config */
3688 if (is_edp) { 3640 if (has_edp_encoder) {
3689 target_clock = mode->clock; 3641 target_clock = mode->clock;
3690 intel_edp_link_config(intel_encoder, 3642 intel_edp_link_config(has_edp_encoder,
3691 &lane, &link_bw); 3643 &lane, &link_bw);
3692 } else { 3644 } else {
3693 /* DP over FDI requires target mode clock 3645 /* DP over FDI requires target mode clock
3694 instead of link clock */ 3646 instead of link clock */
@@ -3709,7 +3661,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3709 temp |= PIPE_8BPC; 3661 temp |= PIPE_8BPC;
3710 else 3662 else
3711 temp |= PIPE_6BPC; 3663 temp |= PIPE_6BPC;
3712 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) { 3664 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3713 switch (dev_priv->edp_bpp/3) { 3665 switch (dev_priv->edp_bpp/3) {
3714 case 8: 3666 case 8:
3715 temp |= PIPE_8BPC; 3667 temp |= PIPE_8BPC;
@@ -3782,7 +3734,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3782 3734
3783 udelay(200); 3735 udelay(200);
3784 3736
3785 if (is_edp) { 3737 if (has_edp_encoder) {
3786 if (dev_priv->lvds_use_ssc) { 3738 if (dev_priv->lvds_use_ssc) {
3787 temp |= DREF_SSC1_ENABLE; 3739 temp |= DREF_SSC1_ENABLE;
3788 I915_WRITE(PCH_DREF_CONTROL, temp); 3740 I915_WRITE(PCH_DREF_CONTROL, temp);
@@ -3931,7 +3883,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3931 dpll_reg = pch_dpll_reg; 3883 dpll_reg = pch_dpll_reg;
3932 } 3884 }
3933 3885
3934 if (!is_edp) { 3886 if (!has_edp_encoder) {
3935 I915_WRITE(fp_reg, fp); 3887 I915_WRITE(fp_reg, fp);
3936 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 3888 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3937 I915_READ(dpll_reg); 3889 I915_READ(dpll_reg);
@@ -4026,7 +3978,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4026 } 3978 }
4027 } 3979 }
4028 3980
4029 if (!is_edp) { 3981 if (!has_edp_encoder) {
4030 I915_WRITE(fp_reg, fp); 3982 I915_WRITE(fp_reg, fp);
4031 I915_WRITE(dpll_reg, dpll); 3983 I915_WRITE(dpll_reg, dpll);
4032 I915_READ(dpll_reg); 3984 I915_READ(dpll_reg);
@@ -4105,7 +4057,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4105 I915_WRITE(link_m1_reg, m_n.link_m); 4057 I915_WRITE(link_m1_reg, m_n.link_m);
4106 I915_WRITE(link_n1_reg, m_n.link_n); 4058 I915_WRITE(link_n1_reg, m_n.link_n);
4107 4059
4108 if (is_edp) { 4060 if (has_edp_encoder) {
4109 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 4061 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4110 } else { 4062 } else {
4111 /* enable FDI RX PLL too */ 4063 /* enable FDI RX PLL too */
@@ -4911,15 +4863,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
4911 kfree(intel_crtc); 4863 kfree(intel_crtc);
4912} 4864}
4913 4865
4914struct intel_unpin_work {
4915 struct work_struct work;
4916 struct drm_device *dev;
4917 struct drm_gem_object *old_fb_obj;
4918 struct drm_gem_object *pending_flip_obj;
4919 struct drm_pending_vblank_event *event;
4920 int pending;
4921};
4922
4923static void intel_unpin_work_fn(struct work_struct *__work) 4866static void intel_unpin_work_fn(struct work_struct *__work)
4924{ 4867{
4925 struct intel_unpin_work *work = 4868 struct intel_unpin_work *work =
@@ -5007,7 +4950,8 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
5007 4950
5008 spin_lock_irqsave(&dev->event_lock, flags); 4951 spin_lock_irqsave(&dev->event_lock, flags);
5009 if (intel_crtc->unpin_work) { 4952 if (intel_crtc->unpin_work) {
5010 intel_crtc->unpin_work->pending = 1; 4953 if ((++intel_crtc->unpin_work->pending) > 1)
4954 DRM_ERROR("Prepared flip multiple times\n");
5011 } else { 4955 } else {
5012 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); 4956 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5013 } 4957 }
@@ -5026,9 +4970,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
5026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5027 struct intel_unpin_work *work; 4971 struct intel_unpin_work *work;
5028 unsigned long flags, offset; 4972 unsigned long flags, offset;
5029 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC; 4973 int pipe = intel_crtc->pipe;
5030 int ret, pipesrc; 4974 u32 pf, pipesrc;
5031 u32 flip_mask; 4975 int ret;
5032 4976
5033 work = kzalloc(sizeof *work, GFP_KERNEL); 4977 work = kzalloc(sizeof *work, GFP_KERNEL);
5034 if (work == NULL) 4978 if (work == NULL)
@@ -5077,42 +5021,73 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
5077 atomic_inc(&obj_priv->pending_flip); 5021 atomic_inc(&obj_priv->pending_flip);
5078 work->pending_flip_obj = obj; 5022 work->pending_flip_obj = obj;
5079 5023
5080 if (intel_crtc->plane)
5081 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5082 else
5083 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5084
5085 if (IS_GEN3(dev) || IS_GEN2(dev)) { 5024 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5025 u32 flip_mask;
5026
5027 if (intel_crtc->plane)
5028 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5029 else
5030 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5031
5086 BEGIN_LP_RING(2); 5032 BEGIN_LP_RING(2);
5087 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); 5033 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5088 OUT_RING(0); 5034 OUT_RING(0);
5089 ADVANCE_LP_RING(); 5035 ADVANCE_LP_RING();
5090 } 5036 }
5091 5037
5038 work->enable_stall_check = true;
5039
5092 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5040 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5093 offset = obj_priv->gtt_offset; 5041 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5094 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5095 5042
5096 BEGIN_LP_RING(4); 5043 BEGIN_LP_RING(4);
5097 if (IS_I965G(dev)) { 5044 switch(INTEL_INFO(dev)->gen) {
5045 case 2:
5098 OUT_RING(MI_DISPLAY_FLIP | 5046 OUT_RING(MI_DISPLAY_FLIP |
5099 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5047 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5100 OUT_RING(fb->pitch); 5048 OUT_RING(fb->pitch);
5101 OUT_RING(offset | obj_priv->tiling_mode); 5049 OUT_RING(obj_priv->gtt_offset + offset);
5102 pipesrc = I915_READ(pipesrc_reg); 5050 OUT_RING(MI_NOOP);
5103 OUT_RING(pipesrc & 0x0fff0fff); 5051 break;
5104 } else if (IS_GEN3(dev)) { 5052
5053 case 3:
5105 OUT_RING(MI_DISPLAY_FLIP_I915 | 5054 OUT_RING(MI_DISPLAY_FLIP_I915 |
5106 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5055 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5107 OUT_RING(fb->pitch); 5056 OUT_RING(fb->pitch);
5108 OUT_RING(offset); 5057 OUT_RING(obj_priv->gtt_offset + offset);
5109 OUT_RING(MI_NOOP); 5058 OUT_RING(MI_NOOP);
5110 } else { 5059 break;
5060
5061 case 4:
5062 case 5:
5063 /* i965+ uses the linear or tiled offsets from the
5064 * Display Registers (which do not change across a page-flip)
5065 * so we need only reprogram the base address.
5066 */
5111 OUT_RING(MI_DISPLAY_FLIP | 5067 OUT_RING(MI_DISPLAY_FLIP |
5112 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5068 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5113 OUT_RING(fb->pitch); 5069 OUT_RING(fb->pitch);
5114 OUT_RING(offset); 5070 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5115 OUT_RING(MI_NOOP); 5071
5072 /* XXX Enabling the panel-fitter across page-flip is so far
5073 * untested on non-native modes, so ignore it for now.
5074 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5075 */
5076 pf = 0;
5077 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5078 OUT_RING(pf | pipesrc);
5079 break;
5080
5081 case 6:
5082 OUT_RING(MI_DISPLAY_FLIP |
5083 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5084 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5085 OUT_RING(obj_priv->gtt_offset);
5086
5087 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5088 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5089 OUT_RING(pf | pipesrc);
5090 break;
5116 } 5091 }
5117 ADVANCE_LP_RING(); 5092 ADVANCE_LP_RING();
5118 5093
@@ -5193,7 +5168,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
5193 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 5168 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5194 5169
5195 intel_crtc->cursor_addr = 0; 5170 intel_crtc->cursor_addr = 0;
5196 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; 5171 intel_crtc->dpms_mode = -1;
5197 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 5172 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5198 5173
5199 intel_crtc->busy = false; 5174 intel_crtc->busy = false;
@@ -5701,6 +5676,9 @@ void intel_init_clock_gating(struct drm_device *dev)
5701 I915_WRITE(DISP_ARB_CTL, 5676 I915_WRITE(DISP_ARB_CTL,
5702 (I915_READ(DISP_ARB_CTL) | 5677 (I915_READ(DISP_ARB_CTL) |
5703 DISP_FBC_WM_DIS)); 5678 DISP_FBC_WM_DIS));
5679 I915_WRITE(WM3_LP_ILK, 0);
5680 I915_WRITE(WM2_LP_ILK, 0);
5681 I915_WRITE(WM1_LP_ILK, 0);
5704 } 5682 }
5705 /* 5683 /*
5706 * Based on the document from hardware guys the following bits 5684 * Based on the document from hardware guys the following bits
@@ -5722,8 +5700,7 @@ void intel_init_clock_gating(struct drm_device *dev)
5722 ILK_DPFC_DIS2 | 5700 ILK_DPFC_DIS2 |
5723 ILK_CLK_FBC); 5701 ILK_CLK_FBC);
5724 } 5702 }
5725 if (IS_GEN6(dev)) 5703 return;
5726 return;
5727 } else if (IS_G4X(dev)) { 5704 } else if (IS_G4X(dev)) {
5728 uint32_t dspclk_gate; 5705 uint32_t dspclk_gate;
5729 I915_WRITE(RENCLK_GATE_D1, 0); 5706 I915_WRITE(RENCLK_GATE_D1, 0);
@@ -5784,11 +5761,9 @@ void intel_init_clock_gating(struct drm_device *dev)
5784 OUT_RING(MI_FLUSH); 5761 OUT_RING(MI_FLUSH);
5785 ADVANCE_LP_RING(); 5762 ADVANCE_LP_RING();
5786 } 5763 }
5787 } else { 5764 } else
5788 DRM_DEBUG_KMS("Failed to allocate render context." 5765 DRM_DEBUG_KMS("Failed to allocate render context."
5789 "Disable RC6\n"); 5766 "Disable RC6\n");
5790 return;
5791 }
5792 } 5767 }
5793 5768
5794 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { 5769 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9caccd03dccb..1a51ee07de3e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -239,7 +239,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
239 uint32_t ch_data = ch_ctl + 4; 239 uint32_t ch_data = ch_ctl + 4;
240 int i; 240 int i;
241 int recv_bytes; 241 int recv_bytes;
242 uint32_t ctl;
243 uint32_t status; 242 uint32_t status;
244 uint32_t aux_clock_divider; 243 uint32_t aux_clock_divider;
245 int try, precharge; 244 int try, precharge;
@@ -263,41 +262,43 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
263 else 262 else
264 precharge = 5; 263 precharge = 5;
265 264
265 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
266 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
267 I915_READ(ch_ctl));
268 return -EBUSY;
269 }
270
266 /* Must try at least 3 times according to DP spec */ 271 /* Must try at least 3 times according to DP spec */
267 for (try = 0; try < 5; try++) { 272 for (try = 0; try < 5; try++) {
268 /* Load the send data into the aux channel data registers */ 273 /* Load the send data into the aux channel data registers */
269 for (i = 0; i < send_bytes; i += 4) { 274 for (i = 0; i < send_bytes; i += 4)
270 uint32_t d = pack_aux(send + i, send_bytes - i); 275 I915_WRITE(ch_data + i,
271 276 pack_aux(send + i, send_bytes - i));
272 I915_WRITE(ch_data + i, d);
273 }
274
275 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
276 DP_AUX_CH_CTL_TIME_OUT_400us |
277 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
278 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
279 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
280 DP_AUX_CH_CTL_DONE |
281 DP_AUX_CH_CTL_TIME_OUT_ERROR |
282 DP_AUX_CH_CTL_RECEIVE_ERROR);
283 277
284 /* Send the command and wait for it to complete */ 278 /* Send the command and wait for it to complete */
285 I915_WRITE(ch_ctl, ctl); 279 I915_WRITE(ch_ctl,
286 (void) I915_READ(ch_ctl); 280 DP_AUX_CH_CTL_SEND_BUSY |
281 DP_AUX_CH_CTL_TIME_OUT_400us |
282 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
283 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
284 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
285 DP_AUX_CH_CTL_DONE |
286 DP_AUX_CH_CTL_TIME_OUT_ERROR |
287 DP_AUX_CH_CTL_RECEIVE_ERROR);
287 for (;;) { 288 for (;;) {
288 udelay(100);
289 status = I915_READ(ch_ctl); 289 status = I915_READ(ch_ctl);
290 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 290 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
291 break; 291 break;
292 udelay(100);
292 } 293 }
293 294
294 /* Clear done status and any errors */ 295 /* Clear done status and any errors */
295 I915_WRITE(ch_ctl, (status | 296 I915_WRITE(ch_ctl,
296 DP_AUX_CH_CTL_DONE | 297 status |
297 DP_AUX_CH_CTL_TIME_OUT_ERROR | 298 DP_AUX_CH_CTL_DONE |
298 DP_AUX_CH_CTL_RECEIVE_ERROR)); 299 DP_AUX_CH_CTL_TIME_OUT_ERROR |
299 (void) I915_READ(ch_ctl); 300 DP_AUX_CH_CTL_RECEIVE_ERROR);
300 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0) 301 if (status & DP_AUX_CH_CTL_DONE)
301 break; 302 break;
302 } 303 }
303 304
@@ -324,15 +325,12 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
324 /* Unload any bytes sent back from the other side */ 325 /* Unload any bytes sent back from the other side */
325 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 326 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
326 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 327 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
327
328 if (recv_bytes > recv_size) 328 if (recv_bytes > recv_size)
329 recv_bytes = recv_size; 329 recv_bytes = recv_size;
330 330
331 for (i = 0; i < recv_bytes; i += 4) { 331 for (i = 0; i < recv_bytes; i += 4)
332 uint32_t d = I915_READ(ch_data + i); 332 unpack_aux(I915_READ(ch_data + i),
333 333 recv + i, recv_bytes - i);
334 unpack_aux(d, recv + i, recv_bytes - i);
335 }
336 334
337 return recv_bytes; 335 return recv_bytes;
338} 336}
@@ -1388,7 +1386,7 @@ ironlake_dp_detect(struct drm_connector *connector)
1388 * \return false if DP port is disconnected. 1386 * \return false if DP port is disconnected.
1389 */ 1387 */
1390static enum drm_connector_status 1388static enum drm_connector_status
1391intel_dp_detect(struct drm_connector *connector) 1389intel_dp_detect(struct drm_connector *connector, bool force)
1392{ 1390{
1393 struct drm_encoder *encoder = intel_attached_encoder(connector); 1391 struct drm_encoder *encoder = intel_attached_encoder(connector);
1394 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1392 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0e92aa07b382..ad312ca6b3e5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -176,6 +176,16 @@ struct intel_crtc {
176#define enc_to_intel_encoder(x) container_of(x, struct intel_encoder, enc) 176#define enc_to_intel_encoder(x) container_of(x, struct intel_encoder, enc)
177#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 177#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
178 178
179struct intel_unpin_work {
180 struct work_struct work;
181 struct drm_device *dev;
182 struct drm_gem_object *old_fb_obj;
183 struct drm_gem_object *pending_flip_obj;
184 struct drm_pending_vblank_event *event;
185 int pending;
186 bool enable_stall_check;
187};
188
179struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg, 189struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg,
180 const char *name); 190 const char *name);
181void intel_i2c_destroy(struct i2c_adapter *adapter); 191void intel_i2c_destroy(struct i2c_adapter *adapter);
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index a399f4b2c1c5..7c9ec1472d46 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -221,7 +221,8 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
221 * 221 *
222 * Unimplemented. 222 * Unimplemented.
223 */ 223 */
224static enum drm_connector_status intel_dvo_detect(struct drm_connector *connector) 224static enum drm_connector_status
225intel_dvo_detect(struct drm_connector *connector, bool force)
225{ 226{
226 struct drm_encoder *encoder = intel_attached_encoder(connector); 227 struct drm_encoder *encoder = intel_attached_encoder(connector);
227 struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); 228 struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index ccd4c97e6524..926934a482ec 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -139,7 +139,7 @@ static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
139} 139}
140 140
141static enum drm_connector_status 141static enum drm_connector_status
142intel_hdmi_detect(struct drm_connector *connector) 142intel_hdmi_detect(struct drm_connector *connector, bool force)
143{ 143{
144 struct drm_encoder *encoder = intel_attached_encoder(connector); 144 struct drm_encoder *encoder = intel_attached_encoder(connector);
145 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 145 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index b819c1081147..6ec39a86ed06 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -445,7 +445,8 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
445 * connected and closed means disconnected. We also send hotplug events as 445 * connected and closed means disconnected. We also send hotplug events as
446 * needed, using lid status notification from the input layer. 446 * needed, using lid status notification from the input layer.
447 */ 447 */
448static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector) 448static enum drm_connector_status
449intel_lvds_detect(struct drm_connector *connector, bool force)
449{ 450{
450 struct drm_device *dev = connector->dev; 451 struct drm_device *dev = connector->dev;
451 enum drm_connector_status status = connector_status_connected; 452 enum drm_connector_status status = connector_status_connected;
@@ -540,7 +541,9 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
540 * the LID nofication event. 541 * the LID nofication event.
541 */ 542 */
542 if (connector) 543 if (connector)
543 connector->status = connector->funcs->detect(connector); 544 connector->status = connector->funcs->detect(connector,
545 false);
546
544 /* Don't force modeset on machines where it causes a GPU lockup */ 547 /* Don't force modeset on machines where it causes a GPU lockup */
545 if (dmi_check_system(intel_no_modeset_on_lid)) 548 if (dmi_check_system(intel_no_modeset_on_lid))
546 return NOTIFY_OK; 549 return NOTIFY_OK;
@@ -875,8 +878,6 @@ void intel_lvds_init(struct drm_device *dev)
875 878
876 intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); 879 intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
877 intel_encoder->crtc_mask = (1 << 1); 880 intel_encoder->crtc_mask = (1 << 1);
878 if (IS_I965G(dev))
879 intel_encoder->crtc_mask |= (1 << 0);
880 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); 881 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
881 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 882 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
882 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 883 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 4f00390d7c61..1d306a458be6 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -25,6 +25,8 @@
25 * 25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */ 27 */
28
29#include <linux/seq_file.h>
28#include "drmP.h" 30#include "drmP.h"
29#include "drm.h" 31#include "drm.h"
30#include "i915_drm.h" 32#include "i915_drm.h"
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 51e9c9e718c4..cb3508f78bc3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -220,9 +220,13 @@ static int init_render_ring(struct drm_device *dev,
220{ 220{
221 drm_i915_private_t *dev_priv = dev->dev_private; 221 drm_i915_private_t *dev_priv = dev->dev_private;
222 int ret = init_ring_common(dev, ring); 222 int ret = init_ring_common(dev, ring);
223 int mode;
224
223 if (IS_I9XX(dev) && !IS_GEN3(dev)) { 225 if (IS_I9XX(dev) && !IS_GEN3(dev)) {
224 I915_WRITE(MI_MODE, 226 mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
225 (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH); 227 if (IS_GEN6(dev))
228 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
229 I915_WRITE(MI_MODE, mode);
226 } 230 }
227 return ret; 231 return ret;
228} 232}
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 093e914e8a41..e8e902d614ed 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1061,8 +1061,9 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1061 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1061 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1062 return false; 1062 return false;
1063 1063
1064 if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode)) 1064 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1065 return false; 1065 mode,
1066 adjusted_mode);
1066 } else if (intel_sdvo->is_lvds) { 1067 } else if (intel_sdvo->is_lvds) {
1067 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0); 1068 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0);
1068 1069
@@ -1070,8 +1071,9 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1070 intel_sdvo->sdvo_lvds_fixed_mode)) 1071 intel_sdvo->sdvo_lvds_fixed_mode))
1071 return false; 1072 return false;
1072 1073
1073 if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode)) 1074 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1074 return false; 1075 mode,
1076 adjusted_mode);
1075 } 1077 }
1076 1078
1077 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1079 /* Make the CRTC code factor in the SDVO pixel multiplier. The
@@ -1108,10 +1110,9 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1108 in_out.in0 = intel_sdvo->attached_output; 1110 in_out.in0 = intel_sdvo->attached_output;
1109 in_out.in1 = 0; 1111 in_out.in1 = 0;
1110 1112
1111 if (!intel_sdvo_set_value(intel_sdvo, 1113 intel_sdvo_set_value(intel_sdvo,
1112 SDVO_CMD_SET_IN_OUT_MAP, 1114 SDVO_CMD_SET_IN_OUT_MAP,
1113 &in_out, sizeof(in_out))) 1115 &in_out, sizeof(in_out));
1114 return;
1115 1116
1116 if (intel_sdvo->is_hdmi) { 1117 if (intel_sdvo->is_hdmi) {
1117 if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode)) 1118 if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
@@ -1122,11 +1123,9 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1122 1123
1123 /* We have tried to get input timing in mode_fixup, and filled into 1124 /* We have tried to get input timing in mode_fixup, and filled into
1124 adjusted_mode */ 1125 adjusted_mode */
1125 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) { 1126 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1126 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1127 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1127 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags; 1128 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags;
1128 } else
1129 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1130 1129
1131 /* If it's a TV, we already set the output timing in mode_fixup. 1130 /* If it's a TV, we already set the output timing in mode_fixup.
1132 * Otherwise, the output timing is equal to the input timing. 1131 * Otherwise, the output timing is equal to the input timing.
@@ -1137,8 +1136,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1137 intel_sdvo->attached_output)) 1136 intel_sdvo->attached_output))
1138 return; 1137 return;
1139 1138
1140 if (!intel_sdvo_set_output_timing(intel_sdvo, &input_dtd)) 1139 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
1141 return;
1142 } 1140 }
1143 1141
1144 /* Set the input timing to the screen. Assume always input 0. */ 1142 /* Set the input timing to the screen. Assume always input 0. */
@@ -1165,8 +1163,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1165 intel_sdvo_set_input_timing(encoder, &input_dtd); 1163 intel_sdvo_set_input_timing(encoder, &input_dtd);
1166 } 1164 }
1167#else 1165#else
1168 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1166 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
1169 return;
1170#endif 1167#endif
1171 1168
1172 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode); 1169 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
@@ -1420,7 +1417,7 @@ intel_analog_is_connected(struct drm_device *dev)
1420 if (!analog_connector) 1417 if (!analog_connector)
1421 return false; 1418 return false;
1422 1419
1423 if (analog_connector->funcs->detect(analog_connector) == 1420 if (analog_connector->funcs->detect(analog_connector, false) ==
1424 connector_status_disconnected) 1421 connector_status_disconnected)
1425 return false; 1422 return false;
1426 1423
@@ -1489,7 +1486,8 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1489 return status; 1486 return status;
1490} 1487}
1491 1488
1492static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector) 1489static enum drm_connector_status
1490intel_sdvo_detect(struct drm_connector *connector, bool force)
1493{ 1491{
1494 uint16_t response; 1492 uint16_t response;
1495 struct drm_encoder *encoder = intel_attached_encoder(connector); 1493 struct drm_encoder *encoder = intel_attached_encoder(connector);
@@ -1932,6 +1930,41 @@ static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1932 .destroy = intel_sdvo_enc_destroy, 1930 .destroy = intel_sdvo_enc_destroy,
1933}; 1931};
1934 1932
1933static void
1934intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1935{
1936 uint16_t mask = 0;
1937 unsigned int num_bits;
1938
1939 /* Make a mask of outputs less than or equal to our own priority in the
1940 * list.
1941 */
1942 switch (sdvo->controlled_output) {
1943 case SDVO_OUTPUT_LVDS1:
1944 mask |= SDVO_OUTPUT_LVDS1;
1945 case SDVO_OUTPUT_LVDS0:
1946 mask |= SDVO_OUTPUT_LVDS0;
1947 case SDVO_OUTPUT_TMDS1:
1948 mask |= SDVO_OUTPUT_TMDS1;
1949 case SDVO_OUTPUT_TMDS0:
1950 mask |= SDVO_OUTPUT_TMDS0;
1951 case SDVO_OUTPUT_RGB1:
1952 mask |= SDVO_OUTPUT_RGB1;
1953 case SDVO_OUTPUT_RGB0:
1954 mask |= SDVO_OUTPUT_RGB0;
1955 break;
1956 }
1957
1958 /* Count bits to find what number we are in the priority list. */
1959 mask &= sdvo->caps.output_flags;
1960 num_bits = hweight16(mask);
1961 /* If more than 3 outputs, default to DDC bus 3 for now. */
1962 if (num_bits > 3)
1963 num_bits = 3;
1964
1965 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1966 sdvo->ddc_bus = 1 << num_bits;
1967}
1935 1968
1936/** 1969/**
1937 * Choose the appropriate DDC bus for control bus switch command for this 1970 * Choose the appropriate DDC bus for control bus switch command for this
@@ -1951,7 +1984,10 @@ intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
1951 else 1984 else
1952 mapping = &(dev_priv->sdvo_mappings[1]); 1985 mapping = &(dev_priv->sdvo_mappings[1]);
1953 1986
1954 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 1987 if (mapping->initialized)
1988 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1989 else
1990 intel_sdvo_guess_ddc_bus(sdvo);
1955} 1991}
1956 1992
1957static bool 1993static bool
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index d2029efee982..4a117e318a73 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1231,7 +1231,6 @@ intel_tv_detect_type (struct intel_tv *intel_tv)
1231 struct drm_encoder *encoder = &intel_tv->base.enc; 1231 struct drm_encoder *encoder = &intel_tv->base.enc;
1232 struct drm_device *dev = encoder->dev; 1232 struct drm_device *dev = encoder->dev;
1233 struct drm_i915_private *dev_priv = dev->dev_private; 1233 struct drm_i915_private *dev_priv = dev->dev_private;
1234 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
1235 unsigned long irqflags; 1234 unsigned long irqflags;
1236 u32 tv_ctl, save_tv_ctl; 1235 u32 tv_ctl, save_tv_ctl;
1237 u32 tv_dac, save_tv_dac; 1236 u32 tv_dac, save_tv_dac;
@@ -1268,11 +1267,15 @@ intel_tv_detect_type (struct intel_tv *intel_tv)
1268 DAC_C_0_7_V); 1267 DAC_C_0_7_V);
1269 I915_WRITE(TV_CTL, tv_ctl); 1268 I915_WRITE(TV_CTL, tv_ctl);
1270 I915_WRITE(TV_DAC, tv_dac); 1269 I915_WRITE(TV_DAC, tv_dac);
1271 intel_wait_for_vblank(dev, intel_crtc->pipe); 1270 POSTING_READ(TV_DAC);
1271 msleep(20);
1272
1272 tv_dac = I915_READ(TV_DAC); 1273 tv_dac = I915_READ(TV_DAC);
1273 I915_WRITE(TV_DAC, save_tv_dac); 1274 I915_WRITE(TV_DAC, save_tv_dac);
1274 I915_WRITE(TV_CTL, save_tv_ctl); 1275 I915_WRITE(TV_CTL, save_tv_ctl);
1275 intel_wait_for_vblank(dev, intel_crtc->pipe); 1276 POSTING_READ(TV_CTL);
1277 msleep(20);
1278
1276 /* 1279 /*
1277 * A B C 1280 * A B C
1278 * 0 1 1 Composite 1281 * 0 1 1 Composite
@@ -1338,7 +1341,7 @@ static void intel_tv_find_better_format(struct drm_connector *connector)
1338 * we have a pipe programmed in order to probe the TV. 1341 * we have a pipe programmed in order to probe the TV.
1339 */ 1342 */
1340static enum drm_connector_status 1343static enum drm_connector_status
1341intel_tv_detect(struct drm_connector *connector) 1344intel_tv_detect(struct drm_connector *connector, bool force)
1342{ 1345{
1343 struct drm_display_mode mode; 1346 struct drm_display_mode mode;
1344 struct drm_encoder *encoder = intel_attached_encoder(connector); 1347 struct drm_encoder *encoder = intel_attached_encoder(connector);
@@ -1350,7 +1353,7 @@ intel_tv_detect(struct drm_connector *connector)
1350 1353
1351 if (encoder->crtc && encoder->crtc->enabled) { 1354 if (encoder->crtc && encoder->crtc->enabled) {
1352 type = intel_tv_detect_type(intel_tv); 1355 type = intel_tv_detect_type(intel_tv);
1353 } else { 1356 } else if (force) {
1354 struct drm_crtc *crtc; 1357 struct drm_crtc *crtc;
1355 int dpms_mode; 1358 int dpms_mode;
1356 1359
@@ -1361,10 +1364,9 @@ intel_tv_detect(struct drm_connector *connector)
1361 intel_release_load_detect_pipe(&intel_tv->base, connector, 1364 intel_release_load_detect_pipe(&intel_tv->base, connector,
1362 dpms_mode); 1365 dpms_mode);
1363 } else 1366 } else
1364 type = -1; 1367 return connector_status_unknown;
1365 } 1368 } else
1366 1369 return connector->status;
1367 intel_tv->type = type;
1368 1370
1369 if (type < 0) 1371 if (type < 0)
1370 return connector_status_disconnected; 1372 return connector_status_disconnected;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 14:35:40 -0500