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-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index bf0195a96d53..414af1e2973b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -289,8 +289,6 @@ static int init_ring_common(struct intel_ring_buffer *ring)
289 I915_WRITE_HEAD(ring, 0); 289 I915_WRITE_HEAD(ring, 0);
290 ring->write_tail(ring, 0); 290 ring->write_tail(ring, 0);
291 291
292 /* Initialize the ring. */
293 I915_WRITE_START(ring, obj->gtt_offset);
294 head = I915_READ_HEAD(ring) & HEAD_ADDR; 292 head = I915_READ_HEAD(ring) & HEAD_ADDR;
295 293
296 /* G45 ring initialization fails to reset head to zero */ 294 /* G45 ring initialization fails to reset head to zero */
@@ -316,6 +314,11 @@ static int init_ring_common(struct intel_ring_buffer *ring)
316 } 314 }
317 } 315 }
318 316
317 /* Initialize the ring. This must happen _after_ we've cleared the ring
318 * registers with the above sequence (the readback of the HEAD registers
319 * also enforces ordering), otherwise the hw might lose the new ring
320 * register values. */
321 I915_WRITE_START(ring, obj->gtt_offset);
319 I915_WRITE_CTL(ring, 322 I915_WRITE_CTL(ring,
320 ((ring->size - PAGE_SIZE) & RING_NR_PAGES) 323 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
321 | RING_VALID); 324 | RING_VALID);