diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.h')
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.h | 157 |
1 files changed, 91 insertions, 66 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 3126c2681983..6d6fde85a636 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h | |||
@@ -1,22 +1,40 @@ | |||
1 | #ifndef _INTEL_RINGBUFFER_H_ | 1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | 2 | #define _INTEL_RINGBUFFER_H_ |
3 | 3 | ||
4 | enum { | ||
5 | RCS = 0x0, | ||
6 | VCS, | ||
7 | BCS, | ||
8 | I915_NUM_RINGS, | ||
9 | }; | ||
10 | |||
4 | struct intel_hw_status_page { | 11 | struct intel_hw_status_page { |
5 | void *page_addr; | 12 | u32 __iomem *page_addr; |
6 | unsigned int gfx_addr; | 13 | unsigned int gfx_addr; |
7 | struct drm_gem_object *obj; | 14 | struct drm_i915_gem_object *obj; |
8 | }; | 15 | }; |
9 | 16 | ||
10 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL(ring->mmio_base)) | 17 | #define I915_RING_READ(reg) i915_safe_read(dev_priv, reg) |
11 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val) | 18 | |
12 | #define I915_READ_START(ring) I915_READ(RING_START(ring->mmio_base)) | 19 | #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base)) |
13 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val) | 20 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
14 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD(ring->mmio_base)) | 21 | |
15 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val) | 22 | #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base)) |
16 | #define I915_READ_CTL(ring) I915_READ(RING_CTL(ring->mmio_base)) | 23 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
17 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val) | 24 | |
25 | #define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base)) | ||
26 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | ||
27 | |||
28 | #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base)) | ||
29 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | ||
30 | |||
31 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | ||
32 | #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base)) | ||
33 | |||
34 | #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base)) | ||
35 | #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base)) | ||
36 | #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base)) | ||
18 | 37 | ||
19 | struct drm_i915_gem_execbuffer2; | ||
20 | struct intel_ring_buffer { | 38 | struct intel_ring_buffer { |
21 | const char *name; | 39 | const char *name; |
22 | enum intel_ring_id { | 40 | enum intel_ring_id { |
@@ -25,44 +43,38 @@ struct intel_ring_buffer { | |||
25 | RING_BLT = 0x4, | 43 | RING_BLT = 0x4, |
26 | } id; | 44 | } id; |
27 | u32 mmio_base; | 45 | u32 mmio_base; |
28 | unsigned long size; | ||
29 | void *virtual_start; | 46 | void *virtual_start; |
30 | struct drm_device *dev; | 47 | struct drm_device *dev; |
31 | struct drm_gem_object *gem_object; | 48 | struct drm_i915_gem_object *obj; |
32 | 49 | ||
33 | unsigned int head; | 50 | u32 head; |
34 | unsigned int tail; | 51 | u32 tail; |
35 | int space; | 52 | int space; |
53 | int size; | ||
54 | int effective_size; | ||
36 | struct intel_hw_status_page status_page; | 55 | struct intel_hw_status_page status_page; |
37 | 56 | ||
38 | u32 irq_gem_seqno; /* last seq seem at irq time */ | 57 | spinlock_t irq_lock; |
39 | u32 waiting_gem_seqno; | 58 | u32 irq_refcount; |
40 | int user_irq_refcount; | 59 | u32 irq_mask; |
41 | void (*user_irq_get)(struct drm_device *dev, | 60 | u32 irq_seqno; /* last seq seem at irq time */ |
42 | struct intel_ring_buffer *ring); | 61 | u32 waiting_seqno; |
43 | void (*user_irq_put)(struct drm_device *dev, | 62 | u32 sync_seqno[I915_NUM_RINGS-1]; |
44 | struct intel_ring_buffer *ring); | 63 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
64 | void (*irq_put)(struct intel_ring_buffer *ring); | ||
45 | 65 | ||
46 | int (*init)(struct drm_device *dev, | 66 | int (*init)(struct intel_ring_buffer *ring); |
47 | struct intel_ring_buffer *ring); | ||
48 | 67 | ||
49 | void (*write_tail)(struct drm_device *dev, | 68 | void (*write_tail)(struct intel_ring_buffer *ring, |
50 | struct intel_ring_buffer *ring, | ||
51 | u32 value); | 69 | u32 value); |
52 | void (*flush)(struct drm_device *dev, | 70 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
53 | struct intel_ring_buffer *ring, | 71 | u32 invalidate_domains, |
54 | u32 invalidate_domains, | 72 | u32 flush_domains); |
55 | u32 flush_domains); | 73 | int (*add_request)(struct intel_ring_buffer *ring, |
56 | u32 (*add_request)(struct drm_device *dev, | 74 | u32 *seqno); |
57 | struct intel_ring_buffer *ring, | 75 | u32 (*get_seqno)(struct intel_ring_buffer *ring); |
58 | u32 flush_domains); | 76 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, |
59 | u32 (*get_seqno)(struct drm_device *dev, | 77 | u32 offset, u32 length); |
60 | struct intel_ring_buffer *ring); | ||
61 | int (*dispatch_gem_execbuffer)(struct drm_device *dev, | ||
62 | struct intel_ring_buffer *ring, | ||
63 | struct drm_i915_gem_execbuffer2 *exec, | ||
64 | struct drm_clip_rect *cliprects, | ||
65 | uint64_t exec_offset); | ||
66 | void (*cleanup)(struct intel_ring_buffer *ring); | 78 | void (*cleanup)(struct intel_ring_buffer *ring); |
67 | 79 | ||
68 | /** | 80 | /** |
@@ -95,7 +107,7 @@ struct intel_ring_buffer { | |||
95 | /** | 107 | /** |
96 | * Do we have some not yet emitted requests outstanding? | 108 | * Do we have some not yet emitted requests outstanding? |
97 | */ | 109 | */ |
98 | bool outstanding_lazy_request; | 110 | u32 outstanding_lazy_request; |
99 | 111 | ||
100 | wait_queue_head_t irq_queue; | 112 | wait_queue_head_t irq_queue; |
101 | drm_local_map_t map; | 113 | drm_local_map_t map; |
@@ -104,44 +116,57 @@ struct intel_ring_buffer { | |||
104 | }; | 116 | }; |
105 | 117 | ||
106 | static inline u32 | 118 | static inline u32 |
119 | intel_ring_sync_index(struct intel_ring_buffer *ring, | ||
120 | struct intel_ring_buffer *other) | ||
121 | { | ||
122 | int idx; | ||
123 | |||
124 | /* | ||
125 | * cs -> 0 = vcs, 1 = bcs | ||
126 | * vcs -> 0 = bcs, 1 = cs, | ||
127 | * bcs -> 0 = cs, 1 = vcs. | ||
128 | */ | ||
129 | |||
130 | idx = (other - ring) - 1; | ||
131 | if (idx < 0) | ||
132 | idx += I915_NUM_RINGS; | ||
133 | |||
134 | return idx; | ||
135 | } | ||
136 | |||
137 | static inline u32 | ||
107 | intel_read_status_page(struct intel_ring_buffer *ring, | 138 | intel_read_status_page(struct intel_ring_buffer *ring, |
108 | int reg) | 139 | int reg) |
109 | { | 140 | { |
110 | u32 *regs = ring->status_page.page_addr; | 141 | return ioread32(ring->status_page.page_addr + reg); |
111 | return regs[reg]; | ||
112 | } | 142 | } |
113 | 143 | ||
114 | int intel_init_ring_buffer(struct drm_device *dev, | 144 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
115 | struct intel_ring_buffer *ring); | 145 | int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); |
116 | void intel_cleanup_ring_buffer(struct drm_device *dev, | 146 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
117 | struct intel_ring_buffer *ring); | 147 | |
118 | int intel_wait_ring_buffer(struct drm_device *dev, | 148 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, |
119 | struct intel_ring_buffer *ring, int n); | 149 | u32 data) |
120 | void intel_ring_begin(struct drm_device *dev, | ||
121 | struct intel_ring_buffer *ring, int n); | ||
122 | |||
123 | static inline void intel_ring_emit(struct drm_device *dev, | ||
124 | struct intel_ring_buffer *ring, | ||
125 | unsigned int data) | ||
126 | { | 150 | { |
127 | unsigned int *virt = ring->virtual_start + ring->tail; | 151 | iowrite32(data, ring->virtual_start + ring->tail); |
128 | *virt = data; | ||
129 | ring->tail += 4; | 152 | ring->tail += 4; |
130 | } | 153 | } |
131 | 154 | ||
132 | void intel_ring_advance(struct drm_device *dev, | 155 | void intel_ring_advance(struct intel_ring_buffer *ring); |
133 | struct intel_ring_buffer *ring); | ||
134 | 156 | ||
135 | u32 intel_ring_get_seqno(struct drm_device *dev, | 157 | u32 intel_ring_get_seqno(struct intel_ring_buffer *ring); |
136 | struct intel_ring_buffer *ring); | 158 | int intel_ring_sync(struct intel_ring_buffer *ring, |
159 | struct intel_ring_buffer *to, | ||
160 | u32 seqno); | ||
137 | 161 | ||
138 | int intel_init_render_ring_buffer(struct drm_device *dev); | 162 | int intel_init_render_ring_buffer(struct drm_device *dev); |
139 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | 163 | int intel_init_bsd_ring_buffer(struct drm_device *dev); |
140 | int intel_init_blt_ring_buffer(struct drm_device *dev); | 164 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
141 | 165 | ||
142 | u32 intel_ring_get_active_head(struct drm_device *dev, | 166 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
143 | struct intel_ring_buffer *ring); | 167 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); |
144 | void intel_ring_setup_status_page(struct drm_device *dev, | 168 | |
145 | struct intel_ring_buffer *ring); | 169 | /* DRI warts */ |
170 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); | ||
146 | 171 | ||
147 | #endif /* _INTEL_RINGBUFFER_H_ */ | 172 | #endif /* _INTEL_RINGBUFFER_H_ */ |