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path: root/drivers/gpu/drm/i915/intel_ringbuffer.h
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.h')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h42
1 files changed, 35 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 6d6fde85a636..f23cc5f037a6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -14,22 +14,23 @@ struct intel_hw_status_page {
14 struct drm_i915_gem_object *obj; 14 struct drm_i915_gem_object *obj;
15}; 15};
16 16
17#define I915_RING_READ(reg) i915_safe_read(dev_priv, reg) 17#define I915_RING_READ(reg) i915_gt_read(dev_priv, reg)
18#define I915_RING_WRITE(reg, val) i915_gt_write(dev_priv, reg, val)
18 19
19#define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base)) 20#define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
20#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) 21#define I915_WRITE_TAIL(ring, val) I915_RING_WRITE(RING_TAIL((ring)->mmio_base), val)
21 22
22#define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base)) 23#define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
23#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) 24#define I915_WRITE_START(ring, val) I915_RING_WRITE(RING_START((ring)->mmio_base), val)
24 25
25#define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base)) 26#define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base))
26#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) 27#define I915_WRITE_HEAD(ring, val) I915_RING_WRITE(RING_HEAD((ring)->mmio_base), val)
27 28
28#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base)) 29#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
29#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) 30#define I915_WRITE_CTL(ring, val) I915_RING_WRITE(RING_CTL((ring)->mmio_base), val)
30 31
31#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
32#define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base)) 32#define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
33#define I915_WRITE_IMR(ring, val) I915_RING_WRITE(RING_IMR((ring)->mmio_base), val)
33 34
34#define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base)) 35#define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
35#define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base)) 36#define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
@@ -43,7 +44,7 @@ struct intel_ring_buffer {
43 RING_BLT = 0x4, 44 RING_BLT = 0x4,
44 } id; 45 } id;
45 u32 mmio_base; 46 u32 mmio_base;
46 void *virtual_start; 47 void __iomem *virtual_start;
47 struct drm_device *dev; 48 struct drm_device *dev;
48 struct drm_i915_gem_object *obj; 49 struct drm_i915_gem_object *obj;
49 50
@@ -58,6 +59,7 @@ struct intel_ring_buffer {
58 u32 irq_refcount; 59 u32 irq_refcount;
59 u32 irq_mask; 60 u32 irq_mask;
60 u32 irq_seqno; /* last seq seem at irq time */ 61 u32 irq_seqno; /* last seq seem at irq time */
62 u32 trace_irq_seqno;
61 u32 waiting_seqno; 63 u32 waiting_seqno;
62 u32 sync_seqno[I915_NUM_RINGS-1]; 64 u32 sync_seqno[I915_NUM_RINGS-1];
63 bool __must_check (*irq_get)(struct intel_ring_buffer *ring); 65 bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
@@ -141,6 +143,26 @@ intel_read_status_page(struct intel_ring_buffer *ring,
141 return ioread32(ring->status_page.page_addr + reg); 143 return ioread32(ring->status_page.page_addr + reg);
142} 144}
143 145
146/**
147 * Reads a dword out of the status page, which is written to from the command
148 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
149 * MI_STORE_DATA_IMM.
150 *
151 * The following dwords have a reserved meaning:
152 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
153 * 0x04: ring 0 head pointer
154 * 0x05: ring 1 head pointer (915-class)
155 * 0x06: ring 2 head pointer (915-class)
156 * 0x10-0x1b: Context status DWords (GM45)
157 * 0x1f: Last written status offset. (GM45)
158 *
159 * The area from dword 0x20 to 0x3ff is available for driver usage.
160 */
161#define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg)
162#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
163#define I915_GEM_HWS_INDEX 0x20
164#define I915_BREADCRUMB_INDEX 0x21
165
144void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); 166void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
145int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); 167int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
146int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); 168int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
@@ -166,6 +188,12 @@ int intel_init_blt_ring_buffer(struct drm_device *dev);
166u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); 188u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
167void intel_ring_setup_status_page(struct intel_ring_buffer *ring); 189void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
168 190
191static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
192{
193 if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
194 ring->trace_irq_seqno = seqno;
195}
196
169/* DRI warts */ 197/* DRI warts */
170int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); 198int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
171 199