1 files changed, 2 insertions, 39 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cd79c3843452..e9858d2e92d0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -317,29 +317,6 @@ gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
         return 0;
 }
 
-static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
-{
-        int ret;
-
-        if (!ring->fbc_dirty)
-                return 0;
-
-        ret = intel_ring_begin(ring, 6);
-        if (ret)
-                return ret;
-        /* WaFbcNukeOn3DBlt:ivb/hsw */
-        intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
-        intel_ring_emit(ring, MSG_FBC_REND_STATE);
-        intel_ring_emit(ring, value);
-        intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
-        intel_ring_emit(ring, MSG_FBC_REND_STATE);
-        intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
-        intel_ring_advance(ring);
-
-        ring->fbc_dirty = false;
-        return 0;
-}
-
 static int
 gen7_render_ring_flush(struct intel_engine_cs *ring,
                        u32 invalidate_domains, u32 flush_domains)
@@ -398,9 +375,6 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
         intel_ring_emit(ring, 0);
         intel_ring_advance(ring);
 
-        if (!invalidate_domains && flush_domains)
-                return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
-
         return 0;
 }
 
@@ -462,9 +436,6 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
         if (ret)
                 return ret;
 
-        if (!invalidate_domains && flush_domains)
-                return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
-
         return 0;
 }
 
@@ -2477,7 +2448,6 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,
                            u32 invalidate, u32 flush)
 {
         struct drm_device *dev = ring->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
         uint32_t cmd;
         int ret;
 
@@ -2486,7 +2456,7 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,
                 return ret;
 
         cmd = MI_FLUSH_DW;
-        if (INTEL_INFO(ring->dev)->gen >= 8)
+        if (INTEL_INFO(dev)->gen >= 8)
                 cmd += 1;
 
         /* We always require a command barrier so that subsequent
@@ -2506,7 +2476,7 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,
                 cmd |= MI_INVALIDATE_TLB;
         intel_ring_emit(ring, cmd);
         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
-        if (INTEL_INFO(ring->dev)->gen >= 8) {
+        if (INTEL_INFO(dev)->gen >= 8) {
                 intel_ring_emit(ring, 0); /* upper addr */
                 intel_ring_emit(ring, 0); /* value */
         } else  {
@@ -2515,13 +2485,6 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,
         }
         intel_ring_advance(ring);
 
-        if (!invalidate && flush) {
-                if (IS_GEN7(dev))
-                        return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
-                else if (IS_BROADWELL(dev))
-                        dev_priv->fbc.need_sw_cache_clean = true;
-        }
-
         return 0;
 }