1 files changed, 177 insertions, 17 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2dec134f75eb..b620337e6d67 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -360,6 +360,47 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
         return 0;
 }
 
+static int
+gen8_render_ring_flush(struct intel_ring_buffer *ring,
+                       u32 invalidate_domains, u32 flush_domains)
+{
+        u32 flags = 0;
+        u32 scratch_addr = ring->scratch.gtt_offset + 128;
+        int ret;
+
+        flags |= PIPE_CONTROL_CS_STALL;
+
+        if (flush_domains) {
+                flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+                flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+        }
+        if (invalidate_domains) {
+                flags |= PIPE_CONTROL_TLB_INVALIDATE;
+                flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_QW_WRITE;
+                flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+        }
+
+        ret = intel_ring_begin(ring, 6);
+        if (ret)
+                return ret;
+
+        intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+        intel_ring_emit(ring, flags);
+        intel_ring_emit(ring, scratch_addr);
+        intel_ring_emit(ring, 0);
+        intel_ring_emit(ring, 0);
+        intel_ring_emit(ring, 0);
+        intel_ring_advance(ring);
+
+        return 0;
+
+}
+
 static void ring_write_tail(struct intel_ring_buffer *ring,
                             u32 value)
 {
@@ -1066,6 +1107,52 @@ hsw_vebox_put_irq(struct intel_ring_buffer *ring)
         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 }
 
+static bool
+gen8_ring_get_irq(struct intel_ring_buffer *ring)
+{
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned long flags;
+
+        if (!dev->irq_enabled)
+                return false;
+
+        spin_lock_irqsave(&dev_priv->irq_lock, flags);
+        if (ring->irq_refcount++ == 0) {
+                if (HAS_L3_DPF(dev) && ring->id == RCS) {
+                        I915_WRITE_IMR(ring,
+                                       ~(ring->irq_enable_mask |
+                                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
+                } else {
+                        I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
+                }
+                POSTING_READ(RING_IMR(ring->mmio_base));
+        }
+        spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+
+        return true;
+}
+
+static void
+gen8_ring_put_irq(struct intel_ring_buffer *ring)
+{
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned long flags;
+
+        spin_lock_irqsave(&dev_priv->irq_lock, flags);
+        if (--ring->irq_refcount == 0) {
+                if (HAS_L3_DPF(dev) && ring->id == RCS) {
+                        I915_WRITE_IMR(ring,
+                                       ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
+                } else {
+                        I915_WRITE_IMR(ring, ~0);
+                }
+                POSTING_READ(RING_IMR(ring->mmio_base));
+        }
+        spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+}
+
 static int
 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
                          u32 offset, u32 length,
@@ -1624,6 +1711,8 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
                 return ret;
 
         cmd = MI_FLUSH_DW;
+        if (INTEL_INFO(ring->dev)->gen >= 8)
+                cmd += 1;
         /*
          * Bspec vol 1c.5 - video engine command streamer:
          * "If ENABLED, all TLBs will be invalidated once the flush
@@ -1635,9 +1724,38 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
         intel_ring_emit(ring, cmd);
         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
+        if (INTEL_INFO(ring->dev)->gen >= 8) {
+                intel_ring_emit(ring, 0); /* upper addr */
+                intel_ring_emit(ring, 0); /* value */
+        } else  {
+                intel_ring_emit(ring, 0);
+                intel_ring_emit(ring, MI_NOOP);
+        }
+        intel_ring_advance(ring);
+        return 0;
+}
+
+static int
+gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
+                              u32 offset, u32 len,
+                              unsigned flags)
+{
+        struct drm_i915_private *dev_priv = ring->dev->dev_private;
+        bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
+                !(flags & I915_DISPATCH_SECURE);
+        int ret;
+
+        ret = intel_ring_begin(ring, 4);
+        if (ret)
+                return ret;
+
+        /* FIXME(BDW): Address space and security selectors. */
+        intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
+        intel_ring_emit(ring, offset);
         intel_ring_emit(ring, 0);
         intel_ring_emit(ring, MI_NOOP);
         intel_ring_advance(ring);
+
         return 0;
 }
 
@@ -1697,6 +1815,8 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
                 return ret;
 
         cmd = MI_FLUSH_DW;
+        if (INTEL_INFO(ring->dev)->gen >= 8)
+                cmd += 1;
         /*
          * Bspec vol 1c.3 - blitter engine command streamer:
          * "If ENABLED, all TLBs will be invalidated once the flush
@@ -1708,8 +1828,13 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
                         MI_FLUSH_DW_OP_STOREDW;
         intel_ring_emit(ring, cmd);
         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
-        intel_ring_emit(ring, 0);
-        intel_ring_emit(ring, MI_NOOP);
+        if (INTEL_INFO(ring->dev)->gen >= 8) {
+                intel_ring_emit(ring, 0); /* upper addr */
+                intel_ring_emit(ring, 0); /* value */
+        } else  {
+                intel_ring_emit(ring, 0);
+                intel_ring_emit(ring, MI_NOOP);
+        }
         intel_ring_advance(ring);
 
         if (IS_GEN7(dev) && flush)
@@ -1732,8 +1857,14 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
                 ring->flush = gen7_render_ring_flush;
                 if (INTEL_INFO(dev)->gen == 6)
                         ring->flush = gen6_render_ring_flush;
-                ring->irq_get = gen6_ring_get_irq;
-                ring->irq_put = gen6_ring_put_irq;
+                if (INTEL_INFO(dev)->gen >= 8) {
+                        ring->flush = gen8_render_ring_flush;
+                        ring->irq_get = gen8_ring_get_irq;
+                        ring->irq_put = gen8_ring_put_irq;
+                } else {
+                        ring->irq_get = gen6_ring_get_irq;
+                        ring->irq_put = gen6_ring_put_irq;
+                }
                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
                 ring->get_seqno = gen6_ring_get_seqno;
                 ring->set_seqno = ring_set_seqno;
@@ -1775,6 +1906,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
         ring->write_tail = ring_write_tail;
         if (IS_HASWELL(dev))
                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
+        else if (IS_GEN8(dev))
+                ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
         else if (INTEL_INFO(dev)->gen >= 6)
                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
         else if (INTEL_INFO(dev)->gen >= 4)
@@ -1888,7 +2021,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
         ring->id = VCS;
 
         ring->write_tail = ring_write_tail;
-        if (IS_GEN6(dev) || IS_GEN7(dev)) {
+        if (INTEL_INFO(dev)->gen >= 6) {
                 ring->mmio_base = GEN6_BSD_RING_BASE;
                 /* gen6 bsd needs a special wa for tail updates */
                 if (IS_GEN6(dev))
@@ -1897,10 +2030,20 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
                 ring->add_request = gen6_add_request;
                 ring->get_seqno = gen6_ring_get_seqno;
                 ring->set_seqno = ring_set_seqno;
-                ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
-                ring->irq_get = gen6_ring_get_irq;
-                ring->irq_put = gen6_ring_put_irq;
-                ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
+                if (INTEL_INFO(dev)->gen >= 8) {
+                        ring->irq_enable_mask =
+                                GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
+                        ring->irq_get = gen8_ring_get_irq;
+                        ring->irq_put = gen8_ring_put_irq;
+                        ring->dispatch_execbuffer =
+                                gen8_ring_dispatch_execbuffer;
+                } else {
+                        ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
+                        ring->irq_get = gen6_ring_get_irq;
+                        ring->irq_put = gen6_ring_put_irq;
+                        ring->dispatch_execbuffer =
+                                gen6_ring_dispatch_execbuffer;
+                }
                 ring->sync_to = gen6_ring_sync;
                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
@@ -1946,10 +2089,18 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
         ring->add_request = gen6_add_request;
         ring->get_seqno = gen6_ring_get_seqno;
         ring->set_seqno = ring_set_seqno;
-        ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
-        ring->irq_get = gen6_ring_get_irq;
-        ring->irq_put = gen6_ring_put_irq;
-        ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
+        if (INTEL_INFO(dev)->gen >= 8) {
+                ring->irq_enable_mask =
+                        GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
+                ring->irq_get = gen8_ring_get_irq;
+                ring->irq_put = gen8_ring_put_irq;
+                ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
+        } else {
+                ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
+                ring->irq_get = gen6_ring_get_irq;
+                ring->irq_put = gen6_ring_put_irq;
+                ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
+        }
         ring->sync_to = gen6_ring_sync;
         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
@@ -1978,10 +2129,19 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
         ring->add_request = gen6_add_request;
         ring->get_seqno = gen6_ring_get_seqno;
         ring->set_seqno = ring_set_seqno;
-        ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
-        ring->irq_get = hsw_vebox_get_irq;
-        ring->irq_put = hsw_vebox_put_irq;
-        ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
+
+        if (INTEL_INFO(dev)->gen >= 8) {
+                ring->irq_enable_mask =
+                        GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
+                ring->irq_get = gen8_ring_get_irq;
+                ring->irq_put = gen8_ring_put_irq;
+                ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
+        } else {
+                ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
+                ring->irq_get = hsw_vebox_get_irq;
+                ring->irq_put = hsw_vebox_put_irq;
+                ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
+        }
         ring->sync_to = gen6_ring_sync;
         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;