1 files changed, 0 insertions, 30 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 99bc1f33bfcb..ed9912ca1f82 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3765,34 +3765,6 @@ void intel_init_pm(struct drm_device *dev)
 
         /* For FIFO watermark updates */
         if (HAS_PCH_SPLIT(dev)) {
-                dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
-                dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
-
-                /* IVB configs may use multi-threaded forcewake */
-                if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
-                        u32     ecobus;
-
-                        /* A small trick here - if the bios hasn't configured MT forcewake,
-                         * and if the device is in RC6, then force_wake_mt_get will not wake
-                         * the device and the ECOBUS read will return zero. Which will be
-                         * (correctly) interpreted by the test below as MT forcewake being
-                         * disabled.
-                         */
-                        mutex_lock(&dev->struct_mutex);
-                        __gen6_gt_force_wake_mt_get(dev_priv);
-                        ecobus = I915_READ_NOTRACE(ECOBUS);
-                        __gen6_gt_force_wake_mt_put(dev_priv);
-                        mutex_unlock(&dev->struct_mutex);
-
-                        if (ecobus & FORCEWAKE_MT_ENABLE) {
-                                DRM_DEBUG_KMS("Using MT version of forcewake\n");
-                                dev_priv->display.force_wake_get =
-                                        __gen6_gt_force_wake_mt_get;
-                                dev_priv->display.force_wake_put =
-                                        __gen6_gt_force_wake_mt_put;
-                        }
-                }
-
                 if (HAS_PCH_IBX(dev))
                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
                 else if (HAS_PCH_CPT(dev))
@@ -3848,8 +3820,6 @@ void intel_init_pm(struct drm_device *dev)
                 dev_priv->display.update_wm = valleyview_update_wm;
                 dev_priv->display.init_clock_gating =
                         valleyview_init_clock_gating;
-                dev_priv->display.force_wake_get = vlv_force_wake_get;
-                dev_priv->display.force_wake_put = vlv_force_wake_put;
         } else if (IS_PINEVIEW(dev)) {
                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
                                             dev_priv->is_ddr3,