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path: root/drivers/gpu/drm/i915/intel_pm.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c12
1 files changed, 3 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8f8d84005779..2edb8c77013e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3196,16 +3196,10 @@ static void valleyview_disable_rps(struct drm_device *dev)
3196 3196
3197static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 3197static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3198{ 3198{
3199 if (IS_GEN6(dev))
3200 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3201
3202 if (IS_HASWELL(dev))
3203 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3204
3205 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", 3199 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3206 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 3200 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3207 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 3201 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3208 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 3202 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3209} 3203}
3210 3204
3211int intel_enable_rc6(const struct drm_device *dev) 3205int intel_enable_rc6(const struct drm_device *dev)