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path: root/drivers/gpu/drm/i915/intel_i2c.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_i2c.c')
-rw-r--r--drivers/gpu/drm/i915/intel_i2c.c210
1 files changed, 92 insertions, 118 deletions
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index d30ccccb9d73..601c86e664af 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -37,7 +37,7 @@
37 37
38/* Intel GPIO access functions */ 38/* Intel GPIO access functions */
39 39
40#define I2C_RISEFALL_TIME 20 40#define I2C_RISEFALL_TIME 10
41 41
42static inline struct intel_gmbus * 42static inline struct intel_gmbus *
43to_intel_gmbus(struct i2c_adapter *i2c) 43to_intel_gmbus(struct i2c_adapter *i2c)
@@ -45,13 +45,6 @@ to_intel_gmbus(struct i2c_adapter *i2c)
45 return container_of(i2c, struct intel_gmbus, adapter); 45 return container_of(i2c, struct intel_gmbus, adapter);
46} 46}
47 47
48struct intel_gpio {
49 struct i2c_adapter adapter;
50 struct i2c_algo_bit_data algo;
51 struct drm_i915_private *dev_priv;
52 u32 reg;
53};
54
55void 48void
56intel_i2c_reset(struct drm_device *dev) 49intel_i2c_reset(struct drm_device *dev)
57{ 50{
@@ -78,15 +71,15 @@ static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
78 I915_WRITE(DSPCLK_GATE_D, val); 71 I915_WRITE(DSPCLK_GATE_D, val);
79} 72}
80 73
81static u32 get_reserved(struct intel_gpio *gpio) 74static u32 get_reserved(struct intel_gmbus *bus)
82{ 75{
83 struct drm_i915_private *dev_priv = gpio->dev_priv; 76 struct drm_i915_private *dev_priv = bus->dev_priv;
84 struct drm_device *dev = dev_priv->dev; 77 struct drm_device *dev = dev_priv->dev;
85 u32 reserved = 0; 78 u32 reserved = 0;
86 79
87 /* On most chips, these bits must be preserved in software. */ 80 /* On most chips, these bits must be preserved in software. */
88 if (!IS_I830(dev) && !IS_845G(dev)) 81 if (!IS_I830(dev) && !IS_845G(dev))
89 reserved = I915_READ_NOTRACE(gpio->reg) & 82 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
90 (GPIO_DATA_PULLUP_DISABLE | 83 (GPIO_DATA_PULLUP_DISABLE |
91 GPIO_CLOCK_PULLUP_DISABLE); 84 GPIO_CLOCK_PULLUP_DISABLE);
92 85
@@ -95,29 +88,29 @@ static u32 get_reserved(struct intel_gpio *gpio)
95 88
96static int get_clock(void *data) 89static int get_clock(void *data)
97{ 90{
98 struct intel_gpio *gpio = data; 91 struct intel_gmbus *bus = data;
99 struct drm_i915_private *dev_priv = gpio->dev_priv; 92 struct drm_i915_private *dev_priv = bus->dev_priv;
100 u32 reserved = get_reserved(gpio); 93 u32 reserved = get_reserved(bus);
101 I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK); 94 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
102 I915_WRITE_NOTRACE(gpio->reg, reserved); 95 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
103 return (I915_READ_NOTRACE(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0; 96 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
104} 97}
105 98
106static int get_data(void *data) 99static int get_data(void *data)
107{ 100{
108 struct intel_gpio *gpio = data; 101 struct intel_gmbus *bus = data;
109 struct drm_i915_private *dev_priv = gpio->dev_priv; 102 struct drm_i915_private *dev_priv = bus->dev_priv;
110 u32 reserved = get_reserved(gpio); 103 u32 reserved = get_reserved(bus);
111 I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_DATA_DIR_MASK); 104 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
112 I915_WRITE_NOTRACE(gpio->reg, reserved); 105 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
113 return (I915_READ_NOTRACE(gpio->reg) & GPIO_DATA_VAL_IN) != 0; 106 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
114} 107}
115 108
116static void set_clock(void *data, int state_high) 109static void set_clock(void *data, int state_high)
117{ 110{
118 struct intel_gpio *gpio = data; 111 struct intel_gmbus *bus = data;
119 struct drm_i915_private *dev_priv = gpio->dev_priv; 112 struct drm_i915_private *dev_priv = bus->dev_priv;
120 u32 reserved = get_reserved(gpio); 113 u32 reserved = get_reserved(bus);
121 u32 clock_bits; 114 u32 clock_bits;
122 115
123 if (state_high) 116 if (state_high)
@@ -126,15 +119,15 @@ static void set_clock(void *data, int state_high)
126 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 119 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
127 GPIO_CLOCK_VAL_MASK; 120 GPIO_CLOCK_VAL_MASK;
128 121
129 I915_WRITE_NOTRACE(gpio->reg, reserved | clock_bits); 122 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
130 POSTING_READ(gpio->reg); 123 POSTING_READ(bus->gpio_reg);
131} 124}
132 125
133static void set_data(void *data, int state_high) 126static void set_data(void *data, int state_high)
134{ 127{
135 struct intel_gpio *gpio = data; 128 struct intel_gmbus *bus = data;
136 struct drm_i915_private *dev_priv = gpio->dev_priv; 129 struct drm_i915_private *dev_priv = bus->dev_priv;
137 u32 reserved = get_reserved(gpio); 130 u32 reserved = get_reserved(bus);
138 u32 data_bits; 131 u32 data_bits;
139 132
140 if (state_high) 133 if (state_high)
@@ -143,13 +136,14 @@ static void set_data(void *data, int state_high)
143 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 136 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
144 GPIO_DATA_VAL_MASK; 137 GPIO_DATA_VAL_MASK;
145 138
146 I915_WRITE_NOTRACE(gpio->reg, reserved | data_bits); 139 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
147 POSTING_READ(gpio->reg); 140 POSTING_READ(bus->gpio_reg);
148} 141}
149 142
150static struct i2c_adapter * 143static bool
151intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin) 144intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
152{ 145{
146 struct drm_i915_private *dev_priv = bus->dev_priv;
153 static const int map_pin_to_reg[] = { 147 static const int map_pin_to_reg[] = {
154 0, 148 0,
155 GPIOB, 149 GPIOB,
@@ -160,65 +154,48 @@ intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
160 0, 154 0,
161 GPIOF, 155 GPIOF,
162 }; 156 };
163 struct intel_gpio *gpio; 157 struct i2c_algo_bit_data *algo;
164 158
165 if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin]) 159 if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
166 return NULL; 160 return false;
167 161
168 gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL); 162 algo = &bus->bit_algo;
169 if (gpio == NULL)
170 return NULL;
171 163
172 gpio->reg = map_pin_to_reg[pin]; 164 bus->gpio_reg = map_pin_to_reg[pin];
173 if (HAS_PCH_SPLIT(dev_priv->dev)) 165 if (HAS_PCH_SPLIT(dev_priv->dev))
174 gpio->reg += PCH_GPIOA - GPIOA; 166 bus->gpio_reg += PCH_GPIOA - GPIOA;
175 gpio->dev_priv = dev_priv; 167
176 168 bus->adapter.algo_data = algo;
177 snprintf(gpio->adapter.name, sizeof(gpio->adapter.name), 169 algo->setsda = set_data;
178 "i915 GPIO%c", "?BACDE?F"[pin]); 170 algo->setscl = set_clock;
179 gpio->adapter.owner = THIS_MODULE; 171 algo->getsda = get_data;
180 gpio->adapter.algo_data = &gpio->algo; 172 algo->getscl = get_clock;
181 gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev; 173 algo->udelay = I2C_RISEFALL_TIME;
182 gpio->algo.setsda = set_data; 174 algo->timeout = usecs_to_jiffies(2200);
183 gpio->algo.setscl = set_clock; 175 algo->data = bus;
184 gpio->algo.getsda = get_data; 176
185 gpio->algo.getscl = get_clock; 177 return true;
186 gpio->algo.udelay = I2C_RISEFALL_TIME;
187 gpio->algo.timeout = usecs_to_jiffies(2200);
188 gpio->algo.data = gpio;
189
190 if (i2c_bit_add_bus(&gpio->adapter))
191 goto out_free;
192
193 return &gpio->adapter;
194
195out_free:
196 kfree(gpio);
197 return NULL;
198} 178}
199 179
200static int 180static int
201intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv, 181intel_i2c_quirk_xfer(struct intel_gmbus *bus,
202 struct i2c_adapter *adapter,
203 struct i2c_msg *msgs, 182 struct i2c_msg *msgs,
204 int num) 183 int num)
205{ 184{
206 struct intel_gpio *gpio = container_of(adapter, 185 struct drm_i915_private *dev_priv = bus->dev_priv;
207 struct intel_gpio,
208 adapter);
209 int ret; 186 int ret;
210 187
211 intel_i2c_reset(dev_priv->dev); 188 intel_i2c_reset(dev_priv->dev);
212 189
213 intel_i2c_quirk_set(dev_priv, true); 190 intel_i2c_quirk_set(dev_priv, true);
214 set_data(gpio, 1); 191 set_data(bus, 1);
215 set_clock(gpio, 1); 192 set_clock(bus, 1);
216 udelay(I2C_RISEFALL_TIME); 193 udelay(I2C_RISEFALL_TIME);
217 194
218 ret = adapter->algo->master_xfer(adapter, msgs, num); 195 ret = i2c_bit_algo.master_xfer(&bus->adapter, msgs, num);
219 196
220 set_data(gpio, 1); 197 set_data(bus, 1);
221 set_clock(gpio, 1); 198 set_clock(bus, 1);
222 intel_i2c_quirk_set(dev_priv, false); 199 intel_i2c_quirk_set(dev_priv, false);
223 200
224 return ret; 201 return ret;
@@ -232,12 +209,15 @@ gmbus_xfer(struct i2c_adapter *adapter,
232 struct intel_gmbus *bus = container_of(adapter, 209 struct intel_gmbus *bus = container_of(adapter,
233 struct intel_gmbus, 210 struct intel_gmbus,
234 adapter); 211 adapter);
235 struct drm_i915_private *dev_priv = adapter->algo_data; 212 struct drm_i915_private *dev_priv = bus->dev_priv;
236 int i, reg_offset; 213 int i, reg_offset, ret;
237 214
238 if (bus->force_bit) 215 mutex_lock(&dev_priv->gmbus_mutex);
239 return intel_i2c_quirk_xfer(dev_priv, 216
240 bus->force_bit, msgs, num); 217 if (bus->force_bit) {
218 ret = intel_i2c_quirk_xfer(bus, msgs, num);
219 goto out;
220 }
241 221
242 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; 222 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
243 223
@@ -249,7 +229,8 @@ gmbus_xfer(struct i2c_adapter *adapter,
249 229
250 if (msgs[i].flags & I2C_M_RD) { 230 if (msgs[i].flags & I2C_M_RD) {
251 I915_WRITE(GMBUS1 + reg_offset, 231 I915_WRITE(GMBUS1 + reg_offset,
252 GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) | 232 GMBUS_CYCLE_WAIT |
233 (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
253 (len << GMBUS_BYTE_COUNT_SHIFT) | 234 (len << GMBUS_BYTE_COUNT_SHIFT) |
254 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | 235 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
255 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 236 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
@@ -278,7 +259,8 @@ gmbus_xfer(struct i2c_adapter *adapter,
278 259
279 I915_WRITE(GMBUS3 + reg_offset, val); 260 I915_WRITE(GMBUS3 + reg_offset, val);
280 I915_WRITE(GMBUS1 + reg_offset, 261 I915_WRITE(GMBUS1 + reg_offset,
281 (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) | 262 GMBUS_CYCLE_WAIT |
263 (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
282 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) | 264 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
283 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | 265 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
284 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 266 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
@@ -317,11 +299,15 @@ clear_err:
317 I915_WRITE(GMBUS1 + reg_offset, 0); 299 I915_WRITE(GMBUS1 + reg_offset, 0);
318 300
319done: 301done:
320 /* Mark the GMBUS interface as disabled. We will re-enable it at the 302 /* Mark the GMBUS interface as disabled after waiting for idle.
321 * start of the next xfer, till then let it sleep. 303 * We will re-enable it at the start of the next xfer,
304 * till then let it sleep.
322 */ 305 */
306 if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 10))
307 DRM_INFO("GMBUS timed out waiting for idle\n");
323 I915_WRITE(GMBUS0 + reg_offset, 0); 308 I915_WRITE(GMBUS0 + reg_offset, 0);
324 return i; 309 ret = i;
310 goto out;
325 311
326timeout: 312timeout:
327 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n", 313 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
@@ -329,23 +315,21 @@ timeout:
329 I915_WRITE(GMBUS0 + reg_offset, 0); 315 I915_WRITE(GMBUS0 + reg_offset, 0);
330 316
331 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ 317 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
332 bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff); 318 if (!bus->has_gpio) {
333 if (!bus->force_bit) 319 ret = -EIO;
334 return -ENOMEM; 320 } else {
335 321 bus->force_bit = true;
336 return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num); 322 ret = intel_i2c_quirk_xfer(bus, msgs, num);
323 }
324out:
325 mutex_unlock(&dev_priv->gmbus_mutex);
326 return ret;
337} 327}
338 328
339static u32 gmbus_func(struct i2c_adapter *adapter) 329static u32 gmbus_func(struct i2c_adapter *adapter)
340{ 330{
341 struct intel_gmbus *bus = container_of(adapter, 331 return i2c_bit_algo.functionality(adapter) &
342 struct intel_gmbus, 332 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
343 adapter);
344
345 if (bus->force_bit)
346 bus->force_bit->algo->functionality(bus->force_bit);
347
348 return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
349 /* I2C_FUNC_10BIT_ADDR | */ 333 /* I2C_FUNC_10BIT_ADDR | */
350 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 334 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
351 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 335 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
@@ -375,11 +359,13 @@ int intel_setup_gmbus(struct drm_device *dev)
375 struct drm_i915_private *dev_priv = dev->dev_private; 359 struct drm_i915_private *dev_priv = dev->dev_private;
376 int ret, i; 360 int ret, i;
377 361
378 dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS, 362 dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
379 GFP_KERNEL); 363 GFP_KERNEL);
380 if (dev_priv->gmbus == NULL) 364 if (dev_priv->gmbus == NULL)
381 return -ENOMEM; 365 return -ENOMEM;
382 366
367 mutex_init(&dev_priv->gmbus_mutex);
368
383 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 369 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
384 struct intel_gmbus *bus = &dev_priv->gmbus[i]; 370 struct intel_gmbus *bus = &dev_priv->gmbus[i];
385 371
@@ -391,7 +377,7 @@ int intel_setup_gmbus(struct drm_device *dev)
391 names[i]); 377 names[i]);
392 378
393 bus->adapter.dev.parent = &dev->pdev->dev; 379 bus->adapter.dev.parent = &dev->pdev->dev;
394 bus->adapter.algo_data = dev_priv; 380 bus->dev_priv = dev_priv;
395 381
396 bus->adapter.algo = &gmbus_algorithm; 382 bus->adapter.algo = &gmbus_algorithm;
397 ret = i2c_add_adapter(&bus->adapter); 383 ret = i2c_add_adapter(&bus->adapter);
@@ -401,8 +387,11 @@ int intel_setup_gmbus(struct drm_device *dev)
401 /* By default use a conservative clock rate */ 387 /* By default use a conservative clock rate */
402 bus->reg0 = i | GMBUS_RATE_100KHZ; 388 bus->reg0 = i | GMBUS_RATE_100KHZ;
403 389
390 bus->has_gpio = intel_gpio_setup(bus, i);
391
404 /* XXX force bit banging until GMBUS is fully debugged */ 392 /* XXX force bit banging until GMBUS is fully debugged */
405 bus->force_bit = intel_gpio_create(dev_priv, i); 393 if (bus->has_gpio && IS_GEN2(dev))
394 bus->force_bit = true;
406 } 395 }
407 396
408 intel_i2c_reset(dev_priv->dev); 397 intel_i2c_reset(dev_priv->dev);
@@ -430,19 +419,8 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
430{ 419{
431 struct intel_gmbus *bus = to_intel_gmbus(adapter); 420 struct intel_gmbus *bus = to_intel_gmbus(adapter);
432 421
433 if (force_bit) { 422 if (bus->has_gpio)
434 if (bus->force_bit == NULL) { 423 bus->force_bit = force_bit;
435 struct drm_i915_private *dev_priv = adapter->algo_data;
436 bus->force_bit = intel_gpio_create(dev_priv,
437 bus->reg0 & 0xff);
438 }
439 } else {
440 if (bus->force_bit) {
441 i2c_del_adapter(bus->force_bit);
442 kfree(bus->force_bit);
443 bus->force_bit = NULL;
444 }
445 }
446} 424}
447 425
448void intel_teardown_gmbus(struct drm_device *dev) 426void intel_teardown_gmbus(struct drm_device *dev)
@@ -455,10 +433,6 @@ void intel_teardown_gmbus(struct drm_device *dev)
455 433
456 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 434 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
457 struct intel_gmbus *bus = &dev_priv->gmbus[i]; 435 struct intel_gmbus *bus = &dev_priv->gmbus[i];
458 if (bus->force_bit) {
459 i2c_del_adapter(bus->force_bit);
460 kfree(bus->force_bit);
461 }
462 i2c_del_adapter(&bus->adapter); 436 i2c_del_adapter(&bus->adapter);
463 } 437 }
464 438