diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_i2c.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_i2c.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index c7eab724c418..c2649c7df14c 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c | |||
@@ -26,6 +26,7 @@ | |||
26 | * Eric Anholt <eric@anholt.net> | 26 | * Eric Anholt <eric@anholt.net> |
27 | */ | 27 | */ |
28 | #include <linux/i2c.h> | 28 | #include <linux/i2c.h> |
29 | #include <linux/slab.h> | ||
29 | #include <linux/i2c-id.h> | 30 | #include <linux/i2c-id.h> |
30 | #include <linux/i2c-algo-bit.h> | 31 | #include <linux/i2c-algo-bit.h> |
31 | #include "drmP.h" | 32 | #include "drmP.h" |
@@ -39,7 +40,7 @@ void intel_i2c_quirk_set(struct drm_device *dev, bool enable) | |||
39 | struct drm_i915_private *dev_priv = dev->dev_private; | 40 | struct drm_i915_private *dev_priv = dev->dev_private; |
40 | 41 | ||
41 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ | 42 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ |
42 | if (!IS_IGD(dev)) | 43 | if (!IS_PINEVIEW(dev)) |
43 | return; | 44 | return; |
44 | if (enable) | 45 | if (enable) |
45 | I915_WRITE(DSPCLK_GATE_D, | 46 | I915_WRITE(DSPCLK_GATE_D, |
@@ -118,6 +119,23 @@ static void set_data(void *data, int state_high) | |||
118 | udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */ | 119 | udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */ |
119 | } | 120 | } |
120 | 121 | ||
122 | /* Clears the GMBUS setup. Our driver doesn't make use of the GMBUS I2C | ||
123 | * engine, but if the BIOS leaves it enabled, then that can break our use | ||
124 | * of the bit-banging I2C interfaces. This is notably the case with the | ||
125 | * Mac Mini in EFI mode. | ||
126 | */ | ||
127 | void | ||
128 | intel_i2c_reset_gmbus(struct drm_device *dev) | ||
129 | { | ||
130 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
131 | |||
132 | if (HAS_PCH_SPLIT(dev)) { | ||
133 | I915_WRITE(PCH_GMBUS0, 0); | ||
134 | } else { | ||
135 | I915_WRITE(GMBUS0, 0); | ||
136 | } | ||
137 | } | ||
138 | |||
121 | /** | 139 | /** |
122 | * intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg | 140 | * intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg |
123 | * @dev: DRM device | 141 | * @dev: DRM device |
@@ -168,6 +186,8 @@ struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg, | |||
168 | if(i2c_bit_add_bus(&chan->adapter)) | 186 | if(i2c_bit_add_bus(&chan->adapter)) |
169 | goto out_free; | 187 | goto out_free; |
170 | 188 | ||
189 | intel_i2c_reset_gmbus(dev); | ||
190 | |||
171 | /* JJJ: raise SCL and SDA? */ | 191 | /* JJJ: raise SCL and SDA? */ |
172 | intel_i2c_quirk_set(dev, true); | 192 | intel_i2c_quirk_set(dev, true); |
173 | set_data(chan, 1); | 193 | set_data(chan, 1); |