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Diffstat (limited to 'drivers/gpu/drm/i915/intel_dsi_cmd.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_cmd.c427
1 files changed, 427 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
new file mode 100644
index 000000000000..7c40f981d2c7
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -0,0 +1,427 @@
1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <linux/export.h>
27#include <drm/drmP.h>
28#include <drm/drm_crtc.h>
29#include <video/mipi_display.h>
30#include "i915_drv.h"
31#include "intel_drv.h"
32#include "intel_dsi.h"
33#include "intel_dsi_cmd.h"
34
35/*
36 * XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and
37 * MIPI_COMMAND_ADDRESS registers.
38 *
39 * Apparently these registers provide a MIPI adapter level way to send (lots of)
40 * commands and data to the receiver, without having to write the commands and
41 * data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.
42 *
43 * Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and
44 * MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external
45 * framebuffer in command mode displays) these are just an optimization that can
46 * come later.
47 *
48 * For memory writes, these should probably be used for performance.
49 */
50
51static void print_stat(struct intel_dsi *intel_dsi)
52{
53 struct drm_encoder *encoder = &intel_dsi->base.base;
54 struct drm_device *dev = encoder->dev;
55 struct drm_i915_private *dev_priv = dev->dev_private;
56 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
57 enum pipe pipe = intel_crtc->pipe;
58 u32 val;
59
60 val = I915_READ(MIPI_INTR_STAT(pipe));
61
62#define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : ""
63 DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x"
64 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
65 "\n", pipe, val,
66 STAT_BIT(val, TEARING_EFFECT),
67 STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),
68 STAT_BIT(val, GEN_READ_DATA_AVAIL),
69 STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),
70 STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),
71 STAT_BIT(val, RX_PROT_VIOLATION),
72 STAT_BIT(val, RX_INVALID_TX_LENGTH),
73 STAT_BIT(val, ACK_WITH_NO_ERROR),
74 STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),
75 STAT_BIT(val, LP_RX_TIMEOUT),
76 STAT_BIT(val, HS_TX_TIMEOUT),
77 STAT_BIT(val, DPI_FIFO_UNDERRUN),
78 STAT_BIT(val, LOW_CONTENTION),
79 STAT_BIT(val, HIGH_CONTENTION),
80 STAT_BIT(val, TXDSI_VC_ID_INVALID),
81 STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),
82 STAT_BIT(val, TXCHECKSUM_ERROR),
83 STAT_BIT(val, TXECC_MULTIBIT_ERROR),
84 STAT_BIT(val, TXECC_SINGLE_BIT_ERROR),
85 STAT_BIT(val, TXFALSE_CONTROL_ERROR),
86 STAT_BIT(val, RXDSI_VC_ID_INVALID),
87 STAT_BIT(val, RXDSI_DATA_TYPE_NOT_REGOGNISED),
88 STAT_BIT(val, RXCHECKSUM_ERROR),
89 STAT_BIT(val, RXECC_MULTIBIT_ERROR),
90 STAT_BIT(val, RXECC_SINGLE_BIT_ERROR),
91 STAT_BIT(val, RXFALSE_CONTROL_ERROR),
92 STAT_BIT(val, RXHS_RECEIVE_TIMEOUT_ERROR),
93 STAT_BIT(val, RX_LP_TX_SYNC_ERROR),
94 STAT_BIT(val, RXEXCAPE_MODE_ENTRY_ERROR),
95 STAT_BIT(val, RXEOT_SYNC_ERROR),
96 STAT_BIT(val, RXSOT_SYNC_ERROR),
97 STAT_BIT(val, RXSOT_ERROR));
98#undef STAT_BIT
99}
100
101enum dsi_type {
102 DSI_DCS,
103 DSI_GENERIC,
104};
105
106/* enable or disable command mode hs transmissions */
107void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
108{
109 struct drm_encoder *encoder = &intel_dsi->base.base;
110 struct drm_device *dev = encoder->dev;
111 struct drm_i915_private *dev_priv = dev->dev_private;
112 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
113 enum pipe pipe = intel_crtc->pipe;
114 u32 temp;
115 u32 mask = DBI_FIFO_EMPTY;
116
117 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
118 DRM_ERROR("Timeout waiting for DBI FIFO empty\n");
119
120 temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe));
121 temp &= DBI_HS_LP_MODE_MASK;
122 I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE);
123
124 intel_dsi->hs = enable;
125}
126
127static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
128 u8 data_type, u16 data)
129{
130 struct drm_encoder *encoder = &intel_dsi->base.base;
131 struct drm_device *dev = encoder->dev;
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
134 enum pipe pipe = intel_crtc->pipe;
135 u32 ctrl_reg;
136 u32 ctrl;
137 u32 mask;
138
139 DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
140 channel, data_type, data);
141
142 if (intel_dsi->hs) {
143 ctrl_reg = MIPI_HS_GEN_CTRL(pipe);
144 mask = HS_CTRL_FIFO_FULL;
145 } else {
146 ctrl_reg = MIPI_LP_GEN_CTRL(pipe);
147 mask = LP_CTRL_FIFO_FULL;
148 }
149
150 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) {
151 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
152 print_stat(intel_dsi);
153 }
154
155 /*
156 * Note: This function is also used for long packets, with length passed
157 * as data, since SHORT_PACKET_PARAM_SHIFT ==
158 * LONG_PACKET_WORD_COUNT_SHIFT.
159 */
160 ctrl = data << SHORT_PACKET_PARAM_SHIFT |
161 channel << VIRTUAL_CHANNEL_SHIFT |
162 data_type << DATA_TYPE_SHIFT;
163
164 I915_WRITE(ctrl_reg, ctrl);
165
166 return 0;
167}
168
169static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
170 u8 data_type, const u8 *data, int len)
171{
172 struct drm_encoder *encoder = &intel_dsi->base.base;
173 struct drm_device *dev = encoder->dev;
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
176 enum pipe pipe = intel_crtc->pipe;
177 u32 data_reg;
178 int i, j, n;
179 u32 mask;
180
181 DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
182 channel, data_type, len);
183
184 if (intel_dsi->hs) {
185 data_reg = MIPI_HS_GEN_DATA(pipe);
186 mask = HS_DATA_FIFO_FULL;
187 } else {
188 data_reg = MIPI_LP_GEN_DATA(pipe);
189 mask = LP_DATA_FIFO_FULL;
190 }
191
192 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50))
193 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
194
195 for (i = 0; i < len; i += n) {
196 u32 val = 0;
197 n = min_t(int, len - i, 4);
198
199 for (j = 0; j < n; j++)
200 val |= *data++ << 8 * j;
201
202 I915_WRITE(data_reg, val);
203 /* XXX: check for data fifo full, once that is set, write 4
204 * dwords, then wait for not set, then continue. */
205 }
206
207 return dsi_vc_send_short(intel_dsi, channel, data_type, len);
208}
209
210static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
211 int channel, const u8 *data, int len,
212 enum dsi_type type)
213{
214 int ret;
215
216 if (len == 0) {
217 BUG_ON(type == DSI_GENERIC);
218 ret = dsi_vc_send_short(intel_dsi, channel,
219 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
220 0);
221 } else if (len == 1) {
222 ret = dsi_vc_send_short(intel_dsi, channel,
223 type == DSI_GENERIC ?
224 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
225 MIPI_DSI_DCS_SHORT_WRITE, data[0]);
226 } else if (len == 2) {
227 ret = dsi_vc_send_short(intel_dsi, channel,
228 type == DSI_GENERIC ?
229 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
230 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
231 (data[1] << 8) | data[0]);
232 } else {
233 ret = dsi_vc_send_long(intel_dsi, channel,
234 type == DSI_GENERIC ?
235 MIPI_DSI_GENERIC_LONG_WRITE :
236 MIPI_DSI_DCS_LONG_WRITE, data, len);
237 }
238
239 return ret;
240}
241
242int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
243 const u8 *data, int len)
244{
245 return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);
246}
247
248int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
249 const u8 *data, int len)
250{
251 return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);
252}
253
254static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
255 int channel, u8 dcs_cmd)
256{
257 return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
258 dcs_cmd);
259}
260
261static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
262 int channel, u8 *reqdata,
263 int reqlen)
264{
265 u16 data;
266 u8 data_type;
267
268 switch (reqlen) {
269 case 0:
270 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
271 data = 0;
272 break;
273 case 1:
274 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
275 data = reqdata[0];
276 break;
277 case 2:
278 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
279 data = (reqdata[1] << 8) | reqdata[0];
280 break;
281 default:
282 BUG();
283 }
284
285 return dsi_vc_send_short(intel_dsi, channel, data_type, data);
286}
287
288static int dsi_read_data_return(struct intel_dsi *intel_dsi,
289 u8 *buf, int buflen)
290{
291 struct drm_encoder *encoder = &intel_dsi->base.base;
292 struct drm_device *dev = encoder->dev;
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
295 enum pipe pipe = intel_crtc->pipe;
296 int i, len = 0;
297 u32 data_reg, val;
298
299 if (intel_dsi->hs) {
300 data_reg = MIPI_HS_GEN_DATA(pipe);
301 } else {
302 data_reg = MIPI_LP_GEN_DATA(pipe);
303 }
304
305 while (len < buflen) {
306 val = I915_READ(data_reg);
307 for (i = 0; i < 4 && len < buflen; i++, len++)
308 buf[len] = val >> 8 * i;
309 }
310
311 return len;
312}
313
314int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
315 u8 *buf, int buflen)
316{
317 struct drm_encoder *encoder = &intel_dsi->base.base;
318 struct drm_device *dev = encoder->dev;
319 struct drm_i915_private *dev_priv = dev->dev_private;
320 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
321 enum pipe pipe = intel_crtc->pipe;
322 u32 mask;
323 int ret;
324
325 /*
326 * XXX: should issue multiple read requests and reads if request is
327 * longer than MIPI_MAX_RETURN_PKT_SIZE
328 */
329
330 I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
331
332 ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);
333 if (ret)
334 return ret;
335
336 mask = GEN_READ_DATA_AVAIL;
337 if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
338 DRM_ERROR("Timeout waiting for read data.\n");
339
340 ret = dsi_read_data_return(intel_dsi, buf, buflen);
341 if (ret < 0)
342 return ret;
343
344 if (ret != buflen)
345 return -EIO;
346
347 return 0;
348}
349
350int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
351 u8 *reqdata, int reqlen, u8 *buf, int buflen)
352{
353 struct drm_encoder *encoder = &intel_dsi->base.base;
354 struct drm_device *dev = encoder->dev;
355 struct drm_i915_private *dev_priv = dev->dev_private;
356 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
357 enum pipe pipe = intel_crtc->pipe;
358 u32 mask;
359 int ret;
360
361 /*
362 * XXX: should issue multiple read requests and reads if request is
363 * longer than MIPI_MAX_RETURN_PKT_SIZE
364 */
365
366 I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
367
368 ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
369 reqlen);
370 if (ret)
371 return ret;
372
373 mask = GEN_READ_DATA_AVAIL;
374 if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
375 DRM_ERROR("Timeout waiting for read data.\n");
376
377 ret = dsi_read_data_return(intel_dsi, buf, buflen);
378 if (ret < 0)
379 return ret;
380
381 if (ret != buflen)
382 return -EIO;
383
384 return 0;
385}
386
387/*
388 * send a video mode command
389 *
390 * XXX: commands with data in MIPI_DPI_DATA?
391 */
392int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd)
393{
394 struct drm_encoder *encoder = &intel_dsi->base.base;
395 struct drm_device *dev = encoder->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
398 enum pipe pipe = intel_crtc->pipe;
399 u32 mask;
400
401 /* XXX: pipe, hs */
402 if (intel_dsi->hs)
403 cmd &= ~DPI_LP_MODE;
404 else
405 cmd |= DPI_LP_MODE;
406
407 /* DPI virtual channel?! */
408
409 mask = DPI_FIFO_EMPTY;
410 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
411 DRM_ERROR("Timeout waiting for DPI FIFO empty.\n");
412
413 /* clear bit */
414 I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
415
416 /* XXX: old code skips write if control unchanged */
417 if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe)))
418 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
419
420 I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd);
421
422 mask = SPL_PKT_SENT_INTERRUPT;
423 if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100))
424 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
425
426 return 0;
427}
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-29 10:30:34 -0400