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path: root/drivers/gpu/drm/i915/intel_dp.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c462
1 files changed, 213 insertions, 249 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 40be1fa65be1..c4c5868a8aa0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -42,10 +42,11 @@
42 42
43#define DP_LINK_CONFIGURATION_SIZE 9 43#define DP_LINK_CONFIGURATION_SIZE 9
44 44
45#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP) 45#define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
46#define IS_PCH_eDP(dp_priv) ((dp_priv)->is_pch_edp) 46#define IS_PCH_eDP(i) ((i)->is_pch_edp)
47 47
48struct intel_dp_priv { 48struct intel_dp {
49 struct intel_encoder base;
49 uint32_t output_reg; 50 uint32_t output_reg;
50 uint32_t DP; 51 uint32_t DP;
51 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 52 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
@@ -54,40 +55,39 @@ struct intel_dp_priv {
54 uint8_t link_bw; 55 uint8_t link_bw;
55 uint8_t lane_count; 56 uint8_t lane_count;
56 uint8_t dpcd[4]; 57 uint8_t dpcd[4];
57 struct intel_encoder *intel_encoder;
58 struct i2c_adapter adapter; 58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo; 59 struct i2c_algo_dp_aux_data algo;
60 bool is_pch_edp; 60 bool is_pch_edp;
61}; 61};
62 62
63static void 63static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
64intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, 64{
65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]); 65 return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base);
66}
66 67
67static void 68static void intel_dp_link_train(struct intel_dp *intel_dp);
68intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP); 69static void intel_dp_link_down(struct intel_dp *intel_dp);
69 70
70void 71void
71intel_edp_link_config (struct intel_encoder *intel_encoder, 72intel_edp_link_config (struct intel_encoder *intel_encoder,
72 int *lane_num, int *link_bw) 73 int *lane_num, int *link_bw)
73{ 74{
74 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 75 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
75 76
76 *lane_num = dp_priv->lane_count; 77 *lane_num = intel_dp->lane_count;
77 if (dp_priv->link_bw == DP_LINK_BW_1_62) 78 if (intel_dp->link_bw == DP_LINK_BW_1_62)
78 *link_bw = 162000; 79 *link_bw = 162000;
79 else if (dp_priv->link_bw == DP_LINK_BW_2_7) 80 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
80 *link_bw = 270000; 81 *link_bw = 270000;
81} 82}
82 83
83static int 84static int
84intel_dp_max_lane_count(struct intel_encoder *intel_encoder) 85intel_dp_max_lane_count(struct intel_dp *intel_dp)
85{ 86{
86 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
87 int max_lane_count = 4; 87 int max_lane_count = 4;
88 88
89 if (dp_priv->dpcd[0] >= 0x11) { 89 if (intel_dp->dpcd[0] >= 0x11) {
90 max_lane_count = dp_priv->dpcd[2] & 0x1f; 90 max_lane_count = intel_dp->dpcd[2] & 0x1f;
91 switch (max_lane_count) { 91 switch (max_lane_count) {
92 case 1: case 2: case 4: 92 case 1: case 2: case 4:
93 break; 93 break;
@@ -99,10 +99,9 @@ intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
99} 99}
100 100
101static int 101static int
102intel_dp_max_link_bw(struct intel_encoder *intel_encoder) 102intel_dp_max_link_bw(struct intel_dp *intel_dp)
103{ 103{
104 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 104 int max_link_bw = intel_dp->dpcd[1];
105 int max_link_bw = dp_priv->dpcd[1];
106 105
107 switch (max_link_bw) { 106 switch (max_link_bw) {
108 case DP_LINK_BW_1_62: 107 case DP_LINK_BW_1_62:
@@ -126,13 +125,11 @@ intel_dp_link_clock(uint8_t link_bw)
126 125
127/* I think this is a fiction */ 126/* I think this is a fiction */
128static int 127static int
129intel_dp_link_required(struct drm_device *dev, 128intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
130 struct intel_encoder *intel_encoder, int pixel_clock)
131{ 129{
132 struct drm_i915_private *dev_priv = dev->dev_private; 130 struct drm_i915_private *dev_priv = dev->dev_private;
133 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
134 131
135 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) 132 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
136 return (pixel_clock * dev_priv->edp_bpp) / 8; 133 return (pixel_clock * dev_priv->edp_bpp) / 8;
137 else 134 else
138 return pixel_clock * 3; 135 return pixel_clock * 3;
@@ -149,14 +146,13 @@ intel_dp_mode_valid(struct drm_connector *connector,
149 struct drm_display_mode *mode) 146 struct drm_display_mode *mode)
150{ 147{
151 struct drm_encoder *encoder = intel_attached_encoder(connector); 148 struct drm_encoder *encoder = intel_attached_encoder(connector);
152 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 149 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
153 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
154 struct drm_device *dev = connector->dev; 150 struct drm_device *dev = connector->dev;
155 struct drm_i915_private *dev_priv = dev->dev_private; 151 struct drm_i915_private *dev_priv = dev->dev_private;
156 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder)); 152 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
157 int max_lanes = intel_dp_max_lane_count(intel_encoder); 153 int max_lanes = intel_dp_max_lane_count(intel_dp);
158 154
159 if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) && 155 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
160 dev_priv->panel_fixed_mode) { 156 dev_priv->panel_fixed_mode) {
161 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 157 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
162 return MODE_PANEL; 158 return MODE_PANEL;
@@ -167,8 +163,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
167 163
168 /* only refuse the mode on non eDP since we have seen some wierd eDP panels 164 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
169 which are outside spec tolerances but somehow work by magic */ 165 which are outside spec tolerances but somehow work by magic */
170 if (!IS_eDP(intel_encoder) && 166 if (!IS_eDP(intel_dp) &&
171 (intel_dp_link_required(connector->dev, intel_encoder, mode->clock) 167 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
172 > intel_dp_max_data_rate(max_link_clock, max_lanes))) 168 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
173 return MODE_CLOCK_HIGH; 169 return MODE_CLOCK_HIGH;
174 170
@@ -232,13 +228,12 @@ intel_hrawclk(struct drm_device *dev)
232} 228}
233 229
234static int 230static int
235intel_dp_aux_ch(struct intel_encoder *intel_encoder, 231intel_dp_aux_ch(struct intel_dp *intel_dp,
236 uint8_t *send, int send_bytes, 232 uint8_t *send, int send_bytes,
237 uint8_t *recv, int recv_size) 233 uint8_t *recv, int recv_size)
238{ 234{
239 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 235 uint32_t output_reg = intel_dp->output_reg;
240 uint32_t output_reg = dp_priv->output_reg; 236 struct drm_device *dev = intel_dp->base.enc.dev;
241 struct drm_device *dev = intel_encoder->enc.dev;
242 struct drm_i915_private *dev_priv = dev->dev_private; 237 struct drm_i915_private *dev_priv = dev->dev_private;
243 uint32_t ch_ctl = output_reg + 0x10; 238 uint32_t ch_ctl = output_reg + 0x10;
244 uint32_t ch_data = ch_ctl + 4; 239 uint32_t ch_data = ch_ctl + 4;
@@ -253,7 +248,7 @@ intel_dp_aux_ch(struct intel_encoder *intel_encoder,
253 * and would like to run at 2MHz. So, take the 248 * and would like to run at 2MHz. So, take the
254 * hrawclk value and divide by 2 and use that 249 * hrawclk value and divide by 2 and use that
255 */ 250 */
256 if (IS_eDP(intel_encoder)) { 251 if (IS_eDP(intel_dp)) {
257 if (IS_GEN6(dev)) 252 if (IS_GEN6(dev))
258 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ 253 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
259 else 254 else
@@ -344,7 +339,7 @@ intel_dp_aux_ch(struct intel_encoder *intel_encoder,
344 339
345/* Write data to the aux channel in native mode */ 340/* Write data to the aux channel in native mode */
346static int 341static int
347intel_dp_aux_native_write(struct intel_encoder *intel_encoder, 342intel_dp_aux_native_write(struct intel_dp *intel_dp,
348 uint16_t address, uint8_t *send, int send_bytes) 343 uint16_t address, uint8_t *send, int send_bytes)
349{ 344{
350 int ret; 345 int ret;
@@ -361,7 +356,7 @@ intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
361 memcpy(&msg[4], send, send_bytes); 356 memcpy(&msg[4], send, send_bytes);
362 msg_bytes = send_bytes + 4; 357 msg_bytes = send_bytes + 4;
363 for (;;) { 358 for (;;) {
364 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1); 359 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
365 if (ret < 0) 360 if (ret < 0)
366 return ret; 361 return ret;
367 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 362 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
@@ -376,15 +371,15 @@ intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
376 371
377/* Write a single byte to the aux channel in native mode */ 372/* Write a single byte to the aux channel in native mode */
378static int 373static int
379intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder, 374intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
380 uint16_t address, uint8_t byte) 375 uint16_t address, uint8_t byte)
381{ 376{
382 return intel_dp_aux_native_write(intel_encoder, address, &byte, 1); 377 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
383} 378}
384 379
385/* read bytes from a native aux channel */ 380/* read bytes from a native aux channel */
386static int 381static int
387intel_dp_aux_native_read(struct intel_encoder *intel_encoder, 382intel_dp_aux_native_read(struct intel_dp *intel_dp,
388 uint16_t address, uint8_t *recv, int recv_bytes) 383 uint16_t address, uint8_t *recv, int recv_bytes)
389{ 384{
390 uint8_t msg[4]; 385 uint8_t msg[4];
@@ -403,7 +398,7 @@ intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
403 reply_bytes = recv_bytes + 1; 398 reply_bytes = recv_bytes + 1;
404 399
405 for (;;) { 400 for (;;) {
406 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, 401 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
407 reply, reply_bytes); 402 reply, reply_bytes);
408 if (ret == 0) 403 if (ret == 0)
409 return -EPROTO; 404 return -EPROTO;
@@ -426,10 +421,9 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
426 uint8_t write_byte, uint8_t *read_byte) 421 uint8_t write_byte, uint8_t *read_byte)
427{ 422{
428 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 423 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
429 struct intel_dp_priv *dp_priv = container_of(adapter, 424 struct intel_dp *intel_dp = container_of(adapter,
430 struct intel_dp_priv, 425 struct intel_dp,
431 adapter); 426 adapter);
432 struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
433 uint16_t address = algo_data->address; 427 uint16_t address = algo_data->address;
434 uint8_t msg[5]; 428 uint8_t msg[5];
435 uint8_t reply[2]; 429 uint8_t reply[2];
@@ -468,7 +462,7 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
468 } 462 }
469 463
470 for (;;) { 464 for (;;) {
471 ret = intel_dp_aux_ch(intel_encoder, 465 ret = intel_dp_aux_ch(intel_dp,
472 msg, msg_bytes, 466 msg, msg_bytes,
473 reply, reply_bytes); 467 reply, reply_bytes);
474 if (ret < 0) { 468 if (ret < 0) {
@@ -496,41 +490,38 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
496} 490}
497 491
498static int 492static int
499intel_dp_i2c_init(struct intel_encoder *intel_encoder, 493intel_dp_i2c_init(struct intel_dp *intel_dp,
500 struct intel_connector *intel_connector, const char *name) 494 struct intel_connector *intel_connector, const char *name)
501{ 495{
502 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
503
504 DRM_DEBUG_KMS("i2c_init %s\n", name); 496 DRM_DEBUG_KMS("i2c_init %s\n", name);
505 dp_priv->algo.running = false; 497 intel_dp->algo.running = false;
506 dp_priv->algo.address = 0; 498 intel_dp->algo.address = 0;
507 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch; 499 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
508 500
509 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter)); 501 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
510 dp_priv->adapter.owner = THIS_MODULE; 502 intel_dp->adapter.owner = THIS_MODULE;
511 dp_priv->adapter.class = I2C_CLASS_DDC; 503 intel_dp->adapter.class = I2C_CLASS_DDC;
512 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1); 504 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
513 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0'; 505 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
514 dp_priv->adapter.algo_data = &dp_priv->algo; 506 intel_dp->adapter.algo_data = &intel_dp->algo;
515 dp_priv->adapter.dev.parent = &intel_connector->base.kdev; 507 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
516 508
517 return i2c_dp_aux_add_bus(&dp_priv->adapter); 509 return i2c_dp_aux_add_bus(&intel_dp->adapter);
518} 510}
519 511
520static bool 512static bool
521intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 513intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
522 struct drm_display_mode *adjusted_mode) 514 struct drm_display_mode *adjusted_mode)
523{ 515{
524 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
525 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
526 struct drm_device *dev = encoder->dev; 516 struct drm_device *dev = encoder->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private; 517 struct drm_i915_private *dev_priv = dev->dev_private;
518 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
528 int lane_count, clock; 519 int lane_count, clock;
529 int max_lane_count = intel_dp_max_lane_count(intel_encoder); 520 int max_lane_count = intel_dp_max_lane_count(intel_dp);
530 int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0; 521 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
531 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 522 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
532 523
533 if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) && 524 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
534 dev_priv->panel_fixed_mode) { 525 dev_priv->panel_fixed_mode) {
535 struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode; 526 struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
536 527
@@ -558,28 +549,28 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
558 for (clock = 0; clock <= max_clock; clock++) { 549 for (clock = 0; clock <= max_clock; clock++) {
559 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 550 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
560 551
561 if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock) 552 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
562 <= link_avail) { 553 <= link_avail) {
563 dp_priv->link_bw = bws[clock]; 554 intel_dp->link_bw = bws[clock];
564 dp_priv->lane_count = lane_count; 555 intel_dp->lane_count = lane_count;
565 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); 556 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
566 DRM_DEBUG_KMS("Display port link bw %02x lane " 557 DRM_DEBUG_KMS("Display port link bw %02x lane "
567 "count %d clock %d\n", 558 "count %d clock %d\n",
568 dp_priv->link_bw, dp_priv->lane_count, 559 intel_dp->link_bw, intel_dp->lane_count,
569 adjusted_mode->clock); 560 adjusted_mode->clock);
570 return true; 561 return true;
571 } 562 }
572 } 563 }
573 } 564 }
574 565
575 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 566 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
576 /* okay we failed just pick the highest */ 567 /* okay we failed just pick the highest */
577 dp_priv->lane_count = max_lane_count; 568 intel_dp->lane_count = max_lane_count;
578 dp_priv->link_bw = bws[max_clock]; 569 intel_dp->link_bw = bws[max_clock];
579 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); 570 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
580 DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 571 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
581 "count %d clock %d\n", 572 "count %d clock %d\n",
582 dp_priv->link_bw, dp_priv->lane_count, 573 intel_dp->link_bw, intel_dp->lane_count,
583 adjusted_mode->clock); 574 adjusted_mode->clock);
584 return true; 575 return true;
585 } 576 }
@@ -626,17 +617,14 @@ bool intel_pch_has_edp(struct drm_crtc *crtc)
626 struct drm_encoder *encoder; 617 struct drm_encoder *encoder;
627 618
628 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 619 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
629 struct intel_encoder *intel_encoder; 620 struct intel_dp *intel_dp;
630 struct intel_dp_priv *dp_priv;
631 621
632 if (!encoder || encoder->crtc != crtc) 622 if (encoder->crtc != crtc)
633 continue; 623 continue;
634 624
635 intel_encoder = enc_to_intel_encoder(encoder); 625 intel_dp = enc_to_intel_dp(encoder);
636 dp_priv = intel_encoder->dev_priv; 626 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
637 627 return intel_dp->is_pch_edp;
638 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT)
639 return dp_priv->is_pch_edp;
640 } 628 }
641 return false; 629 return false;
642} 630}
@@ -657,18 +645,15 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
657 * Find the lane count in the intel_encoder private 645 * Find the lane count in the intel_encoder private
658 */ 646 */
659 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 647 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
660 struct intel_encoder *intel_encoder; 648 struct intel_dp *intel_dp;
661 struct intel_dp_priv *dp_priv;
662 649
663 if (encoder->crtc != crtc) 650 if (encoder->crtc != crtc)
664 continue; 651 continue;
665 652
666 intel_encoder = enc_to_intel_encoder(encoder); 653 intel_dp = enc_to_intel_dp(encoder);
667 dp_priv = intel_encoder->dev_priv; 654 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
668 655 lane_count = intel_dp->lane_count;
669 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 656 if (IS_PCH_eDP(intel_dp))
670 lane_count = dp_priv->lane_count;
671 if (IS_PCH_eDP(dp_priv))
672 bpp = dev_priv->edp_bpp; 657 bpp = dev_priv->edp_bpp;
673 break; 658 break;
674 } 659 }
@@ -724,61 +709,60 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
724 struct drm_display_mode *adjusted_mode) 709 struct drm_display_mode *adjusted_mode)
725{ 710{
726 struct drm_device *dev = encoder->dev; 711 struct drm_device *dev = encoder->dev;
727 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 712 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
728 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 713 struct drm_crtc *crtc = intel_dp->base.enc.crtc;
729 struct drm_crtc *crtc = intel_encoder->enc.crtc;
730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
731 715
732 dp_priv->DP = (DP_VOLTAGE_0_4 | 716 intel_dp->DP = (DP_VOLTAGE_0_4 |
733 DP_PRE_EMPHASIS_0); 717 DP_PRE_EMPHASIS_0);
734 718
735 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 719 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
736 dp_priv->DP |= DP_SYNC_HS_HIGH; 720 intel_dp->DP |= DP_SYNC_HS_HIGH;
737 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 721 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
738 dp_priv->DP |= DP_SYNC_VS_HIGH; 722 intel_dp->DP |= DP_SYNC_VS_HIGH;
739 723
740 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 724 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
741 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT; 725 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
742 else 726 else
743 dp_priv->DP |= DP_LINK_TRAIN_OFF; 727 intel_dp->DP |= DP_LINK_TRAIN_OFF;
744 728
745 switch (dp_priv->lane_count) { 729 switch (intel_dp->lane_count) {
746 case 1: 730 case 1:
747 dp_priv->DP |= DP_PORT_WIDTH_1; 731 intel_dp->DP |= DP_PORT_WIDTH_1;
748 break; 732 break;
749 case 2: 733 case 2:
750 dp_priv->DP |= DP_PORT_WIDTH_2; 734 intel_dp->DP |= DP_PORT_WIDTH_2;
751 break; 735 break;
752 case 4: 736 case 4:
753 dp_priv->DP |= DP_PORT_WIDTH_4; 737 intel_dp->DP |= DP_PORT_WIDTH_4;
754 break; 738 break;
755 } 739 }
756 if (dp_priv->has_audio) 740 if (intel_dp->has_audio)
757 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE; 741 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
758 742
759 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 743 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
760 dp_priv->link_configuration[0] = dp_priv->link_bw; 744 intel_dp->link_configuration[0] = intel_dp->link_bw;
761 dp_priv->link_configuration[1] = dp_priv->lane_count; 745 intel_dp->link_configuration[1] = intel_dp->lane_count;
762 746
763 /* 747 /*
764 * Check for DPCD version > 1.1 and enhanced framing support 748 * Check for DPCD version > 1.1 and enhanced framing support
765 */ 749 */
766 if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 750 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
767 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 751 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
768 dp_priv->DP |= DP_ENHANCED_FRAMING; 752 intel_dp->DP |= DP_ENHANCED_FRAMING;
769 } 753 }
770 754
771 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 755 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
772 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) 756 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
773 dp_priv->DP |= DP_PIPEB_SELECT; 757 intel_dp->DP |= DP_PIPEB_SELECT;
774 758
775 if (IS_eDP(intel_encoder)) { 759 if (IS_eDP(intel_dp)) {
776 /* don't miss out required setting for eDP */ 760 /* don't miss out required setting for eDP */
777 dp_priv->DP |= DP_PLL_ENABLE; 761 intel_dp->DP |= DP_PLL_ENABLE;
778 if (adjusted_mode->clock < 200000) 762 if (adjusted_mode->clock < 200000)
779 dp_priv->DP |= DP_PLL_FREQ_160MHZ; 763 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
780 else 764 else
781 dp_priv->DP |= DP_PLL_FREQ_270MHZ; 765 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
782 } 766 }
783} 767}
784 768
@@ -852,30 +836,29 @@ static void ironlake_edp_backlight_off (struct drm_device *dev)
852static void 836static void
853intel_dp_dpms(struct drm_encoder *encoder, int mode) 837intel_dp_dpms(struct drm_encoder *encoder, int mode)
854{ 838{
855 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 839 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
856 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
857 struct drm_device *dev = encoder->dev; 840 struct drm_device *dev = encoder->dev;
858 struct drm_i915_private *dev_priv = dev->dev_private; 841 struct drm_i915_private *dev_priv = dev->dev_private;
859 uint32_t dp_reg = I915_READ(dp_priv->output_reg); 842 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
860 843
861 if (mode != DRM_MODE_DPMS_ON) { 844 if (mode != DRM_MODE_DPMS_ON) {
862 if (dp_reg & DP_PORT_EN) { 845 if (dp_reg & DP_PORT_EN) {
863 intel_dp_link_down(intel_encoder, dp_priv->DP); 846 intel_dp_link_down(intel_dp);
864 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 847 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
865 ironlake_edp_backlight_off(dev); 848 ironlake_edp_backlight_off(dev);
866 ironlake_edp_panel_off(dev); 849 ironlake_edp_panel_off(dev);
867 } 850 }
868 } 851 }
869 } else { 852 } else {
870 if (!(dp_reg & DP_PORT_EN)) { 853 if (!(dp_reg & DP_PORT_EN)) {
871 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration); 854 intel_dp_link_train(intel_dp);
872 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 855 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
873 ironlake_edp_panel_on(dev); 856 ironlake_edp_panel_on(dev);
874 ironlake_edp_backlight_on(dev); 857 ironlake_edp_backlight_on(dev);
875 } 858 }
876 } 859 }
877 } 860 }
878 dp_priv->dpms_mode = mode; 861 intel_dp->dpms_mode = mode;
879} 862}
880 863
881/* 864/*
@@ -883,12 +866,12 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
883 * link status information 866 * link status information
884 */ 867 */
885static bool 868static bool
886intel_dp_get_link_status(struct intel_encoder *intel_encoder, 869intel_dp_get_link_status(struct intel_dp *intel_dp,
887 uint8_t link_status[DP_LINK_STATUS_SIZE]) 870 uint8_t link_status[DP_LINK_STATUS_SIZE])
888{ 871{
889 int ret; 872 int ret;
890 873
891 ret = intel_dp_aux_native_read(intel_encoder, 874 ret = intel_dp_aux_native_read(intel_dp,
892 DP_LANE0_1_STATUS, 875 DP_LANE0_1_STATUS,
893 link_status, DP_LINK_STATUS_SIZE); 876 link_status, DP_LINK_STATUS_SIZE);
894 if (ret != DP_LINK_STATUS_SIZE) 877 if (ret != DP_LINK_STATUS_SIZE)
@@ -965,7 +948,7 @@ intel_dp_pre_emphasis_max(uint8_t voltage_swing)
965} 948}
966 949
967static void 950static void
968intel_get_adjust_train(struct intel_encoder *intel_encoder, 951intel_get_adjust_train(struct intel_dp *intel_dp,
969 uint8_t link_status[DP_LINK_STATUS_SIZE], 952 uint8_t link_status[DP_LINK_STATUS_SIZE],
970 int lane_count, 953 int lane_count,
971 uint8_t train_set[4]) 954 uint8_t train_set[4])
@@ -1101,27 +1084,26 @@ intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1101} 1084}
1102 1085
1103static bool 1086static bool
1104intel_dp_set_link_train(struct intel_encoder *intel_encoder, 1087intel_dp_set_link_train(struct intel_dp *intel_dp,
1105 uint32_t dp_reg_value, 1088 uint32_t dp_reg_value,
1106 uint8_t dp_train_pat, 1089 uint8_t dp_train_pat,
1107 uint8_t train_set[4], 1090 uint8_t train_set[4],
1108 bool first) 1091 bool first)
1109{ 1092{
1110 struct drm_device *dev = intel_encoder->enc.dev; 1093 struct drm_device *dev = intel_dp->base.enc.dev;
1111 struct drm_i915_private *dev_priv = dev->dev_private; 1094 struct drm_i915_private *dev_priv = dev->dev_private;
1112 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1113 int ret; 1095 int ret;
1114 1096
1115 I915_WRITE(dp_priv->output_reg, dp_reg_value); 1097 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1116 POSTING_READ(dp_priv->output_reg); 1098 POSTING_READ(intel_dp->output_reg);
1117 if (first) 1099 if (first)
1118 intel_wait_for_vblank(dev); 1100 intel_wait_for_vblank(dev);
1119 1101
1120 intel_dp_aux_native_write_1(intel_encoder, 1102 intel_dp_aux_native_write_1(intel_dp,
1121 DP_TRAINING_PATTERN_SET, 1103 DP_TRAINING_PATTERN_SET,
1122 dp_train_pat); 1104 dp_train_pat);
1123 1105
1124 ret = intel_dp_aux_native_write(intel_encoder, 1106 ret = intel_dp_aux_native_write(intel_dp,
1125 DP_TRAINING_LANE0_SET, train_set, 4); 1107 DP_TRAINING_LANE0_SET, train_set, 4);
1126 if (ret != 4) 1108 if (ret != 4)
1127 return false; 1109 return false;
@@ -1130,12 +1112,10 @@ intel_dp_set_link_train(struct intel_encoder *intel_encoder,
1130} 1112}
1131 1113
1132static void 1114static void
1133intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, 1115intel_dp_link_train(struct intel_dp *intel_dp)
1134 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
1135{ 1116{
1136 struct drm_device *dev = intel_encoder->enc.dev; 1117 struct drm_device *dev = intel_dp->base.enc.dev;
1137 struct drm_i915_private *dev_priv = dev->dev_private; 1118 struct drm_i915_private *dev_priv = dev->dev_private;
1138 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1139 uint8_t train_set[4]; 1119 uint8_t train_set[4];
1140 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1120 uint8_t link_status[DP_LINK_STATUS_SIZE];
1141 int i; 1121 int i;
@@ -1145,13 +1125,15 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1145 bool first = true; 1125 bool first = true;
1146 int tries; 1126 int tries;
1147 u32 reg; 1127 u32 reg;
1128 uint32_t DP = intel_dp->DP;
1148 1129
1149 /* Write the link configuration data */ 1130 /* Write the link configuration data */
1150 intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET, 1131 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1151 link_configuration, DP_LINK_CONFIGURATION_SIZE); 1132 intel_dp->link_configuration,
1133 DP_LINK_CONFIGURATION_SIZE);
1152 1134
1153 DP |= DP_PORT_EN; 1135 DP |= DP_PORT_EN;
1154 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1136 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1155 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1137 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1156 else 1138 else
1157 DP &= ~DP_LINK_TRAIN_MASK; 1139 DP &= ~DP_LINK_TRAIN_MASK;
@@ -1162,39 +1144,39 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1162 for (;;) { 1144 for (;;) {
1163 /* Use train_set[0] to set the voltage and pre emphasis values */ 1145 /* Use train_set[0] to set the voltage and pre emphasis values */
1164 uint32_t signal_levels; 1146 uint32_t signal_levels;
1165 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) { 1147 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
1166 signal_levels = intel_gen6_edp_signal_levels(train_set[0]); 1148 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1167 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1149 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1168 } else { 1150 } else {
1169 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); 1151 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
1170 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1152 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1171 } 1153 }
1172 1154
1173 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1155 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1174 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1156 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1175 else 1157 else
1176 reg = DP | DP_LINK_TRAIN_PAT_1; 1158 reg = DP | DP_LINK_TRAIN_PAT_1;
1177 1159
1178 if (!intel_dp_set_link_train(intel_encoder, reg, 1160 if (!intel_dp_set_link_train(intel_dp, reg,
1179 DP_TRAINING_PATTERN_1, train_set, first)) 1161 DP_TRAINING_PATTERN_1, train_set, first))
1180 break; 1162 break;
1181 first = false; 1163 first = false;
1182 /* Set training pattern 1 */ 1164 /* Set training pattern 1 */
1183 1165
1184 udelay(100); 1166 udelay(100);
1185 if (!intel_dp_get_link_status(intel_encoder, link_status)) 1167 if (!intel_dp_get_link_status(intel_dp, link_status))
1186 break; 1168 break;
1187 1169
1188 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) { 1170 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1189 clock_recovery = true; 1171 clock_recovery = true;
1190 break; 1172 break;
1191 } 1173 }
1192 1174
1193 /* Check to see if we've tried the max voltage */ 1175 /* Check to see if we've tried the max voltage */
1194 for (i = 0; i < dp_priv->lane_count; i++) 1176 for (i = 0; i < intel_dp->lane_count; i++)
1195 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1177 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1196 break; 1178 break;
1197 if (i == dp_priv->lane_count) 1179 if (i == intel_dp->lane_count)
1198 break; 1180 break;
1199 1181
1200 /* Check to see if we've tried the same voltage 5 times */ 1182 /* Check to see if we've tried the same voltage 5 times */
@@ -1207,7 +1189,7 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1207 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1189 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1208 1190
1209 /* Compute new train_set as requested by target */ 1191 /* Compute new train_set as requested by target */
1210 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set); 1192 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
1211 } 1193 }
1212 1194
1213 /* channel equalization */ 1195 /* channel equalization */
@@ -1217,30 +1199,30 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1217 /* Use train_set[0] to set the voltage and pre emphasis values */ 1199 /* Use train_set[0] to set the voltage and pre emphasis values */
1218 uint32_t signal_levels; 1200 uint32_t signal_levels;
1219 1201
1220 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) { 1202 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
1221 signal_levels = intel_gen6_edp_signal_levels(train_set[0]); 1203 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1222 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1204 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1223 } else { 1205 } else {
1224 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); 1206 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
1225 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1207 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1226 } 1208 }
1227 1209
1228 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1210 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1229 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1211 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1230 else 1212 else
1231 reg = DP | DP_LINK_TRAIN_PAT_2; 1213 reg = DP | DP_LINK_TRAIN_PAT_2;
1232 1214
1233 /* channel eq pattern */ 1215 /* channel eq pattern */
1234 if (!intel_dp_set_link_train(intel_encoder, reg, 1216 if (!intel_dp_set_link_train(intel_dp, reg,
1235 DP_TRAINING_PATTERN_2, train_set, 1217 DP_TRAINING_PATTERN_2, train_set,
1236 false)) 1218 false))
1237 break; 1219 break;
1238 1220
1239 udelay(400); 1221 udelay(400);
1240 if (!intel_dp_get_link_status(intel_encoder, link_status)) 1222 if (!intel_dp_get_link_status(intel_dp, link_status))
1241 break; 1223 break;
1242 1224
1243 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) { 1225 if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) {
1244 channel_eq = true; 1226 channel_eq = true;
1245 break; 1227 break;
1246 } 1228 }
@@ -1250,53 +1232,53 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1250 break; 1232 break;
1251 1233
1252 /* Compute new train_set as requested by target */ 1234 /* Compute new train_set as requested by target */
1253 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set); 1235 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
1254 ++tries; 1236 ++tries;
1255 } 1237 }
1256 1238
1257 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1239 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1258 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1240 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1259 else 1241 else
1260 reg = DP | DP_LINK_TRAIN_OFF; 1242 reg = DP | DP_LINK_TRAIN_OFF;
1261 1243
1262 I915_WRITE(dp_priv->output_reg, reg); 1244 I915_WRITE(intel_dp->output_reg, reg);
1263 POSTING_READ(dp_priv->output_reg); 1245 POSTING_READ(intel_dp->output_reg);
1264 intel_dp_aux_native_write_1(intel_encoder, 1246 intel_dp_aux_native_write_1(intel_dp,
1265 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1247 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1266} 1248}
1267 1249
1268static void 1250static void
1269intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP) 1251intel_dp_link_down(struct intel_dp *intel_dp)
1270{ 1252{
1271 struct drm_device *dev = intel_encoder->enc.dev; 1253 struct drm_device *dev = intel_dp->base.enc.dev;
1272 struct drm_i915_private *dev_priv = dev->dev_private; 1254 struct drm_i915_private *dev_priv = dev->dev_private;
1273 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1255 uint32_t DP = intel_dp->DP;
1274 1256
1275 DRM_DEBUG_KMS("\n"); 1257 DRM_DEBUG_KMS("\n");
1276 1258
1277 if (IS_eDP(intel_encoder)) { 1259 if (IS_eDP(intel_dp)) {
1278 DP &= ~DP_PLL_ENABLE; 1260 DP &= ~DP_PLL_ENABLE;
1279 I915_WRITE(dp_priv->output_reg, DP); 1261 I915_WRITE(intel_dp->output_reg, DP);
1280 POSTING_READ(dp_priv->output_reg); 1262 POSTING_READ(intel_dp->output_reg);
1281 udelay(100); 1263 udelay(100);
1282 } 1264 }
1283 1265
1284 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) { 1266 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) {
1285 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1267 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1286 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1268 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1287 POSTING_READ(dp_priv->output_reg); 1269 POSTING_READ(intel_dp->output_reg);
1288 } else { 1270 } else {
1289 DP &= ~DP_LINK_TRAIN_MASK; 1271 DP &= ~DP_LINK_TRAIN_MASK;
1290 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1272 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1291 POSTING_READ(dp_priv->output_reg); 1273 POSTING_READ(intel_dp->output_reg);
1292 } 1274 }
1293 1275
1294 udelay(17000); 1276 udelay(17000);
1295 1277
1296 if (IS_eDP(intel_encoder)) 1278 if (IS_eDP(intel_dp))
1297 DP |= DP_LINK_TRAIN_OFF; 1279 DP |= DP_LINK_TRAIN_OFF;
1298 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN); 1280 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1299 POSTING_READ(dp_priv->output_reg); 1281 POSTING_READ(intel_dp->output_reg);
1300} 1282}
1301 1283
1302/* 1284/*
@@ -1309,41 +1291,39 @@ intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1309 */ 1291 */
1310 1292
1311static void 1293static void
1312intel_dp_check_link_status(struct intel_encoder *intel_encoder) 1294intel_dp_check_link_status(struct intel_dp *intel_dp)
1313{ 1295{
1314 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1315 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1296 uint8_t link_status[DP_LINK_STATUS_SIZE];
1316 1297
1317 if (!intel_encoder->enc.crtc) 1298 if (!intel_dp->base.enc.crtc)
1318 return; 1299 return;
1319 1300
1320 if (!intel_dp_get_link_status(intel_encoder, link_status)) { 1301 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1321 intel_dp_link_down(intel_encoder, dp_priv->DP); 1302 intel_dp_link_down(intel_dp);
1322 return; 1303 return;
1323 } 1304 }
1324 1305
1325 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count)) 1306 if (!intel_channel_eq_ok(link_status, intel_dp->lane_count))
1326 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration); 1307 intel_dp_link_train(intel_dp);
1327} 1308}
1328 1309
1329static enum drm_connector_status 1310static enum drm_connector_status
1330ironlake_dp_detect(struct drm_connector *connector) 1311ironlake_dp_detect(struct drm_connector *connector)
1331{ 1312{
1332 struct drm_encoder *encoder = intel_attached_encoder(connector); 1313 struct drm_encoder *encoder = intel_attached_encoder(connector);
1333 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1314 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1334 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1335 enum drm_connector_status status; 1315 enum drm_connector_status status;
1336 1316
1337 status = connector_status_disconnected; 1317 status = connector_status_disconnected;
1338 if (intel_dp_aux_native_read(intel_encoder, 1318 if (intel_dp_aux_native_read(intel_dp,
1339 0x000, dp_priv->dpcd, 1319 0x000, intel_dp->dpcd,
1340 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) 1320 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1341 { 1321 {
1342 if (dp_priv->dpcd[0] != 0) 1322 if (intel_dp->dpcd[0] != 0)
1343 status = connector_status_connected; 1323 status = connector_status_connected;
1344 } 1324 }
1345 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0], 1325 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1346 dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]); 1326 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1347 return status; 1327 return status;
1348} 1328}
1349 1329
@@ -1357,19 +1337,18 @@ static enum drm_connector_status
1357intel_dp_detect(struct drm_connector *connector) 1337intel_dp_detect(struct drm_connector *connector)
1358{ 1338{
1359 struct drm_encoder *encoder = intel_attached_encoder(connector); 1339 struct drm_encoder *encoder = intel_attached_encoder(connector);
1360 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1340 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1361 struct drm_device *dev = intel_encoder->enc.dev; 1341 struct drm_device *dev = intel_dp->base.enc.dev;
1362 struct drm_i915_private *dev_priv = dev->dev_private; 1342 struct drm_i915_private *dev_priv = dev->dev_private;
1363 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1364 uint32_t temp, bit; 1343 uint32_t temp, bit;
1365 enum drm_connector_status status; 1344 enum drm_connector_status status;
1366 1345
1367 dp_priv->has_audio = false; 1346 intel_dp->has_audio = false;
1368 1347
1369 if (HAS_PCH_SPLIT(dev)) 1348 if (HAS_PCH_SPLIT(dev))
1370 return ironlake_dp_detect(connector); 1349 return ironlake_dp_detect(connector);
1371 1350
1372 switch (dp_priv->output_reg) { 1351 switch (intel_dp->output_reg) {
1373 case DP_B: 1352 case DP_B:
1374 bit = DPB_HOTPLUG_INT_STATUS; 1353 bit = DPB_HOTPLUG_INT_STATUS;
1375 break; 1354 break;
@@ -1389,11 +1368,11 @@ intel_dp_detect(struct drm_connector *connector)
1389 return connector_status_disconnected; 1368 return connector_status_disconnected;
1390 1369
1391 status = connector_status_disconnected; 1370 status = connector_status_disconnected;
1392 if (intel_dp_aux_native_read(intel_encoder, 1371 if (intel_dp_aux_native_read(intel_dp,
1393 0x000, dp_priv->dpcd, 1372 0x000, intel_dp->dpcd,
1394 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) 1373 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1395 { 1374 {
1396 if (dp_priv->dpcd[0] != 0) 1375 if (intel_dp->dpcd[0] != 0)
1397 status = connector_status_connected; 1376 status = connector_status_connected;
1398 } 1377 }
1399 return status; 1378 return status;
@@ -1402,18 +1381,17 @@ intel_dp_detect(struct drm_connector *connector)
1402static int intel_dp_get_modes(struct drm_connector *connector) 1381static int intel_dp_get_modes(struct drm_connector *connector)
1403{ 1382{
1404 struct drm_encoder *encoder = intel_attached_encoder(connector); 1383 struct drm_encoder *encoder = intel_attached_encoder(connector);
1405 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1384 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1406 struct drm_device *dev = intel_encoder->enc.dev; 1385 struct drm_device *dev = intel_dp->base.enc.dev;
1407 struct drm_i915_private *dev_priv = dev->dev_private; 1386 struct drm_i915_private *dev_priv = dev->dev_private;
1408 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1409 int ret; 1387 int ret;
1410 1388
1411 /* We should parse the EDID data and find out if it has an audio sink 1389 /* We should parse the EDID data and find out if it has an audio sink
1412 */ 1390 */
1413 1391
1414 ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 1392 ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus);
1415 if (ret) { 1393 if (ret) {
1416 if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) && 1394 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
1417 !dev_priv->panel_fixed_mode) { 1395 !dev_priv->panel_fixed_mode) {
1418 struct drm_display_mode *newmode; 1396 struct drm_display_mode *newmode;
1419 list_for_each_entry(newmode, &connector->probed_modes, 1397 list_for_each_entry(newmode, &connector->probed_modes,
@@ -1430,7 +1408,7 @@ static int intel_dp_get_modes(struct drm_connector *connector)
1430 } 1408 }
1431 1409
1432 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1410 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1433 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 1411 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
1434 if (dev_priv->panel_fixed_mode != NULL) { 1412 if (dev_priv->panel_fixed_mode != NULL) {
1435 struct drm_display_mode *mode; 1413 struct drm_display_mode *mode;
1436 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 1414 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
@@ -1470,27 +1448,17 @@ static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs =
1470 .best_encoder = intel_attached_encoder, 1448 .best_encoder = intel_attached_encoder,
1471}; 1449};
1472 1450
1473static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1474{
1475 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1476
1477 if (intel_encoder->i2c_bus)
1478 intel_i2c_destroy(intel_encoder->i2c_bus);
1479 drm_encoder_cleanup(encoder);
1480 kfree(intel_encoder);
1481}
1482
1483static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1451static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1484 .destroy = intel_dp_enc_destroy, 1452 .destroy = intel_encoder_destroy,
1485}; 1453};
1486 1454
1487void 1455void
1488intel_dp_hot_plug(struct intel_encoder *intel_encoder) 1456intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1489{ 1457{
1490 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1458 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1491 1459
1492 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON) 1460 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1493 intel_dp_check_link_status(intel_encoder); 1461 intel_dp_check_link_status(intel_dp);
1494} 1462}
1495 1463
1496/* Return which DP Port should be selected for Transcoder DP control */ 1464/* Return which DP Port should be selected for Transcoder DP control */
@@ -1500,18 +1468,18 @@ intel_trans_dp_port_sel (struct drm_crtc *crtc)
1500 struct drm_device *dev = crtc->dev; 1468 struct drm_device *dev = crtc->dev;
1501 struct drm_mode_config *mode_config = &dev->mode_config; 1469 struct drm_mode_config *mode_config = &dev->mode_config;
1502 struct drm_encoder *encoder; 1470 struct drm_encoder *encoder;
1503 struct intel_encoder *intel_encoder = NULL;
1504 1471
1505 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 1472 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1473 struct intel_dp *intel_dp;
1474
1506 if (encoder->crtc != crtc) 1475 if (encoder->crtc != crtc)
1507 continue; 1476 continue;
1508 1477
1509 intel_encoder = enc_to_intel_encoder(encoder); 1478 intel_dp = enc_to_intel_dp(encoder);
1510 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 1479 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1511 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1480 return intel_dp->output_reg;
1512 return dp_priv->output_reg;
1513 }
1514 } 1481 }
1482
1515 return -1; 1483 return -1;
1516} 1484}
1517 1485
@@ -1540,30 +1508,28 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1540{ 1508{
1541 struct drm_i915_private *dev_priv = dev->dev_private; 1509 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct drm_connector *connector; 1510 struct drm_connector *connector;
1511 struct intel_dp *intel_dp;
1543 struct intel_encoder *intel_encoder; 1512 struct intel_encoder *intel_encoder;
1544 struct intel_connector *intel_connector; 1513 struct intel_connector *intel_connector;
1545 struct intel_dp_priv *dp_priv;
1546 const char *name = NULL; 1514 const char *name = NULL;
1547 int type; 1515 int type;
1548 1516
1549 intel_encoder = kcalloc(sizeof(struct intel_encoder) + 1517 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1550 sizeof(struct intel_dp_priv), 1, GFP_KERNEL); 1518 if (!intel_dp)
1551 if (!intel_encoder)
1552 return; 1519 return;
1553 1520
1554 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1521 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1555 if (!intel_connector) { 1522 if (!intel_connector) {
1556 kfree(intel_encoder); 1523 kfree(intel_dp);
1557 return; 1524 return;
1558 } 1525 }
1526 intel_encoder = &intel_dp->base;
1559 1527
1560 dp_priv = (struct intel_dp_priv *)(intel_encoder + 1); 1528 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1561
1562 if (HAS_PCH_SPLIT(dev) && (output_reg == PCH_DP_D))
1563 if (intel_dpd_is_edp(dev)) 1529 if (intel_dpd_is_edp(dev))
1564 dp_priv->is_pch_edp = true; 1530 intel_dp->is_pch_edp = true;
1565 1531
1566 if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) { 1532 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
1567 type = DRM_MODE_CONNECTOR_eDP; 1533 type = DRM_MODE_CONNECTOR_eDP;
1568 intel_encoder->type = INTEL_OUTPUT_EDP; 1534 intel_encoder->type = INTEL_OUTPUT_EDP;
1569 } else { 1535 } else {
@@ -1584,18 +1550,16 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1584 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1550 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1585 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1551 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1586 1552
1587 if (IS_eDP(intel_encoder)) 1553 if (IS_eDP(intel_dp))
1588 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1554 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1589 1555
1590 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1556 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1591 connector->interlace_allowed = true; 1557 connector->interlace_allowed = true;
1592 connector->doublescan_allowed = 0; 1558 connector->doublescan_allowed = 0;
1593 1559
1594 dp_priv->intel_encoder = intel_encoder; 1560 intel_dp->output_reg = output_reg;
1595 dp_priv->output_reg = output_reg; 1561 intel_dp->has_audio = false;
1596 dp_priv->has_audio = false; 1562 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1597 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1598 intel_encoder->dev_priv = dp_priv;
1599 1563
1600 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs, 1564 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1601 DRM_MODE_ENCODER_TMDS); 1565 DRM_MODE_ENCODER_TMDS);
@@ -1630,12 +1594,12 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1630 break; 1594 break;
1631 } 1595 }
1632 1596
1633 intel_dp_i2c_init(intel_encoder, intel_connector, name); 1597 intel_dp_i2c_init(intel_dp, intel_connector, name);
1634 1598
1635 intel_encoder->ddc_bus = &dp_priv->adapter; 1599 intel_encoder->ddc_bus = &intel_dp->adapter;
1636 intel_encoder->hot_plug = intel_dp_hot_plug; 1600 intel_encoder->hot_plug = intel_dp_hot_plug;
1637 1601
1638 if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) { 1602 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
1639 /* initialize panel mode from VBT if available for eDP */ 1603 /* initialize panel mode from VBT if available for eDP */
1640 if (dev_priv->lfp_lvds_vbt_mode) { 1604 if (dev_priv->lfp_lvds_vbt_mode) {
1641 dev_priv->panel_fixed_mode = 1605 dev_priv->panel_fixed_mode =