diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 254 |
1 files changed, 163 insertions, 91 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 77e40cfcf216..f6299bb788e5 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -48,8 +48,6 @@ struct intel_dp_priv { | |||
48 | uint32_t output_reg; | 48 | uint32_t output_reg; |
49 | uint32_t DP; | 49 | uint32_t DP; |
50 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | 50 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
51 | uint32_t save_DP; | ||
52 | uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE]; | ||
53 | bool has_audio; | 51 | bool has_audio; |
54 | int dpms_mode; | 52 | int dpms_mode; |
55 | uint8_t link_bw; | 53 | uint8_t link_bw; |
@@ -141,7 +139,8 @@ static int | |||
141 | intel_dp_mode_valid(struct drm_connector *connector, | 139 | intel_dp_mode_valid(struct drm_connector *connector, |
142 | struct drm_display_mode *mode) | 140 | struct drm_display_mode *mode) |
143 | { | 141 | { |
144 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | 142 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
143 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | ||
145 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder)); | 144 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder)); |
146 | int max_lanes = intel_dp_max_lane_count(intel_encoder); | 145 | int max_lanes = intel_dp_max_lane_count(intel_encoder); |
147 | 146 | ||
@@ -215,7 +214,7 @@ intel_dp_aux_ch(struct intel_encoder *intel_encoder, | |||
215 | { | 214 | { |
216 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 215 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; |
217 | uint32_t output_reg = dp_priv->output_reg; | 216 | uint32_t output_reg = dp_priv->output_reg; |
218 | struct drm_device *dev = intel_encoder->base.dev; | 217 | struct drm_device *dev = intel_encoder->enc.dev; |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | 218 | struct drm_i915_private *dev_priv = dev->dev_private; |
220 | uint32_t ch_ctl = output_reg + 0x10; | 219 | uint32_t ch_ctl = output_reg + 0x10; |
221 | uint32_t ch_data = ch_ctl + 4; | 220 | uint32_t ch_data = ch_ctl + 4; |
@@ -224,19 +223,27 @@ intel_dp_aux_ch(struct intel_encoder *intel_encoder, | |||
224 | uint32_t ctl; | 223 | uint32_t ctl; |
225 | uint32_t status; | 224 | uint32_t status; |
226 | uint32_t aux_clock_divider; | 225 | uint32_t aux_clock_divider; |
227 | int try; | 226 | int try, precharge; |
228 | 227 | ||
229 | /* The clock divider is based off the hrawclk, | 228 | /* The clock divider is based off the hrawclk, |
230 | * and would like to run at 2MHz. So, take the | 229 | * and would like to run at 2MHz. So, take the |
231 | * hrawclk value and divide by 2 and use that | 230 | * hrawclk value and divide by 2 and use that |
232 | */ | 231 | */ |
233 | if (IS_eDP(intel_encoder)) | 232 | if (IS_eDP(intel_encoder)) { |
234 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | 233 | if (IS_GEN6(dev)) |
235 | else if (HAS_PCH_SPLIT(dev)) | 234 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ |
235 | else | ||
236 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | ||
237 | } else if (HAS_PCH_SPLIT(dev)) | ||
236 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ | 238 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
237 | else | 239 | else |
238 | aux_clock_divider = intel_hrawclk(dev) / 2; | 240 | aux_clock_divider = intel_hrawclk(dev) / 2; |
239 | 241 | ||
242 | if (IS_GEN6(dev)) | ||
243 | precharge = 3; | ||
244 | else | ||
245 | precharge = 5; | ||
246 | |||
240 | /* Must try at least 3 times according to DP spec */ | 247 | /* Must try at least 3 times according to DP spec */ |
241 | for (try = 0; try < 5; try++) { | 248 | for (try = 0; try < 5; try++) { |
242 | /* Load the send data into the aux channel data registers */ | 249 | /* Load the send data into the aux channel data registers */ |
@@ -249,7 +256,7 @@ intel_dp_aux_ch(struct intel_encoder *intel_encoder, | |||
249 | ctl = (DP_AUX_CH_CTL_SEND_BUSY | | 256 | ctl = (DP_AUX_CH_CTL_SEND_BUSY | |
250 | DP_AUX_CH_CTL_TIME_OUT_400us | | 257 | DP_AUX_CH_CTL_TIME_OUT_400us | |
251 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | 258 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
252 | (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | 259 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
253 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | 260 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
254 | DP_AUX_CH_CTL_DONE | | 261 | DP_AUX_CH_CTL_DONE | |
255 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | 262 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
@@ -465,7 +472,8 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, | |||
465 | } | 472 | } |
466 | 473 | ||
467 | static int | 474 | static int |
468 | intel_dp_i2c_init(struct intel_encoder *intel_encoder, const char *name) | 475 | intel_dp_i2c_init(struct intel_encoder *intel_encoder, |
476 | struct intel_connector *intel_connector, const char *name) | ||
469 | { | 477 | { |
470 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 478 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; |
471 | 479 | ||
@@ -480,7 +488,7 @@ intel_dp_i2c_init(struct intel_encoder *intel_encoder, const char *name) | |||
480 | strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1); | 488 | strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1); |
481 | dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0'; | 489 | dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0'; |
482 | dp_priv->adapter.algo_data = &dp_priv->algo; | 490 | dp_priv->adapter.algo_data = &dp_priv->algo; |
483 | dp_priv->adapter.dev.parent = &intel_encoder->base.kdev; | 491 | dp_priv->adapter.dev.parent = &intel_connector->base.kdev; |
484 | 492 | ||
485 | return i2c_dp_aux_add_bus(&dp_priv->adapter); | 493 | return i2c_dp_aux_add_bus(&dp_priv->adapter); |
486 | } | 494 | } |
@@ -555,7 +563,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |||
555 | { | 563 | { |
556 | struct drm_device *dev = crtc->dev; | 564 | struct drm_device *dev = crtc->dev; |
557 | struct drm_mode_config *mode_config = &dev->mode_config; | 565 | struct drm_mode_config *mode_config = &dev->mode_config; |
558 | struct drm_connector *connector; | 566 | struct drm_encoder *encoder; |
559 | struct drm_i915_private *dev_priv = dev->dev_private; | 567 | struct drm_i915_private *dev_priv = dev->dev_private; |
560 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | 568 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
561 | int lane_count = 4; | 569 | int lane_count = 4; |
@@ -564,13 +572,16 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |||
564 | /* | 572 | /* |
565 | * Find the lane count in the intel_encoder private | 573 | * Find the lane count in the intel_encoder private |
566 | */ | 574 | */ |
567 | list_for_each_entry(connector, &mode_config->connector_list, head) { | 575 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
568 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | 576 | struct intel_encoder *intel_encoder; |
569 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 577 | struct intel_dp_priv *dp_priv; |
570 | 578 | ||
571 | if (!connector->encoder || connector->encoder->crtc != crtc) | 579 | if (!encoder || encoder->crtc != crtc) |
572 | continue; | 580 | continue; |
573 | 581 | ||
582 | intel_encoder = enc_to_intel_encoder(encoder); | ||
583 | dp_priv = intel_encoder->dev_priv; | ||
584 | |||
574 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { | 585 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { |
575 | lane_count = dp_priv->lane_count; | 586 | lane_count = dp_priv->lane_count; |
576 | break; | 587 | break; |
@@ -626,16 +637,24 @@ static void | |||
626 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | 637 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
627 | struct drm_display_mode *adjusted_mode) | 638 | struct drm_display_mode *adjusted_mode) |
628 | { | 639 | { |
640 | struct drm_device *dev = encoder->dev; | ||
629 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | 641 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
630 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 642 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; |
631 | struct drm_crtc *crtc = intel_encoder->enc.crtc; | 643 | struct drm_crtc *crtc = intel_encoder->enc.crtc; |
632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | 644 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
633 | 645 | ||
634 | dp_priv->DP = (DP_LINK_TRAIN_OFF | | 646 | dp_priv->DP = (DP_VOLTAGE_0_4 | |
635 | DP_VOLTAGE_0_4 | | 647 | DP_PRE_EMPHASIS_0); |
636 | DP_PRE_EMPHASIS_0 | | 648 | |
637 | DP_SYNC_VS_HIGH | | 649 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
638 | DP_SYNC_HS_HIGH); | 650 | dp_priv->DP |= DP_SYNC_HS_HIGH; |
651 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | ||
652 | dp_priv->DP |= DP_SYNC_VS_HIGH; | ||
653 | |||
654 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) | ||
655 | dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT; | ||
656 | else | ||
657 | dp_priv->DP |= DP_LINK_TRAIN_OFF; | ||
639 | 658 | ||
640 | switch (dp_priv->lane_count) { | 659 | switch (dp_priv->lane_count) { |
641 | case 1: | 660 | case 1: |
@@ -664,7 +683,8 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |||
664 | dp_priv->DP |= DP_ENHANCED_FRAMING; | 683 | dp_priv->DP |= DP_ENHANCED_FRAMING; |
665 | } | 684 | } |
666 | 685 | ||
667 | if (intel_crtc->pipe == 1) | 686 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
687 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | ||
668 | dp_priv->DP |= DP_PIPEB_SELECT; | 688 | dp_priv->DP |= DP_PIPEB_SELECT; |
669 | 689 | ||
670 | if (IS_eDP(intel_encoder)) { | 690 | if (IS_eDP(intel_encoder)) { |
@@ -704,7 +724,7 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode) | |||
704 | { | 724 | { |
705 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | 725 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
706 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 726 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; |
707 | struct drm_device *dev = intel_encoder->base.dev; | 727 | struct drm_device *dev = encoder->dev; |
708 | struct drm_i915_private *dev_priv = dev->dev_private; | 728 | struct drm_i915_private *dev_priv = dev->dev_private; |
709 | uint32_t dp_reg = I915_READ(dp_priv->output_reg); | 729 | uint32_t dp_reg = I915_READ(dp_priv->output_reg); |
710 | 730 | ||
@@ -749,20 +769,6 @@ intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |||
749 | return link_status[r - DP_LANE0_1_STATUS]; | 769 | return link_status[r - DP_LANE0_1_STATUS]; |
750 | } | 770 | } |
751 | 771 | ||
752 | static void | ||
753 | intel_dp_save(struct drm_connector *connector) | ||
754 | { | ||
755 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
756 | struct drm_device *dev = intel_encoder->base.dev; | ||
757 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
758 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | ||
759 | |||
760 | dp_priv->save_DP = I915_READ(dp_priv->output_reg); | ||
761 | intel_dp_aux_native_read(intel_encoder, DP_LINK_BW_SET, | ||
762 | dp_priv->save_link_configuration, | ||
763 | sizeof (dp_priv->save_link_configuration)); | ||
764 | } | ||
765 | |||
766 | static uint8_t | 772 | static uint8_t |
767 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | 773 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], |
768 | int lane) | 774 | int lane) |
@@ -892,6 +898,25 @@ intel_dp_signal_levels(uint8_t train_set, int lane_count) | |||
892 | return signal_levels; | 898 | return signal_levels; |
893 | } | 899 | } |
894 | 900 | ||
901 | /* Gen6's DP voltage swing and pre-emphasis control */ | ||
902 | static uint32_t | ||
903 | intel_gen6_edp_signal_levels(uint8_t train_set) | ||
904 | { | ||
905 | switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) { | ||
906 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | ||
907 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | ||
908 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | ||
909 | return EDP_LINK_TRAIN_400MV_6DB_SNB_B; | ||
910 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | ||
911 | return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B; | ||
912 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | ||
913 | return EDP_LINK_TRAIN_800MV_0DB_SNB_B; | ||
914 | default: | ||
915 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n"); | ||
916 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | ||
917 | } | ||
918 | } | ||
919 | |||
895 | static uint8_t | 920 | static uint8_t |
896 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | 921 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], |
897 | int lane) | 922 | int lane) |
@@ -948,7 +973,7 @@ intel_dp_set_link_train(struct intel_encoder *intel_encoder, | |||
948 | uint8_t train_set[4], | 973 | uint8_t train_set[4], |
949 | bool first) | 974 | bool first) |
950 | { | 975 | { |
951 | struct drm_device *dev = intel_encoder->base.dev; | 976 | struct drm_device *dev = intel_encoder->enc.dev; |
952 | struct drm_i915_private *dev_priv = dev->dev_private; | 977 | struct drm_i915_private *dev_priv = dev->dev_private; |
953 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 978 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; |
954 | int ret; | 979 | int ret; |
@@ -974,7 +999,7 @@ static void | |||
974 | intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, | 999 | intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, |
975 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]) | 1000 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]) |
976 | { | 1001 | { |
977 | struct drm_device *dev = intel_encoder->base.dev; | 1002 | struct drm_device *dev = intel_encoder->enc.dev; |
978 | struct drm_i915_private *dev_priv = dev->dev_private; | 1003 | struct drm_i915_private *dev_priv = dev->dev_private; |
979 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 1004 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; |
980 | uint8_t train_set[4]; | 1005 | uint8_t train_set[4]; |
@@ -985,23 +1010,38 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, | |||
985 | bool channel_eq = false; | 1010 | bool channel_eq = false; |
986 | bool first = true; | 1011 | bool first = true; |
987 | int tries; | 1012 | int tries; |
1013 | u32 reg; | ||
988 | 1014 | ||
989 | /* Write the link configuration data */ | 1015 | /* Write the link configuration data */ |
990 | intel_dp_aux_native_write(intel_encoder, 0x100, | 1016 | intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET, |
991 | link_configuration, DP_LINK_CONFIGURATION_SIZE); | 1017 | link_configuration, DP_LINK_CONFIGURATION_SIZE); |
992 | 1018 | ||
993 | DP |= DP_PORT_EN; | 1019 | DP |= DP_PORT_EN; |
994 | DP &= ~DP_LINK_TRAIN_MASK; | 1020 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) |
1021 | DP &= ~DP_LINK_TRAIN_MASK_CPT; | ||
1022 | else | ||
1023 | DP &= ~DP_LINK_TRAIN_MASK; | ||
995 | memset(train_set, 0, 4); | 1024 | memset(train_set, 0, 4); |
996 | voltage = 0xff; | 1025 | voltage = 0xff; |
997 | tries = 0; | 1026 | tries = 0; |
998 | clock_recovery = false; | 1027 | clock_recovery = false; |
999 | for (;;) { | 1028 | for (;;) { |
1000 | /* Use train_set[0] to set the voltage and pre emphasis values */ | 1029 | /* Use train_set[0] to set the voltage and pre emphasis values */ |
1001 | uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); | 1030 | uint32_t signal_levels; |
1002 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; | 1031 | if (IS_GEN6(dev) && IS_eDP(intel_encoder)) { |
1032 | signal_levels = intel_gen6_edp_signal_levels(train_set[0]); | ||
1033 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; | ||
1034 | } else { | ||
1035 | signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); | ||
1036 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; | ||
1037 | } | ||
1003 | 1038 | ||
1004 | if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_1, | 1039 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) |
1040 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; | ||
1041 | else | ||
1042 | reg = DP | DP_LINK_TRAIN_PAT_1; | ||
1043 | |||
1044 | if (!intel_dp_set_link_train(intel_encoder, reg, | ||
1005 | DP_TRAINING_PATTERN_1, train_set, first)) | 1045 | DP_TRAINING_PATTERN_1, train_set, first)) |
1006 | break; | 1046 | break; |
1007 | first = false; | 1047 | first = false; |
@@ -1041,11 +1081,23 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, | |||
1041 | channel_eq = false; | 1081 | channel_eq = false; |
1042 | for (;;) { | 1082 | for (;;) { |
1043 | /* Use train_set[0] to set the voltage and pre emphasis values */ | 1083 | /* Use train_set[0] to set the voltage and pre emphasis values */ |
1044 | uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); | 1084 | uint32_t signal_levels; |
1045 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; | 1085 | |
1086 | if (IS_GEN6(dev) && IS_eDP(intel_encoder)) { | ||
1087 | signal_levels = intel_gen6_edp_signal_levels(train_set[0]); | ||
1088 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; | ||
1089 | } else { | ||
1090 | signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); | ||
1091 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; | ||
1092 | } | ||
1093 | |||
1094 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) | ||
1095 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; | ||
1096 | else | ||
1097 | reg = DP | DP_LINK_TRAIN_PAT_2; | ||
1046 | 1098 | ||
1047 | /* channel eq pattern */ | 1099 | /* channel eq pattern */ |
1048 | if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_2, | 1100 | if (!intel_dp_set_link_train(intel_encoder, reg, |
1049 | DP_TRAINING_PATTERN_2, train_set, | 1101 | DP_TRAINING_PATTERN_2, train_set, |
1050 | false)) | 1102 | false)) |
1051 | break; | 1103 | break; |
@@ -1068,7 +1120,12 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, | |||
1068 | ++tries; | 1120 | ++tries; |
1069 | } | 1121 | } |
1070 | 1122 | ||
1071 | I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF); | 1123 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) |
1124 | reg = DP | DP_LINK_TRAIN_OFF_CPT; | ||
1125 | else | ||
1126 | reg = DP | DP_LINK_TRAIN_OFF; | ||
1127 | |||
1128 | I915_WRITE(dp_priv->output_reg, reg); | ||
1072 | POSTING_READ(dp_priv->output_reg); | 1129 | POSTING_READ(dp_priv->output_reg); |
1073 | intel_dp_aux_native_write_1(intel_encoder, | 1130 | intel_dp_aux_native_write_1(intel_encoder, |
1074 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); | 1131 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
@@ -1077,7 +1134,7 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, | |||
1077 | static void | 1134 | static void |
1078 | intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP) | 1135 | intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP) |
1079 | { | 1136 | { |
1080 | struct drm_device *dev = intel_encoder->base.dev; | 1137 | struct drm_device *dev = intel_encoder->enc.dev; |
1081 | struct drm_i915_private *dev_priv = dev->dev_private; | 1138 | struct drm_i915_private *dev_priv = dev->dev_private; |
1082 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 1139 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; |
1083 | 1140 | ||
@@ -1090,9 +1147,15 @@ intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP) | |||
1090 | udelay(100); | 1147 | udelay(100); |
1091 | } | 1148 | } |
1092 | 1149 | ||
1093 | DP &= ~DP_LINK_TRAIN_MASK; | 1150 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) { |
1094 | I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); | 1151 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1095 | POSTING_READ(dp_priv->output_reg); | 1152 | I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
1153 | POSTING_READ(dp_priv->output_reg); | ||
1154 | } else { | ||
1155 | DP &= ~DP_LINK_TRAIN_MASK; | ||
1156 | I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); | ||
1157 | POSTING_READ(dp_priv->output_reg); | ||
1158 | } | ||
1096 | 1159 | ||
1097 | udelay(17000); | 1160 | udelay(17000); |
1098 | 1161 | ||
@@ -1102,18 +1165,6 @@ intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP) | |||
1102 | POSTING_READ(dp_priv->output_reg); | 1165 | POSTING_READ(dp_priv->output_reg); |
1103 | } | 1166 | } |
1104 | 1167 | ||
1105 | static void | ||
1106 | intel_dp_restore(struct drm_connector *connector) | ||
1107 | { | ||
1108 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
1109 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | ||
1110 | |||
1111 | if (dp_priv->save_DP & DP_PORT_EN) | ||
1112 | intel_dp_link_train(intel_encoder, dp_priv->save_DP, dp_priv->save_link_configuration); | ||
1113 | else | ||
1114 | intel_dp_link_down(intel_encoder, dp_priv->save_DP); | ||
1115 | } | ||
1116 | |||
1117 | /* | 1168 | /* |
1118 | * According to DP spec | 1169 | * According to DP spec |
1119 | * 5.1.2: | 1170 | * 5.1.2: |
@@ -1144,7 +1195,8 @@ intel_dp_check_link_status(struct intel_encoder *intel_encoder) | |||
1144 | static enum drm_connector_status | 1195 | static enum drm_connector_status |
1145 | ironlake_dp_detect(struct drm_connector *connector) | 1196 | ironlake_dp_detect(struct drm_connector *connector) |
1146 | { | 1197 | { |
1147 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | 1198 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
1199 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | ||
1148 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 1200 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; |
1149 | enum drm_connector_status status; | 1201 | enum drm_connector_status status; |
1150 | 1202 | ||
@@ -1168,8 +1220,9 @@ ironlake_dp_detect(struct drm_connector *connector) | |||
1168 | static enum drm_connector_status | 1220 | static enum drm_connector_status |
1169 | intel_dp_detect(struct drm_connector *connector) | 1221 | intel_dp_detect(struct drm_connector *connector) |
1170 | { | 1222 | { |
1171 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | 1223 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
1172 | struct drm_device *dev = intel_encoder->base.dev; | 1224 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
1225 | struct drm_device *dev = intel_encoder->enc.dev; | ||
1173 | struct drm_i915_private *dev_priv = dev->dev_private; | 1226 | struct drm_i915_private *dev_priv = dev->dev_private; |
1174 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 1227 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; |
1175 | uint32_t temp, bit; | 1228 | uint32_t temp, bit; |
@@ -1180,16 +1233,6 @@ intel_dp_detect(struct drm_connector *connector) | |||
1180 | if (HAS_PCH_SPLIT(dev)) | 1233 | if (HAS_PCH_SPLIT(dev)) |
1181 | return ironlake_dp_detect(connector); | 1234 | return ironlake_dp_detect(connector); |
1182 | 1235 | ||
1183 | temp = I915_READ(PORT_HOTPLUG_EN); | ||
1184 | |||
1185 | I915_WRITE(PORT_HOTPLUG_EN, | ||
1186 | temp | | ||
1187 | DPB_HOTPLUG_INT_EN | | ||
1188 | DPC_HOTPLUG_INT_EN | | ||
1189 | DPD_HOTPLUG_INT_EN); | ||
1190 | |||
1191 | POSTING_READ(PORT_HOTPLUG_EN); | ||
1192 | |||
1193 | switch (dp_priv->output_reg) { | 1236 | switch (dp_priv->output_reg) { |
1194 | case DP_B: | 1237 | case DP_B: |
1195 | bit = DPB_HOTPLUG_INT_STATUS; | 1238 | bit = DPB_HOTPLUG_INT_STATUS; |
@@ -1222,15 +1265,16 @@ intel_dp_detect(struct drm_connector *connector) | |||
1222 | 1265 | ||
1223 | static int intel_dp_get_modes(struct drm_connector *connector) | 1266 | static int intel_dp_get_modes(struct drm_connector *connector) |
1224 | { | 1267 | { |
1225 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | 1268 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
1226 | struct drm_device *dev = intel_encoder->base.dev; | 1269 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
1270 | struct drm_device *dev = intel_encoder->enc.dev; | ||
1227 | struct drm_i915_private *dev_priv = dev->dev_private; | 1271 | struct drm_i915_private *dev_priv = dev->dev_private; |
1228 | int ret; | 1272 | int ret; |
1229 | 1273 | ||
1230 | /* We should parse the EDID data and find out if it has an audio sink | 1274 | /* We should parse the EDID data and find out if it has an audio sink |
1231 | */ | 1275 | */ |
1232 | 1276 | ||
1233 | ret = intel_ddc_get_modes(intel_encoder); | 1277 | ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus); |
1234 | if (ret) | 1278 | if (ret) |
1235 | return ret; | 1279 | return ret; |
1236 | 1280 | ||
@@ -1249,13 +1293,9 @@ static int intel_dp_get_modes(struct drm_connector *connector) | |||
1249 | static void | 1293 | static void |
1250 | intel_dp_destroy (struct drm_connector *connector) | 1294 | intel_dp_destroy (struct drm_connector *connector) |
1251 | { | 1295 | { |
1252 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
1253 | |||
1254 | if (intel_encoder->i2c_bus) | ||
1255 | intel_i2c_destroy(intel_encoder->i2c_bus); | ||
1256 | drm_sysfs_connector_remove(connector); | 1296 | drm_sysfs_connector_remove(connector); |
1257 | drm_connector_cleanup(connector); | 1297 | drm_connector_cleanup(connector); |
1258 | kfree(intel_encoder); | 1298 | kfree(connector); |
1259 | } | 1299 | } |
1260 | 1300 | ||
1261 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { | 1301 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
@@ -1268,8 +1308,6 @@ static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { | |||
1268 | 1308 | ||
1269 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | 1309 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
1270 | .dpms = drm_helper_connector_dpms, | 1310 | .dpms = drm_helper_connector_dpms, |
1271 | .save = intel_dp_save, | ||
1272 | .restore = intel_dp_restore, | ||
1273 | .detect = intel_dp_detect, | 1311 | .detect = intel_dp_detect, |
1274 | .fill_modes = drm_helper_probe_single_connector_modes, | 1312 | .fill_modes = drm_helper_probe_single_connector_modes, |
1275 | .destroy = intel_dp_destroy, | 1313 | .destroy = intel_dp_destroy, |
@@ -1278,12 +1316,17 @@ static const struct drm_connector_funcs intel_dp_connector_funcs = { | |||
1278 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | 1316 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
1279 | .get_modes = intel_dp_get_modes, | 1317 | .get_modes = intel_dp_get_modes, |
1280 | .mode_valid = intel_dp_mode_valid, | 1318 | .mode_valid = intel_dp_mode_valid, |
1281 | .best_encoder = intel_best_encoder, | 1319 | .best_encoder = intel_attached_encoder, |
1282 | }; | 1320 | }; |
1283 | 1321 | ||
1284 | static void intel_dp_enc_destroy(struct drm_encoder *encoder) | 1322 | static void intel_dp_enc_destroy(struct drm_encoder *encoder) |
1285 | { | 1323 | { |
1324 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | ||
1325 | |||
1326 | if (intel_encoder->i2c_bus) | ||
1327 | intel_i2c_destroy(intel_encoder->i2c_bus); | ||
1286 | drm_encoder_cleanup(encoder); | 1328 | drm_encoder_cleanup(encoder); |
1329 | kfree(intel_encoder); | ||
1287 | } | 1330 | } |
1288 | 1331 | ||
1289 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { | 1332 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
@@ -1299,12 +1342,35 @@ intel_dp_hot_plug(struct intel_encoder *intel_encoder) | |||
1299 | intel_dp_check_link_status(intel_encoder); | 1342 | intel_dp_check_link_status(intel_encoder); |
1300 | } | 1343 | } |
1301 | 1344 | ||
1345 | /* Return which DP Port should be selected for Transcoder DP control */ | ||
1346 | int | ||
1347 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | ||
1348 | { | ||
1349 | struct drm_device *dev = crtc->dev; | ||
1350 | struct drm_mode_config *mode_config = &dev->mode_config; | ||
1351 | struct drm_encoder *encoder; | ||
1352 | struct intel_encoder *intel_encoder = NULL; | ||
1353 | |||
1354 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | ||
1355 | if (!encoder || encoder->crtc != crtc) | ||
1356 | continue; | ||
1357 | |||
1358 | intel_encoder = enc_to_intel_encoder(encoder); | ||
1359 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { | ||
1360 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | ||
1361 | return dp_priv->output_reg; | ||
1362 | } | ||
1363 | } | ||
1364 | return -1; | ||
1365 | } | ||
1366 | |||
1302 | void | 1367 | void |
1303 | intel_dp_init(struct drm_device *dev, int output_reg) | 1368 | intel_dp_init(struct drm_device *dev, int output_reg) |
1304 | { | 1369 | { |
1305 | struct drm_i915_private *dev_priv = dev->dev_private; | 1370 | struct drm_i915_private *dev_priv = dev->dev_private; |
1306 | struct drm_connector *connector; | 1371 | struct drm_connector *connector; |
1307 | struct intel_encoder *intel_encoder; | 1372 | struct intel_encoder *intel_encoder; |
1373 | struct intel_connector *intel_connector; | ||
1308 | struct intel_dp_priv *dp_priv; | 1374 | struct intel_dp_priv *dp_priv; |
1309 | const char *name = NULL; | 1375 | const char *name = NULL; |
1310 | 1376 | ||
@@ -1313,9 +1379,15 @@ intel_dp_init(struct drm_device *dev, int output_reg) | |||
1313 | if (!intel_encoder) | 1379 | if (!intel_encoder) |
1314 | return; | 1380 | return; |
1315 | 1381 | ||
1382 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | ||
1383 | if (!intel_connector) { | ||
1384 | kfree(intel_encoder); | ||
1385 | return; | ||
1386 | } | ||
1387 | |||
1316 | dp_priv = (struct intel_dp_priv *)(intel_encoder + 1); | 1388 | dp_priv = (struct intel_dp_priv *)(intel_encoder + 1); |
1317 | 1389 | ||
1318 | connector = &intel_encoder->base; | 1390 | connector = &intel_connector->base; |
1319 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, | 1391 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, |
1320 | DRM_MODE_CONNECTOR_DisplayPort); | 1392 | DRM_MODE_CONNECTOR_DisplayPort); |
1321 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); | 1393 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
@@ -1349,7 +1421,7 @@ intel_dp_init(struct drm_device *dev, int output_reg) | |||
1349 | DRM_MODE_ENCODER_TMDS); | 1421 | DRM_MODE_ENCODER_TMDS); |
1350 | drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs); | 1422 | drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs); |
1351 | 1423 | ||
1352 | drm_mode_connector_attach_encoder(&intel_encoder->base, | 1424 | drm_mode_connector_attach_encoder(&intel_connector->base, |
1353 | &intel_encoder->enc); | 1425 | &intel_encoder->enc); |
1354 | drm_sysfs_connector_add(connector); | 1426 | drm_sysfs_connector_add(connector); |
1355 | 1427 | ||
@@ -1378,7 +1450,7 @@ intel_dp_init(struct drm_device *dev, int output_reg) | |||
1378 | break; | 1450 | break; |
1379 | } | 1451 | } |
1380 | 1452 | ||
1381 | intel_dp_i2c_init(intel_encoder, name); | 1453 | intel_dp_i2c_init(intel_encoder, intel_connector, name); |
1382 | 1454 | ||
1383 | intel_encoder->ddc_bus = &dp_priv->adapter; | 1455 | intel_encoder->ddc_bus = &dp_priv->adapter; |
1384 | intel_encoder->hot_plug = intel_dp_hot_plug; | 1456 | intel_encoder->hot_plug = intel_dp_hot_plug; |