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path: root/drivers/gpu/drm/i915/intel_dp.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c890
1 files changed, 637 insertions, 253 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9ab8708ac6ba..e2aced6eec4c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -42,30 +42,81 @@
42 42
43#define DP_LINK_CONFIGURATION_SIZE 9 43#define DP_LINK_CONFIGURATION_SIZE 9
44 44
45#define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
46#define IS_PCH_eDP(i) ((i)->is_pch_edp)
47
48struct intel_dp { 45struct intel_dp {
49 struct intel_encoder base; 46 struct intel_encoder base;
50 uint32_t output_reg; 47 uint32_t output_reg;
51 uint32_t DP; 48 uint32_t DP;
52 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
53 bool has_audio; 50 bool has_audio;
54 int dpms_mode; 51 int force_audio;
52 uint32_t color_range;
55 uint8_t link_bw; 53 uint8_t link_bw;
56 uint8_t lane_count; 54 uint8_t lane_count;
57 uint8_t dpcd[4]; 55 uint8_t dpcd[4];
58 struct i2c_adapter adapter; 56 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo; 57 struct i2c_algo_dp_aux_data algo;
60 bool is_pch_edp; 58 bool is_pch_edp;
59 uint8_t train_set[4];
60 uint8_t link_status[DP_LINK_STATUS_SIZE];
61}; 61};
62 62
63/**
64 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
65 * @intel_dp: DP struct
66 *
67 * If a CPU or PCH DP output is attached to an eDP panel, this function
68 * will return true, and false otherwise.
69 */
70static bool is_edp(struct intel_dp *intel_dp)
71{
72 return intel_dp->base.type == INTEL_OUTPUT_EDP;
73}
74
75/**
76 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
77 * @intel_dp: DP struct
78 *
79 * Returns true if the given DP struct corresponds to a PCH DP port attached
80 * to an eDP panel, false otherwise. Helpful for determining whether we
81 * may need FDI resources for a given DP output or not.
82 */
83static bool is_pch_edp(struct intel_dp *intel_dp)
84{
85 return intel_dp->is_pch_edp;
86}
87
63static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 88static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
64{ 89{
65 return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base); 90 return container_of(encoder, struct intel_dp, base.base);
66} 91}
67 92
68static void intel_dp_link_train(struct intel_dp *intel_dp); 93static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
94{
95 return container_of(intel_attached_encoder(connector),
96 struct intel_dp, base);
97}
98
99/**
100 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
101 * @encoder: DRM encoder
102 *
103 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
104 * by intel_display.c.
105 */
106bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
107{
108 struct intel_dp *intel_dp;
109
110 if (!encoder)
111 return false;
112
113 intel_dp = enc_to_intel_dp(encoder);
114
115 return is_pch_edp(intel_dp);
116}
117
118static void intel_dp_start_link_train(struct intel_dp *intel_dp);
119static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
69static void intel_dp_link_down(struct intel_dp *intel_dp); 120static void intel_dp_link_down(struct intel_dp *intel_dp);
70 121
71void 122void
@@ -86,8 +137,8 @@ intel_dp_max_lane_count(struct intel_dp *intel_dp)
86{ 137{
87 int max_lane_count = 4; 138 int max_lane_count = 4;
88 139
89 if (intel_dp->dpcd[0] >= 0x11) { 140 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
90 max_lane_count = intel_dp->dpcd[2] & 0x1f; 141 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
91 switch (max_lane_count) { 142 switch (max_lane_count) {
92 case 1: case 2: case 4: 143 case 1: case 2: case 4:
93 break; 144 break;
@@ -101,7 +152,7 @@ intel_dp_max_lane_count(struct intel_dp *intel_dp)
101static int 152static int
102intel_dp_max_link_bw(struct intel_dp *intel_dp) 153intel_dp_max_link_bw(struct intel_dp *intel_dp)
103{ 154{
104 int max_link_bw = intel_dp->dpcd[1]; 155 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
105 156
106 switch (max_link_bw) { 157 switch (max_link_bw) {
107 case DP_LINK_BW_1_62: 158 case DP_LINK_BW_1_62:
@@ -129,8 +180,8 @@ intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pi
129{ 180{
130 struct drm_i915_private *dev_priv = dev->dev_private; 181 struct drm_i915_private *dev_priv = dev->dev_private;
131 182
132 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 183 if (is_edp(intel_dp))
133 return (pixel_clock * dev_priv->edp_bpp) / 8; 184 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
134 else 185 else
135 return pixel_clock * 3; 186 return pixel_clock * 3;
136} 187}
@@ -145,15 +196,13 @@ static int
145intel_dp_mode_valid(struct drm_connector *connector, 196intel_dp_mode_valid(struct drm_connector *connector,
146 struct drm_display_mode *mode) 197 struct drm_display_mode *mode)
147{ 198{
148 struct drm_encoder *encoder = intel_attached_encoder(connector); 199 struct intel_dp *intel_dp = intel_attached_dp(connector);
149 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
150 struct drm_device *dev = connector->dev; 200 struct drm_device *dev = connector->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private; 201 struct drm_i915_private *dev_priv = dev->dev_private;
152 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 202 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
153 int max_lanes = intel_dp_max_lane_count(intel_dp); 203 int max_lanes = intel_dp_max_lane_count(intel_dp);
154 204
155 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && 205 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
156 dev_priv->panel_fixed_mode) {
157 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 206 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
158 return MODE_PANEL; 207 return MODE_PANEL;
159 208
@@ -161,9 +210,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
161 return MODE_PANEL; 210 return MODE_PANEL;
162 } 211 }
163 212
164 /* only refuse the mode on non eDP since we have seen some wierd eDP panels 213 /* only refuse the mode on non eDP since we have seen some weird eDP panels
165 which are outside spec tolerances but somehow work by magic */ 214 which are outside spec tolerances but somehow work by magic */
166 if (!IS_eDP(intel_dp) && 215 if (!is_edp(intel_dp) &&
167 (intel_dp_link_required(connector->dev, intel_dp, mode->clock) 216 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
168 > intel_dp_max_data_rate(max_link_clock, max_lanes))) 217 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
169 return MODE_CLOCK_HIGH; 218 return MODE_CLOCK_HIGH;
@@ -233,7 +282,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
233 uint8_t *recv, int recv_size) 282 uint8_t *recv, int recv_size)
234{ 283{
235 uint32_t output_reg = intel_dp->output_reg; 284 uint32_t output_reg = intel_dp->output_reg;
236 struct drm_device *dev = intel_dp->base.enc.dev; 285 struct drm_device *dev = intel_dp->base.base.dev;
237 struct drm_i915_private *dev_priv = dev->dev_private; 286 struct drm_i915_private *dev_priv = dev->dev_private;
238 uint32_t ch_ctl = output_reg + 0x10; 287 uint32_t ch_ctl = output_reg + 0x10;
239 uint32_t ch_data = ch_ctl + 4; 288 uint32_t ch_data = ch_ctl + 4;
@@ -246,8 +295,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
246 /* The clock divider is based off the hrawclk, 295 /* The clock divider is based off the hrawclk,
247 * and would like to run at 2MHz. So, take the 296 * and would like to run at 2MHz. So, take the
248 * hrawclk value and divide by 2 and use that 297 * hrawclk value and divide by 2 and use that
298 *
299 * Note that PCH attached eDP panels should use a 125MHz input
300 * clock divider.
249 */ 301 */
250 if (IS_eDP(intel_dp)) { 302 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
251 if (IS_GEN6(dev)) 303 if (IS_GEN6(dev))
252 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ 304 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
253 else 305 else
@@ -425,6 +477,7 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
425 uint16_t address = algo_data->address; 477 uint16_t address = algo_data->address;
426 uint8_t msg[5]; 478 uint8_t msg[5];
427 uint8_t reply[2]; 479 uint8_t reply[2];
480 unsigned retry;
428 int msg_bytes; 481 int msg_bytes;
429 int reply_bytes; 482 int reply_bytes;
430 int ret; 483 int ret;
@@ -459,14 +512,33 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
459 break; 512 break;
460 } 513 }
461 514
462 for (;;) { 515 for (retry = 0; retry < 5; retry++) {
463 ret = intel_dp_aux_ch(intel_dp, 516 ret = intel_dp_aux_ch(intel_dp,
464 msg, msg_bytes, 517 msg, msg_bytes,
465 reply, reply_bytes); 518 reply, reply_bytes);
466 if (ret < 0) { 519 if (ret < 0) {
467 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 520 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
468 return ret; 521 return ret;
469 } 522 }
523
524 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
525 case AUX_NATIVE_REPLY_ACK:
526 /* I2C-over-AUX Reply field is only valid
527 * when paired with AUX ACK.
528 */
529 break;
530 case AUX_NATIVE_REPLY_NACK:
531 DRM_DEBUG_KMS("aux_ch native nack\n");
532 return -EREMOTEIO;
533 case AUX_NATIVE_REPLY_DEFER:
534 udelay(100);
535 continue;
536 default:
537 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
538 reply[0]);
539 return -EREMOTEIO;
540 }
541
470 switch (reply[0] & AUX_I2C_REPLY_MASK) { 542 switch (reply[0] & AUX_I2C_REPLY_MASK) {
471 case AUX_I2C_REPLY_ACK: 543 case AUX_I2C_REPLY_ACK:
472 if (mode == MODE_I2C_READ) { 544 if (mode == MODE_I2C_READ) {
@@ -474,17 +546,20 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
474 } 546 }
475 return reply_bytes - 1; 547 return reply_bytes - 1;
476 case AUX_I2C_REPLY_NACK: 548 case AUX_I2C_REPLY_NACK:
477 DRM_DEBUG_KMS("aux_ch nack\n"); 549 DRM_DEBUG_KMS("aux_i2c nack\n");
478 return -EREMOTEIO; 550 return -EREMOTEIO;
479 case AUX_I2C_REPLY_DEFER: 551 case AUX_I2C_REPLY_DEFER:
480 DRM_DEBUG_KMS("aux_ch defer\n"); 552 DRM_DEBUG_KMS("aux_i2c defer\n");
481 udelay(100); 553 udelay(100);
482 break; 554 break;
483 default: 555 default:
484 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]); 556 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
485 return -EREMOTEIO; 557 return -EREMOTEIO;
486 } 558 }
487 } 559 }
560
561 DRM_ERROR("too many retries, giving up\n");
562 return -EREMOTEIO;
488} 563}
489 564
490static int 565static int
@@ -519,8 +594,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
519 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 594 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
520 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 595 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
521 596
522 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && 597 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
523 dev_priv->panel_fixed_mode) {
524 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); 598 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
525 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 599 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
526 mode, adjusted_mode); 600 mode, adjusted_mode);
@@ -549,7 +623,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
549 } 623 }
550 } 624 }
551 625
552 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { 626 if (is_edp(intel_dp)) {
553 /* okay we failed just pick the highest */ 627 /* okay we failed just pick the highest */
554 intel_dp->lane_count = max_lane_count; 628 intel_dp->lane_count = max_lane_count;
555 intel_dp->link_bw = bws[max_clock]; 629 intel_dp->link_bw = bws[max_clock];
@@ -598,25 +672,6 @@ intel_dp_compute_m_n(int bpp,
598 intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 672 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
599} 673}
600 674
601bool intel_pch_has_edp(struct drm_crtc *crtc)
602{
603 struct drm_device *dev = crtc->dev;
604 struct drm_mode_config *mode_config = &dev->mode_config;
605 struct drm_encoder *encoder;
606
607 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
608 struct intel_dp *intel_dp;
609
610 if (encoder->crtc != crtc)
611 continue;
612
613 intel_dp = enc_to_intel_dp(encoder);
614 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
615 return intel_dp->is_pch_edp;
616 }
617 return false;
618}
619
620void 675void
621intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 676intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
622 struct drm_display_mode *adjusted_mode) 677 struct drm_display_mode *adjusted_mode)
@@ -628,6 +683,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
629 int lane_count = 4, bpp = 24; 684 int lane_count = 4, bpp = 24;
630 struct intel_dp_m_n m_n; 685 struct intel_dp_m_n m_n;
686 int pipe = intel_crtc->pipe;
631 687
632 /* 688 /*
633 * Find the lane count in the intel_encoder private 689 * Find the lane count in the intel_encoder private
@@ -641,8 +697,10 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
641 intel_dp = enc_to_intel_dp(encoder); 697 intel_dp = enc_to_intel_dp(encoder);
642 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { 698 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
643 lane_count = intel_dp->lane_count; 699 lane_count = intel_dp->lane_count;
644 if (IS_PCH_eDP(intel_dp)) 700 break;
645 bpp = dev_priv->edp_bpp; 701 } else if (is_edp(intel_dp)) {
702 lane_count = dev_priv->edp.lanes;
703 bpp = dev_priv->edp.bpp;
646 break; 704 break;
647 } 705 }
648 } 706 }
@@ -656,39 +714,19 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
656 mode->clock, adjusted_mode->clock, &m_n); 714 mode->clock, adjusted_mode->clock, &m_n);
657 715
658 if (HAS_PCH_SPLIT(dev)) { 716 if (HAS_PCH_SPLIT(dev)) {
659 if (intel_crtc->pipe == 0) { 717 I915_WRITE(TRANSDATA_M1(pipe),
660 I915_WRITE(TRANSA_DATA_M1, 718 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
661 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 719 m_n.gmch_m);
662 m_n.gmch_m); 720 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
663 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); 721 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
664 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); 722 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
665 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
666 } else {
667 I915_WRITE(TRANSB_DATA_M1,
668 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
669 m_n.gmch_m);
670 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
671 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
672 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
673 }
674 } else { 723 } else {
675 if (intel_crtc->pipe == 0) { 724 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
676 I915_WRITE(PIPEA_GMCH_DATA_M, 725 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
677 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 726 m_n.gmch_m);
678 m_n.gmch_m); 727 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
679 I915_WRITE(PIPEA_GMCH_DATA_N, 728 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
680 m_n.gmch_n); 729 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
681 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
682 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
683 } else {
684 I915_WRITE(PIPEB_GMCH_DATA_M,
685 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
686 m_n.gmch_m);
687 I915_WRITE(PIPEB_GMCH_DATA_N,
688 m_n.gmch_n);
689 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
690 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
691 }
692 } 730 }
693} 731}
694 732
@@ -698,18 +736,18 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
698{ 736{
699 struct drm_device *dev = encoder->dev; 737 struct drm_device *dev = encoder->dev;
700 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 738 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
701 struct drm_crtc *crtc = intel_dp->base.enc.crtc; 739 struct drm_crtc *crtc = intel_dp->base.base.crtc;
702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
703 741
704 intel_dp->DP = (DP_VOLTAGE_0_4 | 742 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
705 DP_PRE_EMPHASIS_0); 743 intel_dp->DP |= intel_dp->color_range;
706 744
707 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 745 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
708 intel_dp->DP |= DP_SYNC_HS_HIGH; 746 intel_dp->DP |= DP_SYNC_HS_HIGH;
709 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 747 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
710 intel_dp->DP |= DP_SYNC_VS_HIGH; 748 intel_dp->DP |= DP_SYNC_VS_HIGH;
711 749
712 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 750 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
713 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 751 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
714 else 752 else
715 intel_dp->DP |= DP_LINK_TRAIN_OFF; 753 intel_dp->DP |= DP_LINK_TRAIN_OFF;
@@ -735,7 +773,8 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
735 /* 773 /*
736 * Check for DPCD version > 1.1 and enhanced framing support 774 * Check for DPCD version > 1.1 and enhanced framing support
737 */ 775 */
738 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 776 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
777 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
739 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 778 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
740 intel_dp->DP |= DP_ENHANCED_FRAMING; 779 intel_dp->DP |= DP_ENHANCED_FRAMING;
741 } 780 }
@@ -744,7 +783,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
744 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) 783 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
745 intel_dp->DP |= DP_PIPEB_SELECT; 784 intel_dp->DP |= DP_PIPEB_SELECT;
746 785
747 if (IS_eDP(intel_dp)) { 786 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
748 /* don't miss out required setting for eDP */ 787 /* don't miss out required setting for eDP */
749 intel_dp->DP |= DP_PLL_ENABLE; 788 intel_dp->DP |= DP_PLL_ENABLE;
750 if (adjusted_mode->clock < 200000) 789 if (adjusted_mode->clock < 200000)
@@ -754,13 +793,49 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
754 } 793 }
755} 794}
756 795
757static void ironlake_edp_panel_on (struct drm_device *dev) 796static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
797{
798 struct drm_device *dev = intel_dp->base.base.dev;
799 struct drm_i915_private *dev_priv = dev->dev_private;
800 u32 pp;
801
802 /*
803 * If the panel wasn't on, make sure there's not a currently
804 * active PP sequence before enabling AUX VDD.
805 */
806 if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
807 msleep(dev_priv->panel_t3);
808
809 pp = I915_READ(PCH_PP_CONTROL);
810 pp |= EDP_FORCE_VDD;
811 I915_WRITE(PCH_PP_CONTROL, pp);
812 POSTING_READ(PCH_PP_CONTROL);
813}
814
815static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
758{ 816{
817 struct drm_device *dev = intel_dp->base.base.dev;
759 struct drm_i915_private *dev_priv = dev->dev_private; 818 struct drm_i915_private *dev_priv = dev->dev_private;
760 u32 pp; 819 u32 pp;
761 820
821 pp = I915_READ(PCH_PP_CONTROL);
822 pp &= ~EDP_FORCE_VDD;
823 I915_WRITE(PCH_PP_CONTROL, pp);
824 POSTING_READ(PCH_PP_CONTROL);
825
826 /* Make sure sequencer is idle before allowing subsequent activity */
827 msleep(dev_priv->panel_t12);
828}
829
830/* Returns true if the panel was already on when called */
831static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
832{
833 struct drm_device *dev = intel_dp->base.base.dev;
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
836
762 if (I915_READ(PCH_PP_STATUS) & PP_ON) 837 if (I915_READ(PCH_PP_STATUS) & PP_ON)
763 return; 838 return true;
764 839
765 pp = I915_READ(PCH_PP_CONTROL); 840 pp = I915_READ(PCH_PP_CONTROL);
766 841
@@ -771,21 +846,25 @@ static void ironlake_edp_panel_on (struct drm_device *dev)
771 846
772 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 847 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
773 I915_WRITE(PCH_PP_CONTROL, pp); 848 I915_WRITE(PCH_PP_CONTROL, pp);
849 POSTING_READ(PCH_PP_CONTROL);
774 850
775 if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000, 10)) 851 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
852 5000))
776 DRM_ERROR("panel on wait timed out: 0x%08x\n", 853 DRM_ERROR("panel on wait timed out: 0x%08x\n",
777 I915_READ(PCH_PP_STATUS)); 854 I915_READ(PCH_PP_STATUS));
778 855
779 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
780 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 856 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
781 I915_WRITE(PCH_PP_CONTROL, pp); 857 I915_WRITE(PCH_PP_CONTROL, pp);
782 POSTING_READ(PCH_PP_CONTROL); 858 POSTING_READ(PCH_PP_CONTROL);
859
860 return false;
783} 861}
784 862
785static void ironlake_edp_panel_off (struct drm_device *dev) 863static void ironlake_edp_panel_off (struct drm_device *dev)
786{ 864{
787 struct drm_i915_private *dev_priv = dev->dev_private; 865 struct drm_i915_private *dev_priv = dev->dev_private;
788 u32 pp; 866 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
867 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
789 868
790 pp = I915_READ(PCH_PP_CONTROL); 869 pp = I915_READ(PCH_PP_CONTROL);
791 870
@@ -796,13 +875,13 @@ static void ironlake_edp_panel_off (struct drm_device *dev)
796 875
797 pp &= ~POWER_TARGET_ON; 876 pp &= ~POWER_TARGET_ON;
798 I915_WRITE(PCH_PP_CONTROL, pp); 877 I915_WRITE(PCH_PP_CONTROL, pp);
878 POSTING_READ(PCH_PP_CONTROL);
799 879
800 if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000, 10)) 880 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
801 DRM_ERROR("panel off wait timed out: 0x%08x\n", 881 DRM_ERROR("panel off wait timed out: 0x%08x\n",
802 I915_READ(PCH_PP_STATUS)); 882 I915_READ(PCH_PP_STATUS));
803 883
804 /* Make sure VDD is enabled so DP AUX will work */ 884 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
805 pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */
806 I915_WRITE(PCH_PP_CONTROL, pp); 885 I915_WRITE(PCH_PP_CONTROL, pp);
807 POSTING_READ(PCH_PP_CONTROL); 886 POSTING_READ(PCH_PP_CONTROL);
808} 887}
@@ -813,6 +892,13 @@ static void ironlake_edp_backlight_on (struct drm_device *dev)
813 u32 pp; 892 u32 pp;
814 893
815 DRM_DEBUG_KMS("\n"); 894 DRM_DEBUG_KMS("\n");
895 /*
896 * If we enable the backlight right away following a panel power
897 * on, we may see slight flicker as the panel syncs with the eDP
898 * link. So delay a bit to make sure the image is solid before
899 * allowing it to appear.
900 */
901 msleep(300);
816 pp = I915_READ(PCH_PP_CONTROL); 902 pp = I915_READ(PCH_PP_CONTROL);
817 pp |= EDP_BLC_ENABLE; 903 pp |= EDP_BLC_ENABLE;
818 I915_WRITE(PCH_PP_CONTROL, pp); 904 I915_WRITE(PCH_PP_CONTROL, pp);
@@ -837,8 +923,10 @@ static void ironlake_edp_pll_on(struct drm_encoder *encoder)
837 923
838 DRM_DEBUG_KMS("\n"); 924 DRM_DEBUG_KMS("\n");
839 dpa_ctl = I915_READ(DP_A); 925 dpa_ctl = I915_READ(DP_A);
840 dpa_ctl &= ~DP_PLL_ENABLE; 926 dpa_ctl |= DP_PLL_ENABLE;
841 I915_WRITE(DP_A, dpa_ctl); 927 I915_WRITE(DP_A, dpa_ctl);
928 POSTING_READ(DP_A);
929 udelay(200);
842} 930}
843 931
844static void ironlake_edp_pll_off(struct drm_encoder *encoder) 932static void ironlake_edp_pll_off(struct drm_encoder *encoder)
@@ -848,38 +936,79 @@ static void ironlake_edp_pll_off(struct drm_encoder *encoder)
848 u32 dpa_ctl; 936 u32 dpa_ctl;
849 937
850 dpa_ctl = I915_READ(DP_A); 938 dpa_ctl = I915_READ(DP_A);
851 dpa_ctl |= DP_PLL_ENABLE; 939 dpa_ctl &= ~DP_PLL_ENABLE;
852 I915_WRITE(DP_A, dpa_ctl); 940 I915_WRITE(DP_A, dpa_ctl);
941 POSTING_READ(DP_A);
853 udelay(200); 942 udelay(200);
854} 943}
855 944
945/* If the sink supports it, try to set the power state appropriately */
946static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
947{
948 int ret, i;
949
950 /* Should have a valid DPCD by this point */
951 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
952 return;
953
954 if (mode != DRM_MODE_DPMS_ON) {
955 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
956 DP_SET_POWER_D3);
957 if (ret != 1)
958 DRM_DEBUG_DRIVER("failed to write sink power state\n");
959 } else {
960 /*
961 * When turning on, we need to retry for 1ms to give the sink
962 * time to wake up.
963 */
964 for (i = 0; i < 3; i++) {
965 ret = intel_dp_aux_native_write_1(intel_dp,
966 DP_SET_POWER,
967 DP_SET_POWER_D0);
968 if (ret == 1)
969 break;
970 msleep(1);
971 }
972 }
973}
974
856static void intel_dp_prepare(struct drm_encoder *encoder) 975static void intel_dp_prepare(struct drm_encoder *encoder)
857{ 976{
858 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 977 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
859 struct drm_device *dev = encoder->dev; 978 struct drm_device *dev = encoder->dev;
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
862 979
863 if (IS_eDP(intel_dp)) { 980 /* Wake up the sink first */
981 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
982
983 if (is_edp(intel_dp)) {
864 ironlake_edp_backlight_off(dev); 984 ironlake_edp_backlight_off(dev);
865 ironlake_edp_panel_on(dev); 985 ironlake_edp_panel_off(dev);
866 ironlake_edp_pll_on(encoder); 986 if (!is_pch_edp(intel_dp))
987 ironlake_edp_pll_on(encoder);
988 else
989 ironlake_edp_pll_off(encoder);
867 } 990 }
868 if (dp_reg & DP_PORT_EN) 991 intel_dp_link_down(intel_dp);
869 intel_dp_link_down(intel_dp);
870} 992}
871 993
872static void intel_dp_commit(struct drm_encoder *encoder) 994static void intel_dp_commit(struct drm_encoder *encoder)
873{ 995{
874 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 996 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
875 struct drm_device *dev = encoder->dev; 997 struct drm_device *dev = encoder->dev;
876 struct drm_i915_private *dev_priv = dev->dev_private;
877 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
878 998
879 if (!(dp_reg & DP_PORT_EN)) { 999 if (is_edp(intel_dp))
880 intel_dp_link_train(intel_dp); 1000 ironlake_edp_panel_vdd_on(intel_dp);
1001
1002 intel_dp_start_link_train(intel_dp);
1003
1004 if (is_edp(intel_dp)) {
1005 ironlake_edp_panel_on(intel_dp);
1006 ironlake_edp_panel_vdd_off(intel_dp);
881 } 1007 }
882 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 1008
1009 intel_dp_complete_link_train(intel_dp);
1010
1011 if (is_edp(intel_dp))
883 ironlake_edp_backlight_on(dev); 1012 ironlake_edp_backlight_on(dev);
884} 1013}
885 1014
@@ -892,24 +1021,54 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
892 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1021 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
893 1022
894 if (mode != DRM_MODE_DPMS_ON) { 1023 if (mode != DRM_MODE_DPMS_ON) {
895 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { 1024 if (is_edp(intel_dp))
896 ironlake_edp_backlight_off(dev); 1025 ironlake_edp_backlight_off(dev);
1026 intel_dp_sink_dpms(intel_dp, mode);
1027 intel_dp_link_down(intel_dp);
1028 if (is_edp(intel_dp))
897 ironlake_edp_panel_off(dev); 1029 ironlake_edp_panel_off(dev);
898 } 1030 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
899 if (dp_reg & DP_PORT_EN)
900 intel_dp_link_down(intel_dp);
901 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
902 ironlake_edp_pll_off(encoder); 1031 ironlake_edp_pll_off(encoder);
903 } else { 1032 } else {
1033 if (is_edp(intel_dp))
1034 ironlake_edp_panel_vdd_on(intel_dp);
1035 intel_dp_sink_dpms(intel_dp, mode);
904 if (!(dp_reg & DP_PORT_EN)) { 1036 if (!(dp_reg & DP_PORT_EN)) {
905 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 1037 intel_dp_start_link_train(intel_dp);
906 ironlake_edp_panel_on(dev); 1038 if (is_edp(intel_dp)) {
907 intel_dp_link_train(intel_dp); 1039 ironlake_edp_panel_on(intel_dp);
908 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 1040 ironlake_edp_panel_vdd_off(intel_dp);
909 ironlake_edp_backlight_on(dev); 1041 }
1042 intel_dp_complete_link_train(intel_dp);
910 } 1043 }
1044 if (is_edp(intel_dp))
1045 ironlake_edp_backlight_on(dev);
1046 }
1047}
1048
1049/*
1050 * Native read with retry for link status and receiver capability reads for
1051 * cases where the sink may still be asleep.
1052 */
1053static bool
1054intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1055 uint8_t *recv, int recv_bytes)
1056{
1057 int ret, i;
1058
1059 /*
1060 * Sinks are *supposed* to come up within 1ms from an off state,
1061 * but we're also supposed to retry 3 times per the spec.
1062 */
1063 for (i = 0; i < 3; i++) {
1064 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1065 recv_bytes);
1066 if (ret == recv_bytes)
1067 return true;
1068 msleep(1);
911 } 1069 }
912 intel_dp->dpms_mode = mode; 1070
1071 return false;
913} 1072}
914 1073
915/* 1074/*
@@ -917,17 +1076,12 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
917 * link status information 1076 * link status information
918 */ 1077 */
919static bool 1078static bool
920intel_dp_get_link_status(struct intel_dp *intel_dp, 1079intel_dp_get_link_status(struct intel_dp *intel_dp)
921 uint8_t link_status[DP_LINK_STATUS_SIZE])
922{ 1080{
923 int ret; 1081 return intel_dp_aux_native_read_retry(intel_dp,
924 1082 DP_LANE0_1_STATUS,
925 ret = intel_dp_aux_native_read(intel_dp, 1083 intel_dp->link_status,
926 DP_LANE0_1_STATUS, 1084 DP_LINK_STATUS_SIZE);
927 link_status, DP_LINK_STATUS_SIZE);
928 if (ret != DP_LINK_STATUS_SIZE)
929 return false;
930 return true;
931} 1085}
932 1086
933static uint8_t 1087static uint8_t
@@ -999,18 +1153,15 @@ intel_dp_pre_emphasis_max(uint8_t voltage_swing)
999} 1153}
1000 1154
1001static void 1155static void
1002intel_get_adjust_train(struct intel_dp *intel_dp, 1156intel_get_adjust_train(struct intel_dp *intel_dp)
1003 uint8_t link_status[DP_LINK_STATUS_SIZE],
1004 int lane_count,
1005 uint8_t train_set[4])
1006{ 1157{
1007 uint8_t v = 0; 1158 uint8_t v = 0;
1008 uint8_t p = 0; 1159 uint8_t p = 0;
1009 int lane; 1160 int lane;
1010 1161
1011 for (lane = 0; lane < lane_count; lane++) { 1162 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1012 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane); 1163 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1013 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane); 1164 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1014 1165
1015 if (this_v > v) 1166 if (this_v > v)
1016 v = this_v; 1167 v = this_v;
@@ -1025,7 +1176,7 @@ intel_get_adjust_train(struct intel_dp *intel_dp,
1025 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1176 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1026 1177
1027 for (lane = 0; lane < 4; lane++) 1178 for (lane = 0; lane < 4; lane++)
1028 train_set[lane] = v | p; 1179 intel_dp->train_set[lane] = v | p;
1029} 1180}
1030 1181
1031static uint32_t 1182static uint32_t
@@ -1070,18 +1221,27 @@ intel_dp_signal_levels(uint8_t train_set, int lane_count)
1070static uint32_t 1221static uint32_t
1071intel_gen6_edp_signal_levels(uint8_t train_set) 1222intel_gen6_edp_signal_levels(uint8_t train_set)
1072{ 1223{
1073 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) { 1224 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1225 DP_TRAIN_PRE_EMPHASIS_MASK);
1226 switch (signal_levels) {
1074 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1227 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1075 return EDP_LINK_TRAIN_400MV_0DB_SNB_B; 1228 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1229 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1230 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1231 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1076 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1232 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1077 return EDP_LINK_TRAIN_400MV_6DB_SNB_B; 1233 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1234 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1078 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1235 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1079 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B; 1236 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1237 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1080 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1238 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1081 return EDP_LINK_TRAIN_800MV_0DB_SNB_B; 1239 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1240 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1082 default: 1241 default:
1083 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n"); 1242 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1084 return EDP_LINK_TRAIN_400MV_0DB_SNB_B; 1243 "0x%x\n", signal_levels);
1244 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1085 } 1245 }
1086} 1246}
1087 1247
@@ -1116,18 +1276,18 @@ intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count
1116 DP_LANE_CHANNEL_EQ_DONE|\ 1276 DP_LANE_CHANNEL_EQ_DONE|\
1117 DP_LANE_SYMBOL_LOCKED) 1277 DP_LANE_SYMBOL_LOCKED)
1118static bool 1278static bool
1119intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1279intel_channel_eq_ok(struct intel_dp *intel_dp)
1120{ 1280{
1121 uint8_t lane_align; 1281 uint8_t lane_align;
1122 uint8_t lane_status; 1282 uint8_t lane_status;
1123 int lane; 1283 int lane;
1124 1284
1125 lane_align = intel_dp_link_status(link_status, 1285 lane_align = intel_dp_link_status(intel_dp->link_status,
1126 DP_LANE_ALIGN_STATUS_UPDATED); 1286 DP_LANE_ALIGN_STATUS_UPDATED);
1127 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1287 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1128 return false; 1288 return false;
1129 for (lane = 0; lane < lane_count; lane++) { 1289 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1130 lane_status = intel_get_lane_status(link_status, lane); 1290 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1131 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1291 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1132 return false; 1292 return false;
1133 } 1293 }
@@ -1137,10 +1297,9 @@ intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1137static bool 1297static bool
1138intel_dp_set_link_train(struct intel_dp *intel_dp, 1298intel_dp_set_link_train(struct intel_dp *intel_dp,
1139 uint32_t dp_reg_value, 1299 uint32_t dp_reg_value,
1140 uint8_t dp_train_pat, 1300 uint8_t dp_train_pat)
1141 uint8_t train_set[4])
1142{ 1301{
1143 struct drm_device *dev = intel_dp->base.enc.dev; 1302 struct drm_device *dev = intel_dp->base.base.dev;
1144 struct drm_i915_private *dev_priv = dev->dev_private; 1303 struct drm_i915_private *dev_priv = dev->dev_private;
1145 int ret; 1304 int ret;
1146 1305
@@ -1152,28 +1311,27 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
1152 dp_train_pat); 1311 dp_train_pat);
1153 1312
1154 ret = intel_dp_aux_native_write(intel_dp, 1313 ret = intel_dp_aux_native_write(intel_dp,
1155 DP_TRAINING_LANE0_SET, train_set, 4); 1314 DP_TRAINING_LANE0_SET,
1315 intel_dp->train_set, 4);
1156 if (ret != 4) 1316 if (ret != 4)
1157 return false; 1317 return false;
1158 1318
1159 return true; 1319 return true;
1160} 1320}
1161 1321
1322/* Enable corresponding port and start training pattern 1 */
1162static void 1323static void
1163intel_dp_link_train(struct intel_dp *intel_dp) 1324intel_dp_start_link_train(struct intel_dp *intel_dp)
1164{ 1325{
1165 struct drm_device *dev = intel_dp->base.enc.dev; 1326 struct drm_device *dev = intel_dp->base.base.dev;
1166 struct drm_i915_private *dev_priv = dev->dev_private; 1327 struct drm_i915_private *dev_priv = dev->dev_private;
1167 uint8_t train_set[4]; 1328 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1168 uint8_t link_status[DP_LINK_STATUS_SIZE];
1169 int i; 1329 int i;
1170 uint8_t voltage; 1330 uint8_t voltage;
1171 bool clock_recovery = false; 1331 bool clock_recovery = false;
1172 bool channel_eq = false;
1173 int tries; 1332 int tries;
1174 u32 reg; 1333 u32 reg;
1175 uint32_t DP = intel_dp->DP; 1334 uint32_t DP = intel_dp->DP;
1176 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc);
1177 1335
1178 /* Enable output, wait for it to become active */ 1336 /* Enable output, wait for it to become active */
1179 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 1337 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
@@ -1186,108 +1344,140 @@ intel_dp_link_train(struct intel_dp *intel_dp)
1186 DP_LINK_CONFIGURATION_SIZE); 1344 DP_LINK_CONFIGURATION_SIZE);
1187 1345
1188 DP |= DP_PORT_EN; 1346 DP |= DP_PORT_EN;
1189 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1347 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1190 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1348 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1191 else 1349 else
1192 DP &= ~DP_LINK_TRAIN_MASK; 1350 DP &= ~DP_LINK_TRAIN_MASK;
1193 memset(train_set, 0, 4); 1351 memset(intel_dp->train_set, 0, 4);
1194 voltage = 0xff; 1352 voltage = 0xff;
1195 tries = 0; 1353 tries = 0;
1196 clock_recovery = false; 1354 clock_recovery = false;
1197 for (;;) { 1355 for (;;) {
1198 /* Use train_set[0] to set the voltage and pre emphasis values */ 1356 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1199 uint32_t signal_levels; 1357 uint32_t signal_levels;
1200 if (IS_GEN6(dev) && IS_eDP(intel_dp)) { 1358 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1201 signal_levels = intel_gen6_edp_signal_levels(train_set[0]); 1359 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1202 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1360 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1203 } else { 1361 } else {
1204 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); 1362 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1205 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1363 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1206 } 1364 }
1207 1365
1208 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1366 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1209 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1367 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1210 else 1368 else
1211 reg = DP | DP_LINK_TRAIN_PAT_1; 1369 reg = DP | DP_LINK_TRAIN_PAT_1;
1212 1370
1213 if (!intel_dp_set_link_train(intel_dp, reg, 1371 if (!intel_dp_set_link_train(intel_dp, reg,
1214 DP_TRAINING_PATTERN_1, train_set)) 1372 DP_TRAINING_PATTERN_1))
1215 break; 1373 break;
1216 /* Set training pattern 1 */ 1374 /* Set training pattern 1 */
1217 1375
1218 udelay(100); 1376 udelay(100);
1219 if (!intel_dp_get_link_status(intel_dp, link_status)) 1377 if (!intel_dp_get_link_status(intel_dp))
1220 break; 1378 break;
1221 1379
1222 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1380 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1223 clock_recovery = true; 1381 clock_recovery = true;
1224 break; 1382 break;
1225 } 1383 }
1226 1384
1227 /* Check to see if we've tried the max voltage */ 1385 /* Check to see if we've tried the max voltage */
1228 for (i = 0; i < intel_dp->lane_count; i++) 1386 for (i = 0; i < intel_dp->lane_count; i++)
1229 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1387 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1230 break; 1388 break;
1231 if (i == intel_dp->lane_count) 1389 if (i == intel_dp->lane_count)
1232 break; 1390 break;
1233 1391
1234 /* Check to see if we've tried the same voltage 5 times */ 1392 /* Check to see if we've tried the same voltage 5 times */
1235 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1393 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1236 ++tries; 1394 ++tries;
1237 if (tries == 5) 1395 if (tries == 5)
1238 break; 1396 break;
1239 } else 1397 } else
1240 tries = 0; 1398 tries = 0;
1241 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1399 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1242 1400
1243 /* Compute new train_set as requested by target */ 1401 /* Compute new intel_dp->train_set as requested by target */
1244 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); 1402 intel_get_adjust_train(intel_dp);
1245 } 1403 }
1246 1404
1405 intel_dp->DP = DP;
1406}
1407
1408static void
1409intel_dp_complete_link_train(struct intel_dp *intel_dp)
1410{
1411 struct drm_device *dev = intel_dp->base.base.dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 bool channel_eq = false;
1414 int tries, cr_tries;
1415 u32 reg;
1416 uint32_t DP = intel_dp->DP;
1417
1247 /* channel equalization */ 1418 /* channel equalization */
1248 tries = 0; 1419 tries = 0;
1420 cr_tries = 0;
1249 channel_eq = false; 1421 channel_eq = false;
1250 for (;;) { 1422 for (;;) {
1251 /* Use train_set[0] to set the voltage and pre emphasis values */ 1423 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1252 uint32_t signal_levels; 1424 uint32_t signal_levels;
1253 1425
1254 if (IS_GEN6(dev) && IS_eDP(intel_dp)) { 1426 if (cr_tries > 5) {
1255 signal_levels = intel_gen6_edp_signal_levels(train_set[0]); 1427 DRM_ERROR("failed to train DP, aborting\n");
1428 intel_dp_link_down(intel_dp);
1429 break;
1430 }
1431
1432 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1433 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1256 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1434 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1257 } else { 1435 } else {
1258 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); 1436 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1259 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1437 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1260 } 1438 }
1261 1439
1262 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1440 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1263 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1441 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1264 else 1442 else
1265 reg = DP | DP_LINK_TRAIN_PAT_2; 1443 reg = DP | DP_LINK_TRAIN_PAT_2;
1266 1444
1267 /* channel eq pattern */ 1445 /* channel eq pattern */
1268 if (!intel_dp_set_link_train(intel_dp, reg, 1446 if (!intel_dp_set_link_train(intel_dp, reg,
1269 DP_TRAINING_PATTERN_2, train_set)) 1447 DP_TRAINING_PATTERN_2))
1270 break; 1448 break;
1271 1449
1272 udelay(400); 1450 udelay(400);
1273 if (!intel_dp_get_link_status(intel_dp, link_status)) 1451 if (!intel_dp_get_link_status(intel_dp))
1274 break; 1452 break;
1275 1453
1276 if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) { 1454 /* Make sure clock is still ok */
1455 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1456 intel_dp_start_link_train(intel_dp);
1457 cr_tries++;
1458 continue;
1459 }
1460
1461 if (intel_channel_eq_ok(intel_dp)) {
1277 channel_eq = true; 1462 channel_eq = true;
1278 break; 1463 break;
1279 } 1464 }
1280 1465
1281 /* Try 5 times */ 1466 /* Try 5 times, then try clock recovery if that fails */
1282 if (tries > 5) 1467 if (tries > 5) {
1283 break; 1468 intel_dp_link_down(intel_dp);
1469 intel_dp_start_link_train(intel_dp);
1470 tries = 0;
1471 cr_tries++;
1472 continue;
1473 }
1284 1474
1285 /* Compute new train_set as requested by target */ 1475 /* Compute new intel_dp->train_set as requested by target */
1286 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); 1476 intel_get_adjust_train(intel_dp);
1287 ++tries; 1477 ++tries;
1288 } 1478 }
1289 1479
1290 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1480 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1291 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1481 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1292 else 1482 else
1293 reg = DP | DP_LINK_TRAIN_OFF; 1483 reg = DP | DP_LINK_TRAIN_OFF;
@@ -1301,33 +1491,69 @@ intel_dp_link_train(struct intel_dp *intel_dp)
1301static void 1491static void
1302intel_dp_link_down(struct intel_dp *intel_dp) 1492intel_dp_link_down(struct intel_dp *intel_dp)
1303{ 1493{
1304 struct drm_device *dev = intel_dp->base.enc.dev; 1494 struct drm_device *dev = intel_dp->base.base.dev;
1305 struct drm_i915_private *dev_priv = dev->dev_private; 1495 struct drm_i915_private *dev_priv = dev->dev_private;
1306 uint32_t DP = intel_dp->DP; 1496 uint32_t DP = intel_dp->DP;
1307 1497
1498 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1499 return;
1500
1308 DRM_DEBUG_KMS("\n"); 1501 DRM_DEBUG_KMS("\n");
1309 1502
1310 if (IS_eDP(intel_dp)) { 1503 if (is_edp(intel_dp)) {
1311 DP &= ~DP_PLL_ENABLE; 1504 DP &= ~DP_PLL_ENABLE;
1312 I915_WRITE(intel_dp->output_reg, DP); 1505 I915_WRITE(intel_dp->output_reg, DP);
1313 POSTING_READ(intel_dp->output_reg); 1506 POSTING_READ(intel_dp->output_reg);
1314 udelay(100); 1507 udelay(100);
1315 } 1508 }
1316 1509
1317 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) { 1510 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1318 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1511 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1319 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1512 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1320 POSTING_READ(intel_dp->output_reg);
1321 } else { 1513 } else {
1322 DP &= ~DP_LINK_TRAIN_MASK; 1514 DP &= ~DP_LINK_TRAIN_MASK;
1323 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1515 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1324 POSTING_READ(intel_dp->output_reg);
1325 } 1516 }
1517 POSTING_READ(intel_dp->output_reg);
1326 1518
1327 udelay(17000); 1519 msleep(17);
1328 1520
1329 if (IS_eDP(intel_dp)) 1521 if (is_edp(intel_dp))
1330 DP |= DP_LINK_TRAIN_OFF; 1522 DP |= DP_LINK_TRAIN_OFF;
1523
1524 if (!HAS_PCH_CPT(dev) &&
1525 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1526 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1527
1528 /* Hardware workaround: leaving our transcoder select
1529 * set to transcoder B while it's off will prevent the
1530 * corresponding HDMI output on transcoder A.
1531 *
1532 * Combine this with another hardware workaround:
1533 * transcoder select bit can only be cleared while the
1534 * port is enabled.
1535 */
1536 DP &= ~DP_PIPEB_SELECT;
1537 I915_WRITE(intel_dp->output_reg, DP);
1538
1539 /* Changes to enable or select take place the vblank
1540 * after being written.
1541 */
1542 if (crtc == NULL) {
1543 /* We can arrive here never having been attached
1544 * to a CRTC, for instance, due to inheriting
1545 * random state from the BIOS.
1546 *
1547 * If the pipe is not running, play safe and
1548 * wait for the clocks to stabilise before
1549 * continuing.
1550 */
1551 POSTING_READ(intel_dp->output_reg);
1552 msleep(50);
1553 } else
1554 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1555 }
1556
1331 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1557 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1332 POSTING_READ(intel_dp->output_reg); 1558 POSTING_READ(intel_dp->output_reg);
1333} 1559}
@@ -1344,60 +1570,63 @@ intel_dp_link_down(struct intel_dp *intel_dp)
1344static void 1570static void
1345intel_dp_check_link_status(struct intel_dp *intel_dp) 1571intel_dp_check_link_status(struct intel_dp *intel_dp)
1346{ 1572{
1347 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1573 int ret;
1574
1575 if (!intel_dp->base.base.crtc)
1576 return;
1348 1577
1349 if (!intel_dp->base.enc.crtc) 1578 if (!intel_dp_get_link_status(intel_dp)) {
1579 intel_dp_link_down(intel_dp);
1350 return; 1580 return;
1581 }
1351 1582
1352 if (!intel_dp_get_link_status(intel_dp, link_status)) { 1583 /* Try to read receiver status if the link appears to be up */
1584 ret = intel_dp_aux_native_read(intel_dp,
1585 0x000, intel_dp->dpcd,
1586 sizeof (intel_dp->dpcd));
1587 if (ret != sizeof(intel_dp->dpcd)) {
1353 intel_dp_link_down(intel_dp); 1588 intel_dp_link_down(intel_dp);
1354 return; 1589 return;
1355 } 1590 }
1356 1591
1357 if (!intel_channel_eq_ok(link_status, intel_dp->lane_count)) 1592 if (!intel_channel_eq_ok(intel_dp)) {
1358 intel_dp_link_train(intel_dp); 1593 intel_dp_start_link_train(intel_dp);
1594 intel_dp_complete_link_train(intel_dp);
1595 }
1359} 1596}
1360 1597
1361static enum drm_connector_status 1598static enum drm_connector_status
1362ironlake_dp_detect(struct drm_connector *connector) 1599ironlake_dp_detect(struct intel_dp *intel_dp)
1363{ 1600{
1364 struct drm_encoder *encoder = intel_attached_encoder(connector);
1365 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1366 enum drm_connector_status status; 1601 enum drm_connector_status status;
1602 bool ret;
1367 1603
1368 status = connector_status_disconnected; 1604 /* Can't disconnect eDP, but you can close the lid... */
1369 if (intel_dp_aux_native_read(intel_dp, 1605 if (is_edp(intel_dp)) {
1370 0x000, intel_dp->dpcd, 1606 status = intel_panel_detect(intel_dp->base.base.dev);
1371 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1607 if (status == connector_status_unknown)
1372 {
1373 if (intel_dp->dpcd[0] != 0)
1374 status = connector_status_connected; 1608 status = connector_status_connected;
1609 return status;
1375 } 1610 }
1611
1612 status = connector_status_disconnected;
1613 ret = intel_dp_aux_native_read_retry(intel_dp,
1614 0x000, intel_dp->dpcd,
1615 sizeof (intel_dp->dpcd));
1616 if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0)
1617 status = connector_status_connected;
1376 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], 1618 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1377 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); 1619 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1378 return status; 1620 return status;
1379} 1621}
1380 1622
1381/**
1382 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1383 *
1384 * \return true if DP port is connected.
1385 * \return false if DP port is disconnected.
1386 */
1387static enum drm_connector_status 1623static enum drm_connector_status
1388intel_dp_detect(struct drm_connector *connector, bool force) 1624g4x_dp_detect(struct intel_dp *intel_dp)
1389{ 1625{
1390 struct drm_encoder *encoder = intel_attached_encoder(connector); 1626 struct drm_device *dev = intel_dp->base.base.dev;
1391 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1392 struct drm_device *dev = intel_dp->base.enc.dev;
1393 struct drm_i915_private *dev_priv = dev->dev_private; 1627 struct drm_i915_private *dev_priv = dev->dev_private;
1394 uint32_t temp, bit;
1395 enum drm_connector_status status; 1628 enum drm_connector_status status;
1396 1629 uint32_t temp, bit;
1397 intel_dp->has_audio = false;
1398
1399 if (HAS_PCH_SPLIT(dev))
1400 return ironlake_dp_detect(connector);
1401 1630
1402 switch (intel_dp->output_reg) { 1631 switch (intel_dp->output_reg) {
1403 case DP_B: 1632 case DP_B:
@@ -1419,31 +1648,66 @@ intel_dp_detect(struct drm_connector *connector, bool force)
1419 return connector_status_disconnected; 1648 return connector_status_disconnected;
1420 1649
1421 status = connector_status_disconnected; 1650 status = connector_status_disconnected;
1422 if (intel_dp_aux_native_read(intel_dp, 1651 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1423 0x000, intel_dp->dpcd,
1424 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1652 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1425 { 1653 {
1426 if (intel_dp->dpcd[0] != 0) 1654 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1427 status = connector_status_connected; 1655 status = connector_status_connected;
1428 } 1656 }
1657
1429 return status; 1658 return status;
1430} 1659}
1431 1660
1661/**
1662 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1663 *
1664 * \return true if DP port is connected.
1665 * \return false if DP port is disconnected.
1666 */
1667static enum drm_connector_status
1668intel_dp_detect(struct drm_connector *connector, bool force)
1669{
1670 struct intel_dp *intel_dp = intel_attached_dp(connector);
1671 struct drm_device *dev = intel_dp->base.base.dev;
1672 enum drm_connector_status status;
1673 struct edid *edid = NULL;
1674
1675 intel_dp->has_audio = false;
1676
1677 if (HAS_PCH_SPLIT(dev))
1678 status = ironlake_dp_detect(intel_dp);
1679 else
1680 status = g4x_dp_detect(intel_dp);
1681 if (status != connector_status_connected)
1682 return status;
1683
1684 if (intel_dp->force_audio) {
1685 intel_dp->has_audio = intel_dp->force_audio > 0;
1686 } else {
1687 edid = drm_get_edid(connector, &intel_dp->adapter);
1688 if (edid) {
1689 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1690 connector->display_info.raw_edid = NULL;
1691 kfree(edid);
1692 }
1693 }
1694
1695 return connector_status_connected;
1696}
1697
1432static int intel_dp_get_modes(struct drm_connector *connector) 1698static int intel_dp_get_modes(struct drm_connector *connector)
1433{ 1699{
1434 struct drm_encoder *encoder = intel_attached_encoder(connector); 1700 struct intel_dp *intel_dp = intel_attached_dp(connector);
1435 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1701 struct drm_device *dev = intel_dp->base.base.dev;
1436 struct drm_device *dev = intel_dp->base.enc.dev;
1437 struct drm_i915_private *dev_priv = dev->dev_private; 1702 struct drm_i915_private *dev_priv = dev->dev_private;
1438 int ret; 1703 int ret;
1439 1704
1440 /* We should parse the EDID data and find out if it has an audio sink 1705 /* We should parse the EDID data and find out if it has an audio sink
1441 */ 1706 */
1442 1707
1443 ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus); 1708 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1444 if (ret) { 1709 if (ret) {
1445 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && 1710 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1446 !dev_priv->panel_fixed_mode) {
1447 struct drm_display_mode *newmode; 1711 struct drm_display_mode *newmode;
1448 list_for_each_entry(newmode, &connector->probed_modes, 1712 list_for_each_entry(newmode, &connector->probed_modes,
1449 head) { 1713 head) {
@@ -1459,7 +1723,7 @@ static int intel_dp_get_modes(struct drm_connector *connector)
1459 } 1723 }
1460 1724
1461 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1725 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1462 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { 1726 if (is_edp(intel_dp)) {
1463 if (dev_priv->panel_fixed_mode != NULL) { 1727 if (dev_priv->panel_fixed_mode != NULL) {
1464 struct drm_display_mode *mode; 1728 struct drm_display_mode *mode;
1465 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 1729 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
@@ -1470,6 +1734,79 @@ static int intel_dp_get_modes(struct drm_connector *connector)
1470 return 0; 1734 return 0;
1471} 1735}
1472 1736
1737static bool
1738intel_dp_detect_audio(struct drm_connector *connector)
1739{
1740 struct intel_dp *intel_dp = intel_attached_dp(connector);
1741 struct edid *edid;
1742 bool has_audio = false;
1743
1744 edid = drm_get_edid(connector, &intel_dp->adapter);
1745 if (edid) {
1746 has_audio = drm_detect_monitor_audio(edid);
1747
1748 connector->display_info.raw_edid = NULL;
1749 kfree(edid);
1750 }
1751
1752 return has_audio;
1753}
1754
1755static int
1756intel_dp_set_property(struct drm_connector *connector,
1757 struct drm_property *property,
1758 uint64_t val)
1759{
1760 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1761 struct intel_dp *intel_dp = intel_attached_dp(connector);
1762 int ret;
1763
1764 ret = drm_connector_property_set_value(connector, property, val);
1765 if (ret)
1766 return ret;
1767
1768 if (property == dev_priv->force_audio_property) {
1769 int i = val;
1770 bool has_audio;
1771
1772 if (i == intel_dp->force_audio)
1773 return 0;
1774
1775 intel_dp->force_audio = i;
1776
1777 if (i == 0)
1778 has_audio = intel_dp_detect_audio(connector);
1779 else
1780 has_audio = i > 0;
1781
1782 if (has_audio == intel_dp->has_audio)
1783 return 0;
1784
1785 intel_dp->has_audio = has_audio;
1786 goto done;
1787 }
1788
1789 if (property == dev_priv->broadcast_rgb_property) {
1790 if (val == !!intel_dp->color_range)
1791 return 0;
1792
1793 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1794 goto done;
1795 }
1796
1797 return -EINVAL;
1798
1799done:
1800 if (intel_dp->base.base.crtc) {
1801 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1802 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1803 crtc->x, crtc->y,
1804 crtc->fb);
1805 }
1806
1807 return 0;
1808}
1809
1473static void 1810static void
1474intel_dp_destroy (struct drm_connector *connector) 1811intel_dp_destroy (struct drm_connector *connector)
1475{ 1812{
@@ -1478,6 +1815,15 @@ intel_dp_destroy (struct drm_connector *connector)
1478 kfree(connector); 1815 kfree(connector);
1479} 1816}
1480 1817
1818static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1819{
1820 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1821
1822 i2c_del_adapter(&intel_dp->adapter);
1823 drm_encoder_cleanup(encoder);
1824 kfree(intel_dp);
1825}
1826
1481static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1827static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1482 .dpms = intel_dp_dpms, 1828 .dpms = intel_dp_dpms,
1483 .mode_fixup = intel_dp_mode_fixup, 1829 .mode_fixup = intel_dp_mode_fixup,
@@ -1490,26 +1836,26 @@ static const struct drm_connector_funcs intel_dp_connector_funcs = {
1490 .dpms = drm_helper_connector_dpms, 1836 .dpms = drm_helper_connector_dpms,
1491 .detect = intel_dp_detect, 1837 .detect = intel_dp_detect,
1492 .fill_modes = drm_helper_probe_single_connector_modes, 1838 .fill_modes = drm_helper_probe_single_connector_modes,
1839 .set_property = intel_dp_set_property,
1493 .destroy = intel_dp_destroy, 1840 .destroy = intel_dp_destroy,
1494}; 1841};
1495 1842
1496static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 1843static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1497 .get_modes = intel_dp_get_modes, 1844 .get_modes = intel_dp_get_modes,
1498 .mode_valid = intel_dp_mode_valid, 1845 .mode_valid = intel_dp_mode_valid,
1499 .best_encoder = intel_attached_encoder, 1846 .best_encoder = intel_best_encoder,
1500}; 1847};
1501 1848
1502static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1849static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1503 .destroy = intel_encoder_destroy, 1850 .destroy = intel_dp_encoder_destroy,
1504}; 1851};
1505 1852
1506void 1853static void
1507intel_dp_hot_plug(struct intel_encoder *intel_encoder) 1854intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1508{ 1855{
1509 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 1856 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1510 1857
1511 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) 1858 intel_dp_check_link_status(intel_dp);
1512 intel_dp_check_link_status(intel_dp);
1513} 1859}
1514 1860
1515/* Return which DP Port should be selected for Transcoder DP control */ 1861/* Return which DP Port should be selected for Transcoder DP control */
@@ -1554,6 +1900,13 @@ bool intel_dpd_is_edp(struct drm_device *dev)
1554 return false; 1900 return false;
1555} 1901}
1556 1902
1903static void
1904intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1905{
1906 intel_attach_force_audio_property(connector);
1907 intel_attach_broadcast_rgb_property(connector);
1908}
1909
1557void 1910void
1558intel_dp_init(struct drm_device *dev, int output_reg) 1911intel_dp_init(struct drm_device *dev, int output_reg)
1559{ 1912{
@@ -1569,6 +1922,8 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1569 if (!intel_dp) 1922 if (!intel_dp)
1570 return; 1923 return;
1571 1924
1925 intel_dp->output_reg = output_reg;
1926
1572 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1927 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1573 if (!intel_connector) { 1928 if (!intel_connector) {
1574 kfree(intel_dp); 1929 kfree(intel_dp);
@@ -1580,7 +1935,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1580 if (intel_dpd_is_edp(dev)) 1935 if (intel_dpd_is_edp(dev))
1581 intel_dp->is_pch_edp = true; 1936 intel_dp->is_pch_edp = true;
1582 1937
1583 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { 1938 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1584 type = DRM_MODE_CONNECTOR_eDP; 1939 type = DRM_MODE_CONNECTOR_eDP;
1585 intel_encoder->type = INTEL_OUTPUT_EDP; 1940 intel_encoder->type = INTEL_OUTPUT_EDP;
1586 } else { 1941 } else {
@@ -1601,23 +1956,18 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1601 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1956 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1602 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1957 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1603 1958
1604 if (IS_eDP(intel_dp)) 1959 if (is_edp(intel_dp))
1605 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1960 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1606 1961
1607 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1962 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1608 connector->interlace_allowed = true; 1963 connector->interlace_allowed = true;
1609 connector->doublescan_allowed = 0; 1964 connector->doublescan_allowed = 0;
1610 1965
1611 intel_dp->output_reg = output_reg; 1966 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1612 intel_dp->has_audio = false;
1613 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1614
1615 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1616 DRM_MODE_ENCODER_TMDS); 1967 DRM_MODE_ENCODER_TMDS);
1617 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs); 1968 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1618 1969
1619 drm_mode_connector_attach_encoder(&intel_connector->base, 1970 intel_connector_attach_encoder(intel_connector, intel_encoder);
1620 &intel_encoder->enc);
1621 drm_sysfs_connector_add(connector); 1971 drm_sysfs_connector_add(connector);
1622 1972
1623 /* Set up the DDC bus. */ 1973 /* Set up the DDC bus. */
@@ -1647,10 +1997,42 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1647 1997
1648 intel_dp_i2c_init(intel_dp, intel_connector, name); 1998 intel_dp_i2c_init(intel_dp, intel_connector, name);
1649 1999
1650 intel_encoder->ddc_bus = &intel_dp->adapter; 2000 /* Cache some DPCD data in the eDP case */
2001 if (is_edp(intel_dp)) {
2002 int ret;
2003 u32 pp_on, pp_div;
2004
2005 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2006 pp_div = I915_READ(PCH_PP_DIVISOR);
2007
2008 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2009 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
2010 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
2011 dev_priv->panel_t12 = pp_div & 0xf;
2012 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2013
2014 ironlake_edp_panel_vdd_on(intel_dp);
2015 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
2016 intel_dp->dpcd,
2017 sizeof(intel_dp->dpcd));
2018 ironlake_edp_panel_vdd_off(intel_dp);
2019 if (ret == sizeof(intel_dp->dpcd)) {
2020 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2021 dev_priv->no_aux_handshake =
2022 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2023 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2024 } else {
2025 /* if this fails, presume the device is a ghost */
2026 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2027 intel_dp_encoder_destroy(&intel_dp->base.base);
2028 intel_dp_destroy(&intel_connector->base);
2029 return;
2030 }
2031 }
2032
1651 intel_encoder->hot_plug = intel_dp_hot_plug; 2033 intel_encoder->hot_plug = intel_dp_hot_plug;
1652 2034
1653 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { 2035 if (is_edp(intel_dp)) {
1654 /* initialize panel mode from VBT if available for eDP */ 2036 /* initialize panel mode from VBT if available for eDP */
1655 if (dev_priv->lfp_lvds_vbt_mode) { 2037 if (dev_priv->lfp_lvds_vbt_mode) {
1656 dev_priv->panel_fixed_mode = 2038 dev_priv->panel_fixed_mode =
@@ -1662,6 +2044,8 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1662 } 2044 }
1663 } 2045 }
1664 2046
2047 intel_dp_add_properties(intel_dp, connector);
2048
1665 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2049 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1666 * 0xd. Failure to do so will result in spurious interrupts being 2050 * 0xd. Failure to do so will result in spurious interrupts being
1667 * generated on the port when a cable is not attached. 2051 * generated on the port when a cable is not attached.
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 18:15:58 -0400