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path: root/drivers/gpu/drm/i915/intel_dp.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c60
1 files changed, 46 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9ab8708ac6ba..0aa77f318790 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -425,6 +425,7 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
425 uint16_t address = algo_data->address; 425 uint16_t address = algo_data->address;
426 uint8_t msg[5]; 426 uint8_t msg[5];
427 uint8_t reply[2]; 427 uint8_t reply[2];
428 unsigned retry;
428 int msg_bytes; 429 int msg_bytes;
429 int reply_bytes; 430 int reply_bytes;
430 int ret; 431 int ret;
@@ -459,14 +460,33 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
459 break; 460 break;
460 } 461 }
461 462
462 for (;;) { 463 for (retry = 0; retry < 5; retry++) {
463 ret = intel_dp_aux_ch(intel_dp, 464 ret = intel_dp_aux_ch(intel_dp,
464 msg, msg_bytes, 465 msg, msg_bytes,
465 reply, reply_bytes); 466 reply, reply_bytes);
466 if (ret < 0) { 467 if (ret < 0) {
467 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 468 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
468 return ret; 469 return ret;
469 } 470 }
471
472 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
473 case AUX_NATIVE_REPLY_ACK:
474 /* I2C-over-AUX Reply field is only valid
475 * when paired with AUX ACK.
476 */
477 break;
478 case AUX_NATIVE_REPLY_NACK:
479 DRM_DEBUG_KMS("aux_ch native nack\n");
480 return -EREMOTEIO;
481 case AUX_NATIVE_REPLY_DEFER:
482 udelay(100);
483 continue;
484 default:
485 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
486 reply[0]);
487 return -EREMOTEIO;
488 }
489
470 switch (reply[0] & AUX_I2C_REPLY_MASK) { 490 switch (reply[0] & AUX_I2C_REPLY_MASK) {
471 case AUX_I2C_REPLY_ACK: 491 case AUX_I2C_REPLY_ACK:
472 if (mode == MODE_I2C_READ) { 492 if (mode == MODE_I2C_READ) {
@@ -474,17 +494,20 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
474 } 494 }
475 return reply_bytes - 1; 495 return reply_bytes - 1;
476 case AUX_I2C_REPLY_NACK: 496 case AUX_I2C_REPLY_NACK:
477 DRM_DEBUG_KMS("aux_ch nack\n"); 497 DRM_DEBUG_KMS("aux_i2c nack\n");
478 return -EREMOTEIO; 498 return -EREMOTEIO;
479 case AUX_I2C_REPLY_DEFER: 499 case AUX_I2C_REPLY_DEFER:
480 DRM_DEBUG_KMS("aux_ch defer\n"); 500 DRM_DEBUG_KMS("aux_i2c defer\n");
481 udelay(100); 501 udelay(100);
482 break; 502 break;
483 default: 503 default:
484 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]); 504 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
485 return -EREMOTEIO; 505 return -EREMOTEIO;
486 } 506 }
487 } 507 }
508
509 DRM_ERROR("too many retries, giving up\n");
510 return -EREMOTEIO;
488} 511}
489 512
490static int 513static int
@@ -1070,18 +1093,27 @@ intel_dp_signal_levels(uint8_t train_set, int lane_count)
1070static uint32_t 1093static uint32_t
1071intel_gen6_edp_signal_levels(uint8_t train_set) 1094intel_gen6_edp_signal_levels(uint8_t train_set)
1072{ 1095{
1073 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) { 1096 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1097 DP_TRAIN_PRE_EMPHASIS_MASK);
1098 switch (signal_levels) {
1074 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1099 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1075 return EDP_LINK_TRAIN_400MV_0DB_SNB_B; 1100 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1101 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1102 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1103 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1076 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1104 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1077 return EDP_LINK_TRAIN_400MV_6DB_SNB_B; 1105 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1106 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1078 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1107 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1079 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B; 1108 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1109 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1080 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1110 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1081 return EDP_LINK_TRAIN_800MV_0DB_SNB_B; 1111 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1112 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1082 default: 1113 default:
1083 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n"); 1114 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1084 return EDP_LINK_TRAIN_400MV_0DB_SNB_B; 1115 "0x%x\n", signal_levels);
1116 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1085 } 1117 }
1086} 1118}
1087 1119