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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c784
1 files changed, 593 insertions, 191 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 91b35fd1db8c..37514a52b05c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -24,6 +24,7 @@
24 * Eric Anholt <eric@anholt.net> 24 * Eric Anholt <eric@anholt.net>
25 */ 25 */
26 26
27#include <linux/dmi.h>
27#include <linux/cpufreq.h> 28#include <linux/cpufreq.h>
28#include <linux/module.h> 29#include <linux/module.h>
29#include <linux/input.h> 30#include <linux/input.h>
@@ -360,6 +361,110 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
360 .find_pll = intel_find_pll_ironlake_dp, 361 .find_pll = intel_find_pll_ironlake_dp,
361}; 362};
362 363
364u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
365{
366 unsigned long flags;
367 u32 val = 0;
368
369 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
370 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
371 DRM_ERROR("DPIO idle wait timed out\n");
372 goto out_unlock;
373 }
374
375 I915_WRITE(DPIO_REG, reg);
376 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
377 DPIO_BYTE);
378 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
379 DRM_ERROR("DPIO read wait timed out\n");
380 goto out_unlock;
381 }
382 val = I915_READ(DPIO_DATA);
383
384out_unlock:
385 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
386 return val;
387}
388
389static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
390 u32 val)
391{
392 unsigned long flags;
393
394 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
395 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
396 DRM_ERROR("DPIO idle wait timed out\n");
397 goto out_unlock;
398 }
399
400 I915_WRITE(DPIO_DATA, val);
401 I915_WRITE(DPIO_REG, reg);
402 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
403 DPIO_BYTE);
404 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
405 DRM_ERROR("DPIO write wait timed out\n");
406
407out_unlock:
408 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
409}
410
411static void vlv_init_dpio(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 /* Reset the DPIO config */
416 I915_WRITE(DPIO_CTL, 0);
417 POSTING_READ(DPIO_CTL);
418 I915_WRITE(DPIO_CTL, 1);
419 POSTING_READ(DPIO_CTL);
420}
421
422static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
423{
424 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
425 return 1;
426}
427
428static const struct dmi_system_id intel_dual_link_lvds[] = {
429 {
430 .callback = intel_dual_link_lvds_callback,
431 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
432 .matches = {
433 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
434 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
435 },
436 },
437 { } /* terminating entry */
438};
439
440static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
441 unsigned int reg)
442{
443 unsigned int val;
444
445 /* use the module option value if specified */
446 if (i915_lvds_channel_mode > 0)
447 return i915_lvds_channel_mode == 2;
448
449 if (dmi_check_system(intel_dual_link_lvds))
450 return true;
451
452 if (dev_priv->lvds_val)
453 val = dev_priv->lvds_val;
454 else {
455 /* BIOS should set the proper LVDS register value at boot, but
456 * in reality, it doesn't set the value when the lid is closed;
457 * we need to check "the value to be set" in VBT when LVDS
458 * register is uninitialized.
459 */
460 val = I915_READ(reg);
461 if (!(val & ~LVDS_DETECTED))
462 val = dev_priv->bios_lvds_val;
463 dev_priv->lvds_val = val;
464 }
465 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
466}
467
363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, 468static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk) 469 int refclk)
365{ 470{
@@ -368,8 +473,7 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
368 const intel_limit_t *limit; 473 const intel_limit_t *limit;
369 474
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 475 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == 476 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */ 477 /* LVDS dual channel */
374 if (refclk == 100000) 478 if (refclk == 100000)
375 limit = &intel_limits_ironlake_dual_lvds_100m; 479 limit = &intel_limits_ironlake_dual_lvds_100m;
@@ -397,8 +501,7 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
397 const intel_limit_t *limit; 501 const intel_limit_t *limit;
398 502
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 503 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 504 if (is_dual_link_lvds(dev_priv, LVDS))
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */ 505 /* LVDS with dual channel */
403 limit = &intel_limits_g4x_dual_channel_lvds; 506 limit = &intel_limits_g4x_dual_channel_lvds;
404 else 507 else
@@ -536,8 +639,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
536 * reliably set up different single/dual channel state, if we 639 * reliably set up different single/dual channel state, if we
537 * even can. 640 * even can.
538 */ 641 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 642 if (is_dual_link_lvds(dev_priv, LVDS))
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast; 643 clock.p2 = limit->p2.p2_fast;
542 else 644 else
543 clock.p2 = limit->p2.p2_slow; 645 clock.p2 = limit->p2.p2_slow;
@@ -2537,7 +2639,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
2537 struct drm_i915_private *dev_priv = dev->dev_private; 2639 struct drm_i915_private *dev_priv = dev->dev_private;
2538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2539 int pipe = intel_crtc->pipe; 2641 int pipe = intel_crtc->pipe;
2540 u32 reg, temp, i; 2642 u32 reg, temp, i, retry;
2541 2643
2542 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2644 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2543 for train result */ 2645 for train result */
@@ -2589,15 +2691,19 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
2589 POSTING_READ(reg); 2691 POSTING_READ(reg);
2590 udelay(500); 2692 udelay(500);
2591 2693
2592 reg = FDI_RX_IIR(pipe); 2694 for (retry = 0; retry < 5; retry++) {
2593 temp = I915_READ(reg); 2695 reg = FDI_RX_IIR(pipe);
2594 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2696 temp = I915_READ(reg);
2595 2697 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2596 if (temp & FDI_RX_BIT_LOCK) { 2698 if (temp & FDI_RX_BIT_LOCK) {
2597 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2699 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2598 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2700 DRM_DEBUG_KMS("FDI train 1 done.\n");
2599 break; 2701 break;
2702 }
2703 udelay(50);
2600 } 2704 }
2705 if (retry < 5)
2706 break;
2601 } 2707 }
2602 if (i == 4) 2708 if (i == 4)
2603 DRM_ERROR("FDI train 1 fail!\n"); 2709 DRM_ERROR("FDI train 1 fail!\n");
@@ -2638,15 +2744,19 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
2638 POSTING_READ(reg); 2744 POSTING_READ(reg);
2639 udelay(500); 2745 udelay(500);
2640 2746
2641 reg = FDI_RX_IIR(pipe); 2747 for (retry = 0; retry < 5; retry++) {
2642 temp = I915_READ(reg); 2748 reg = FDI_RX_IIR(pipe);
2643 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2749 temp = I915_READ(reg);
2644 2750 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2645 if (temp & FDI_RX_SYMBOL_LOCK) { 2751 if (temp & FDI_RX_SYMBOL_LOCK) {
2646 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2752 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2647 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2753 DRM_DEBUG_KMS("FDI train 2 done.\n");
2648 break; 2754 break;
2755 }
2756 udelay(50);
2649 } 2757 }
2758 if (retry < 5)
2759 break;
2650 } 2760 }
2651 if (i == 4) 2761 if (i == 4)
2652 DRM_ERROR("FDI train 2 fail!\n"); 2762 DRM_ERROR("FDI train 2 fail!\n");
@@ -3457,6 +3567,11 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3457 return true; 3567 return true;
3458} 3568}
3459 3569
3570static int valleyview_get_display_clock_speed(struct drm_device *dev)
3571{
3572 return 400000; /* FIXME */
3573}
3574
3460static int i945_get_display_clock_speed(struct drm_device *dev) 3575static int i945_get_display_clock_speed(struct drm_device *dev)
3461{ 3576{
3462 return 400000; 3577 return 400000;
@@ -3606,6 +3721,20 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
3606 2, 3721 2,
3607 G4X_FIFO_LINE_SIZE, 3722 G4X_FIFO_LINE_SIZE,
3608}; 3723};
3724static const struct intel_watermark_params valleyview_wm_info = {
3725 VALLEYVIEW_FIFO_SIZE,
3726 VALLEYVIEW_MAX_WM,
3727 VALLEYVIEW_MAX_WM,
3728 2,
3729 G4X_FIFO_LINE_SIZE,
3730};
3731static const struct intel_watermark_params valleyview_cursor_wm_info = {
3732 I965_CURSOR_FIFO,
3733 VALLEYVIEW_CURSOR_MAX_WM,
3734 I965_CURSOR_DFT_WM,
3735 2,
3736 G4X_FIFO_LINE_SIZE,
3737};
3609static const struct intel_watermark_params i965_cursor_wm_info = { 3738static const struct intel_watermark_params i965_cursor_wm_info = {
3610 I965_CURSOR_FIFO, 3739 I965_CURSOR_FIFO,
3611 I965_CURSOR_MAX_WM, 3740 I965_CURSOR_MAX_WM,
@@ -4128,8 +4257,134 @@ static bool g4x_compute_srwm(struct drm_device *dev,
4128 display, cursor); 4257 display, cursor);
4129} 4258}
4130 4259
4260static bool vlv_compute_drain_latency(struct drm_device *dev,
4261 int plane,
4262 int *plane_prec_mult,
4263 int *plane_dl,
4264 int *cursor_prec_mult,
4265 int *cursor_dl)
4266{
4267 struct drm_crtc *crtc;
4268 int clock, pixel_size;
4269 int entries;
4270
4271 crtc = intel_get_crtc_for_plane(dev, plane);
4272 if (crtc->fb == NULL || !crtc->enabled)
4273 return false;
4274
4275 clock = crtc->mode.clock; /* VESA DOT Clock */
4276 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
4277
4278 entries = (clock / 1000) * pixel_size;
4279 *plane_prec_mult = (entries > 256) ?
4280 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
4281 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
4282 pixel_size);
4283
4284 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
4285 *cursor_prec_mult = (entries > 256) ?
4286 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
4287 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
4288
4289 return true;
4290}
4291
4292/*
4293 * Update drain latency registers of memory arbiter
4294 *
4295 * Valleyview SoC has a new memory arbiter and needs drain latency registers
4296 * to be programmed. Each plane has a drain latency multiplier and a drain
4297 * latency value.
4298 */
4299
4300static void vlv_update_drain_latency(struct drm_device *dev)
4301{
4302 struct drm_i915_private *dev_priv = dev->dev_private;
4303 int planea_prec, planea_dl, planeb_prec, planeb_dl;
4304 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
4305 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
4306 either 16 or 32 */
4307
4308 /* For plane A, Cursor A */
4309 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
4310 &cursor_prec_mult, &cursora_dl)) {
4311 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4312 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
4313 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4314 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
4315
4316 I915_WRITE(VLV_DDL1, cursora_prec |
4317 (cursora_dl << DDL_CURSORA_SHIFT) |
4318 planea_prec | planea_dl);
4319 }
4320
4321 /* For plane B, Cursor B */
4322 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
4323 &cursor_prec_mult, &cursorb_dl)) {
4324 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4325 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
4326 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4327 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
4328
4329 I915_WRITE(VLV_DDL2, cursorb_prec |
4330 (cursorb_dl << DDL_CURSORB_SHIFT) |
4331 planeb_prec | planeb_dl);
4332 }
4333}
4334
4131#define single_plane_enabled(mask) is_power_of_2(mask) 4335#define single_plane_enabled(mask) is_power_of_2(mask)
4132 4336
4337static void valleyview_update_wm(struct drm_device *dev)
4338{
4339 static const int sr_latency_ns = 12000;
4340 struct drm_i915_private *dev_priv = dev->dev_private;
4341 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4342 int plane_sr, cursor_sr;
4343 unsigned int enabled = 0;
4344
4345 vlv_update_drain_latency(dev);
4346
4347 if (g4x_compute_wm0(dev, 0,
4348 &valleyview_wm_info, latency_ns,
4349 &valleyview_cursor_wm_info, latency_ns,
4350 &planea_wm, &cursora_wm))
4351 enabled |= 1;
4352
4353 if (g4x_compute_wm0(dev, 1,
4354 &valleyview_wm_info, latency_ns,
4355 &valleyview_cursor_wm_info, latency_ns,
4356 &planeb_wm, &cursorb_wm))
4357 enabled |= 2;
4358
4359 plane_sr = cursor_sr = 0;
4360 if (single_plane_enabled(enabled) &&
4361 g4x_compute_srwm(dev, ffs(enabled) - 1,
4362 sr_latency_ns,
4363 &valleyview_wm_info,
4364 &valleyview_cursor_wm_info,
4365 &plane_sr, &cursor_sr))
4366 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
4367 else
4368 I915_WRITE(FW_BLC_SELF_VLV,
4369 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
4370
4371 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4372 planea_wm, cursora_wm,
4373 planeb_wm, cursorb_wm,
4374 plane_sr, cursor_sr);
4375
4376 I915_WRITE(DSPFW1,
4377 (plane_sr << DSPFW_SR_SHIFT) |
4378 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4379 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4380 planea_wm);
4381 I915_WRITE(DSPFW2,
4382 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4383 (cursora_wm << DSPFW_CURSORA_SHIFT));
4384 I915_WRITE(DSPFW3,
4385 (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
4386}
4387
4133static void g4x_update_wm(struct drm_device *dev) 4388static void g4x_update_wm(struct drm_device *dev)
4134{ 4389{
4135 static const int sr_latency_ns = 12000; 4390 static const int sr_latency_ns = 12000;
@@ -5113,6 +5368,233 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5113 } 5368 }
5114} 5369}
5115 5370
5371static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
5372 struct drm_display_mode *adjusted_mode)
5373{
5374 struct drm_device *dev = crtc->dev;
5375 struct drm_i915_private *dev_priv = dev->dev_private;
5376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5377 int pipe = intel_crtc->pipe;
5378 u32 temp, lvds_sync = 0;
5379
5380 temp = I915_READ(LVDS);
5381 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5382 if (pipe == 1) {
5383 temp |= LVDS_PIPEB_SELECT;
5384 } else {
5385 temp &= ~LVDS_PIPEB_SELECT;
5386 }
5387 /* set the corresponsding LVDS_BORDER bit */
5388 temp |= dev_priv->lvds_border_bits;
5389 /* Set the B0-B3 data pairs corresponding to whether we're going to
5390 * set the DPLLs for dual-channel mode or not.
5391 */
5392 if (clock->p2 == 7)
5393 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5394 else
5395 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5396
5397 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5398 * appropriately here, but we need to look more thoroughly into how
5399 * panels behave in the two modes.
5400 */
5401 /* set the dithering flag on LVDS as needed */
5402 if (INTEL_INFO(dev)->gen >= 4) {
5403 if (dev_priv->lvds_dither)
5404 temp |= LVDS_ENABLE_DITHER;
5405 else
5406 temp &= ~LVDS_ENABLE_DITHER;
5407 }
5408 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5409 lvds_sync |= LVDS_HSYNC_POLARITY;
5410 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5411 lvds_sync |= LVDS_VSYNC_POLARITY;
5412 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5413 != lvds_sync) {
5414 char flags[2] = "-+";
5415 DRM_INFO("Changing LVDS panel from "
5416 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5417 flags[!(temp & LVDS_HSYNC_POLARITY)],
5418 flags[!(temp & LVDS_VSYNC_POLARITY)],
5419 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5420 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5421 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5422 temp |= lvds_sync;
5423 }
5424 I915_WRITE(LVDS, temp);
5425}
5426
5427static void i9xx_update_pll(struct drm_crtc *crtc,
5428 struct drm_display_mode *mode,
5429 struct drm_display_mode *adjusted_mode,
5430 intel_clock_t *clock, intel_clock_t *reduced_clock,
5431 int num_connectors)
5432{
5433 struct drm_device *dev = crtc->dev;
5434 struct drm_i915_private *dev_priv = dev->dev_private;
5435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5436 int pipe = intel_crtc->pipe;
5437 u32 dpll;
5438 bool is_sdvo;
5439
5440 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5441 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5442
5443 dpll = DPLL_VGA_MODE_DIS;
5444
5445 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5446 dpll |= DPLLB_MODE_LVDS;
5447 else
5448 dpll |= DPLLB_MODE_DAC_SERIAL;
5449 if (is_sdvo) {
5450 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5451 if (pixel_multiplier > 1) {
5452 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5453 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5454 }
5455 dpll |= DPLL_DVO_HIGH_SPEED;
5456 }
5457 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5458 dpll |= DPLL_DVO_HIGH_SPEED;
5459
5460 /* compute bitmask from p1 value */
5461 if (IS_PINEVIEW(dev))
5462 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5463 else {
5464 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5465 if (IS_G4X(dev) && reduced_clock)
5466 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5467 }
5468 switch (clock->p2) {
5469 case 5:
5470 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5471 break;
5472 case 7:
5473 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5474 break;
5475 case 10:
5476 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5477 break;
5478 case 14:
5479 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5480 break;
5481 }
5482 if (INTEL_INFO(dev)->gen >= 4)
5483 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5484
5485 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5486 dpll |= PLL_REF_INPUT_TVCLKINBC;
5487 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5488 /* XXX: just matching BIOS for now */
5489 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5490 dpll |= 3;
5491 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5492 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5493 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5494 else
5495 dpll |= PLL_REF_INPUT_DREFCLK;
5496
5497 dpll |= DPLL_VCO_ENABLE;
5498 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5499 POSTING_READ(DPLL(pipe));
5500 udelay(150);
5501
5502 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5503 * This is an exception to the general rule that mode_set doesn't turn
5504 * things on.
5505 */
5506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5507 intel_update_lvds(crtc, clock, adjusted_mode);
5508
5509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5510 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5511
5512 I915_WRITE(DPLL(pipe), dpll);
5513
5514 /* Wait for the clocks to stabilize. */
5515 POSTING_READ(DPLL(pipe));
5516 udelay(150);
5517
5518 if (INTEL_INFO(dev)->gen >= 4) {
5519 u32 temp = 0;
5520 if (is_sdvo) {
5521 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5522 if (temp > 1)
5523 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5524 else
5525 temp = 0;
5526 }
5527 I915_WRITE(DPLL_MD(pipe), temp);
5528 } else {
5529 /* The pixel multiplier can only be updated once the
5530 * DPLL is enabled and the clocks are stable.
5531 *
5532 * So write it again.
5533 */
5534 I915_WRITE(DPLL(pipe), dpll);
5535 }
5536}
5537
5538static void i8xx_update_pll(struct drm_crtc *crtc,
5539 struct drm_display_mode *adjusted_mode,
5540 intel_clock_t *clock,
5541 int num_connectors)
5542{
5543 struct drm_device *dev = crtc->dev;
5544 struct drm_i915_private *dev_priv = dev->dev_private;
5545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5546 int pipe = intel_crtc->pipe;
5547 u32 dpll;
5548
5549 dpll = DPLL_VGA_MODE_DIS;
5550
5551 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
5552 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5553 } else {
5554 if (clock->p1 == 2)
5555 dpll |= PLL_P1_DIVIDE_BY_TWO;
5556 else
5557 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5558 if (clock->p2 == 4)
5559 dpll |= PLL_P2_DIVIDE_BY_4;
5560 }
5561
5562 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5563 /* XXX: just matching BIOS for now */
5564 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5565 dpll |= 3;
5566 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5567 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5568 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5569 else
5570 dpll |= PLL_REF_INPUT_DREFCLK;
5571
5572 dpll |= DPLL_VCO_ENABLE;
5573 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5574 POSTING_READ(DPLL(pipe));
5575 udelay(150);
5576
5577 I915_WRITE(DPLL(pipe), dpll);
5578
5579 /* Wait for the clocks to stabilize. */
5580 POSTING_READ(DPLL(pipe));
5581 udelay(150);
5582
5583 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5584 * This is an exception to the general rule that mode_set doesn't turn
5585 * things on.
5586 */
5587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5588 intel_update_lvds(crtc, clock, adjusted_mode);
5589
5590 /* The pixel multiplier can only be updated once the
5591 * DPLL is enabled and the clocks are stable.
5592 *
5593 * So write it again.
5594 */
5595 I915_WRITE(DPLL(pipe), dpll);
5596}
5597
5116static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 5598static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5117 struct drm_display_mode *mode, 5599 struct drm_display_mode *mode,
5118 struct drm_display_mode *adjusted_mode, 5600 struct drm_display_mode *adjusted_mode,
@@ -5126,15 +5608,13 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5126 int plane = intel_crtc->plane; 5608 int plane = intel_crtc->plane;
5127 int refclk, num_connectors = 0; 5609 int refclk, num_connectors = 0;
5128 intel_clock_t clock, reduced_clock; 5610 intel_clock_t clock, reduced_clock;
5129 u32 dpll, dspcntr, pipeconf, vsyncshift; 5611 u32 dspcntr, pipeconf, vsyncshift;
5130 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 5612 bool ok, has_reduced_clock = false, is_sdvo = false;
5131 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 5613 bool is_lvds = false, is_tv = false, is_dp = false;
5132 struct drm_mode_config *mode_config = &dev->mode_config; 5614 struct drm_mode_config *mode_config = &dev->mode_config;
5133 struct intel_encoder *encoder; 5615 struct intel_encoder *encoder;
5134 const intel_limit_t *limit; 5616 const intel_limit_t *limit;
5135 int ret; 5617 int ret;
5136 u32 temp;
5137 u32 lvds_sync = 0;
5138 5618
5139 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 5619 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5140 if (encoder->base.crtc != crtc) 5620 if (encoder->base.crtc != crtc)
@@ -5150,15 +5630,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5150 if (encoder->needs_tv_clock) 5630 if (encoder->needs_tv_clock)
5151 is_tv = true; 5631 is_tv = true;
5152 break; 5632 break;
5153 case INTEL_OUTPUT_DVO:
5154 is_dvo = true;
5155 break;
5156 case INTEL_OUTPUT_TVOUT: 5633 case INTEL_OUTPUT_TVOUT:
5157 is_tv = true; 5634 is_tv = true;
5158 break; 5635 break;
5159 case INTEL_OUTPUT_ANALOG:
5160 is_crt = true;
5161 break;
5162 case INTEL_OUTPUT_DISPLAYPORT: 5636 case INTEL_OUTPUT_DISPLAYPORT:
5163 is_dp = true; 5637 is_dp = true;
5164 break; 5638 break;
@@ -5205,71 +5679,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5205 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? 5679 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5206 &reduced_clock : NULL); 5680 &reduced_clock : NULL);
5207 5681
5208 dpll = DPLL_VGA_MODE_DIS; 5682 if (IS_GEN2(dev))
5209 5683 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
5210 if (!IS_GEN2(dev)) {
5211 if (is_lvds)
5212 dpll |= DPLLB_MODE_LVDS;
5213 else
5214 dpll |= DPLLB_MODE_DAC_SERIAL;
5215 if (is_sdvo) {
5216 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5217 if (pixel_multiplier > 1) {
5218 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5219 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5220 }
5221 dpll |= DPLL_DVO_HIGH_SPEED;
5222 }
5223 if (is_dp)
5224 dpll |= DPLL_DVO_HIGH_SPEED;
5225
5226 /* compute bitmask from p1 value */
5227 if (IS_PINEVIEW(dev))
5228 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5229 else {
5230 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5231 if (IS_G4X(dev) && has_reduced_clock)
5232 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5233 }
5234 switch (clock.p2) {
5235 case 5:
5236 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5237 break;
5238 case 7:
5239 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5240 break;
5241 case 10:
5242 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5243 break;
5244 case 14:
5245 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5246 break;
5247 }
5248 if (INTEL_INFO(dev)->gen >= 4)
5249 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5250 } else {
5251 if (is_lvds) {
5252 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5253 } else {
5254 if (clock.p1 == 2)
5255 dpll |= PLL_P1_DIVIDE_BY_TWO;
5256 else
5257 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5258 if (clock.p2 == 4)
5259 dpll |= PLL_P2_DIVIDE_BY_4;
5260 }
5261 }
5262
5263 if (is_sdvo && is_tv)
5264 dpll |= PLL_REF_INPUT_TVCLKINBC;
5265 else if (is_tv)
5266 /* XXX: just matching BIOS for now */
5267 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5268 dpll |= 3;
5269 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5270 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5271 else 5684 else
5272 dpll |= PLL_REF_INPUT_DREFCLK; 5685 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
5686 has_reduced_clock ? &reduced_clock : NULL,
5687 num_connectors);
5273 5688
5274 /* setup pipeconf */ 5689 /* setup pipeconf */
5275 pipeconf = I915_READ(PIPECONF(pipe)); 5690 pipeconf = I915_READ(PIPECONF(pipe));
@@ -5306,97 +5721,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5306 } 5721 }
5307 } 5722 }
5308 5723
5309 dpll |= DPLL_VCO_ENABLE;
5310
5311 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 5724 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5312 drm_mode_debug_printmodeline(mode); 5725 drm_mode_debug_printmodeline(mode);
5313 5726
5314 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5315
5316 POSTING_READ(DPLL(pipe));
5317 udelay(150);
5318
5319 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5320 * This is an exception to the general rule that mode_set doesn't turn
5321 * things on.
5322 */
5323 if (is_lvds) {
5324 temp = I915_READ(LVDS);
5325 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5326 if (pipe == 1) {
5327 temp |= LVDS_PIPEB_SELECT;
5328 } else {
5329 temp &= ~LVDS_PIPEB_SELECT;
5330 }
5331 /* set the corresponsding LVDS_BORDER bit */
5332 temp |= dev_priv->lvds_border_bits;
5333 /* Set the B0-B3 data pairs corresponding to whether we're going to
5334 * set the DPLLs for dual-channel mode or not.
5335 */
5336 if (clock.p2 == 7)
5337 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5338 else
5339 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5340
5341 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5342 * appropriately here, but we need to look more thoroughly into how
5343 * panels behave in the two modes.
5344 */
5345 /* set the dithering flag on LVDS as needed */
5346 if (INTEL_INFO(dev)->gen >= 4) {
5347 if (dev_priv->lvds_dither)
5348 temp |= LVDS_ENABLE_DITHER;
5349 else
5350 temp &= ~LVDS_ENABLE_DITHER;
5351 }
5352 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5353 lvds_sync |= LVDS_HSYNC_POLARITY;
5354 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5355 lvds_sync |= LVDS_VSYNC_POLARITY;
5356 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5357 != lvds_sync) {
5358 char flags[2] = "-+";
5359 DRM_INFO("Changing LVDS panel from "
5360 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5361 flags[!(temp & LVDS_HSYNC_POLARITY)],
5362 flags[!(temp & LVDS_VSYNC_POLARITY)],
5363 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5364 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5365 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5366 temp |= lvds_sync;
5367 }
5368 I915_WRITE(LVDS, temp);
5369 }
5370
5371 if (is_dp) {
5372 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5373 }
5374
5375 I915_WRITE(DPLL(pipe), dpll);
5376
5377 /* Wait for the clocks to stabilize. */
5378 POSTING_READ(DPLL(pipe));
5379 udelay(150);
5380
5381 if (INTEL_INFO(dev)->gen >= 4) {
5382 temp = 0;
5383 if (is_sdvo) {
5384 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5385 if (temp > 1)
5386 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5387 else
5388 temp = 0;
5389 }
5390 I915_WRITE(DPLL_MD(pipe), temp);
5391 } else {
5392 /* The pixel multiplier can only be updated once the
5393 * DPLL is enabled and the clocks are stable.
5394 *
5395 * So write it again.
5396 */
5397 I915_WRITE(DPLL(pipe), dpll);
5398 }
5399
5400 if (HAS_PIPE_CXSR(dev)) { 5727 if (HAS_PIPE_CXSR(dev)) {
5401 if (intel_crtc->lowfreq_avail) { 5728 if (intel_crtc->lowfreq_avail) {
5402 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 5729 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
@@ -7796,7 +8123,7 @@ static void intel_setup_outputs(struct drm_device *dev)
7796 8123
7797 if (I915_READ(HDMIB) & PORT_DETECTED) { 8124 if (I915_READ(HDMIB) & PORT_DETECTED) {
7798 /* PCH SDVOB multiplex with HDMIB */ 8125 /* PCH SDVOB multiplex with HDMIB */
7799 found = intel_sdvo_init(dev, PCH_SDVOB); 8126 found = intel_sdvo_init(dev, PCH_SDVOB, true);
7800 if (!found) 8127 if (!found)
7801 intel_hdmi_init(dev, HDMIB); 8128 intel_hdmi_init(dev, HDMIB);
7802 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 8129 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
@@ -7820,7 +8147,7 @@ static void intel_setup_outputs(struct drm_device *dev)
7820 8147
7821 if (I915_READ(SDVOB) & SDVO_DETECTED) { 8148 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7822 DRM_DEBUG_KMS("probing SDVOB\n"); 8149 DRM_DEBUG_KMS("probing SDVOB\n");
7823 found = intel_sdvo_init(dev, SDVOB); 8150 found = intel_sdvo_init(dev, SDVOB, true);
7824 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { 8151 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7825 DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); 8152 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7826 intel_hdmi_init(dev, SDVOB); 8153 intel_hdmi_init(dev, SDVOB);
@@ -7836,7 +8163,7 @@ static void intel_setup_outputs(struct drm_device *dev)
7836 8163
7837 if (I915_READ(SDVOB) & SDVO_DETECTED) { 8164 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7838 DRM_DEBUG_KMS("probing SDVOC\n"); 8165 DRM_DEBUG_KMS("probing SDVOC\n");
7839 found = intel_sdvo_init(dev, SDVOC); 8166 found = intel_sdvo_init(dev, SDVOC, false);
7840 } 8167 }
7841 8168
7842 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { 8169 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
@@ -8617,6 +8944,54 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
8617 } 8944 }
8618} 8945}
8619 8946
8947static void valleyview_init_clock_gating(struct drm_device *dev)
8948{
8949 struct drm_i915_private *dev_priv = dev->dev_private;
8950 int pipe;
8951 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8952
8953 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8954
8955 I915_WRITE(WM3_LP_ILK, 0);
8956 I915_WRITE(WM2_LP_ILK, 0);
8957 I915_WRITE(WM1_LP_ILK, 0);
8958
8959 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8960 * This implements the WaDisableRCZUnitClockGating workaround.
8961 */
8962 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8963
8964 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8965
8966 I915_WRITE(IVB_CHICKEN3,
8967 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8968 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8969
8970 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8971 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8972 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8973
8974 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8975 I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
8976 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
8977
8978 /* This is required by WaCatErrorRejectionIssue */
8979 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8980 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8981 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8982
8983 for_each_pipe(pipe) {
8984 I915_WRITE(DSPCNTR(pipe),
8985 I915_READ(DSPCNTR(pipe)) |
8986 DISPPLANE_TRICKLE_FEED_DISABLE);
8987 intel_flush_display_plane(dev_priv, pipe);
8988 }
8989
8990 I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) |
8991 (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) |
8992 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
8993}
8994
8620static void g4x_init_clock_gating(struct drm_device *dev) 8995static void g4x_init_clock_gating(struct drm_device *dev)
8621{ 8996{
8622 struct drm_i915_private *dev_priv = dev->dev_private; 8997 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8871,7 +9246,10 @@ static void intel_init_display(struct drm_device *dev)
8871 } 9246 }
8872 9247
8873 /* Returns the core display clock speed */ 9248 /* Returns the core display clock speed */
8874 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) 9249 if (IS_VALLEYVIEW(dev))
9250 dev_priv->display.get_display_clock_speed =
9251 valleyview_get_display_clock_speed;
9252 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8875 dev_priv->display.get_display_clock_speed = 9253 dev_priv->display.get_display_clock_speed =
8876 i945_get_display_clock_speed; 9254 i945_get_display_clock_speed;
8877 else if (IS_I915G(dev)) 9255 else if (IS_I915G(dev))
@@ -8966,6 +9344,12 @@ static void intel_init_display(struct drm_device *dev)
8966 dev_priv->display.write_eld = ironlake_write_eld; 9344 dev_priv->display.write_eld = ironlake_write_eld;
8967 } else 9345 } else
8968 dev_priv->display.update_wm = NULL; 9346 dev_priv->display.update_wm = NULL;
9347 } else if (IS_VALLEYVIEW(dev)) {
9348 dev_priv->display.update_wm = valleyview_update_wm;
9349 dev_priv->display.init_clock_gating =
9350 valleyview_init_clock_gating;
9351 dev_priv->display.force_wake_get = vlv_force_wake_get;
9352 dev_priv->display.force_wake_put = vlv_force_wake_put;
8969 } else if (IS_PINEVIEW(dev)) { 9353 } else if (IS_PINEVIEW(dev)) {
8970 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 9354 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8971 dev_priv->is_ddr3, 9355 dev_priv->is_ddr3,
@@ -9049,7 +9433,7 @@ static void quirk_pipea_force(struct drm_device *dev)
9049 struct drm_i915_private *dev_priv = dev->dev_private; 9433 struct drm_i915_private *dev_priv = dev->dev_private;
9050 9434
9051 dev_priv->quirks |= QUIRK_PIPEA_FORCE; 9435 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9052 DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); 9436 DRM_INFO("applying pipe a force quirk\n");
9053} 9437}
9054 9438
9055/* 9439/*
@@ -9059,6 +9443,18 @@ static void quirk_ssc_force_disable(struct drm_device *dev)
9059{ 9443{
9060 struct drm_i915_private *dev_priv = dev->dev_private; 9444 struct drm_i915_private *dev_priv = dev->dev_private;
9061 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 9445 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9446 DRM_INFO("applying lvds SSC disable quirk\n");
9447}
9448
9449/*
9450 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9451 * brightness value
9452 */
9453static void quirk_invert_brightness(struct drm_device *dev)
9454{
9455 struct drm_i915_private *dev_priv = dev->dev_private;
9456 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9457 DRM_INFO("applying inverted panel brightness quirk\n");
9062} 9458}
9063 9459
9064struct intel_quirk { 9460struct intel_quirk {
@@ -9093,6 +9489,9 @@ struct intel_quirk intel_quirks[] = {
9093 9489
9094 /* Sony Vaio Y cannot use SSC on LVDS */ 9490 /* Sony Vaio Y cannot use SSC on LVDS */
9095 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, 9491 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9492
9493 /* Acer Aspire 5734Z must invert backlight brightness */
9494 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9096}; 9495};
9097 9496
9098static void intel_init_quirks(struct drm_device *dev) 9497static void intel_init_quirks(struct drm_device *dev)
@@ -9236,6 +9635,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
9236 if (IS_IRONLAKE_M(dev)) 9635 if (IS_IRONLAKE_M(dev))
9237 ironlake_disable_rc6(dev); 9636 ironlake_disable_rc6(dev);
9238 9637
9638 if (IS_VALLEYVIEW(dev))
9639 vlv_init_dpio(dev);
9640
9239 mutex_unlock(&dev->struct_mutex); 9641 mutex_unlock(&dev->struct_mutex);
9240 9642
9241 /* Disable the irq before mode object teardown, for the irq might 9643 /* Disable the irq before mode object teardown, for the irq might
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 10:29:52 -0400