1 files changed, 34 insertions, 13 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2b6ce9b2674a..682bd3729baf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3253,6 +3253,16 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
         if (HAS_PCH_CPT(dev))
                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
+
+        /*
+         * There seems to be a race in PCH platform hw (at least on some
+         * outputs) where an enabled pipe still completes any pageflip right
+         * away (as if the pipe is off) instead of waiting for vblank. As soon
+         * as the first vblank happend, everything works as expected. Hence just
+         * wait for one vblank before returning to avoid strange things
+         * happening.
+         */
+        intel_wait_for_vblank(dev, intel_crtc->pipe);
 }
 
 static void ironlake_crtc_disable(struct drm_crtc *crtc)
@@ -7892,8 +7902,7 @@ static struct intel_quirk intel_quirks[] = {
         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
 
-        /* 855 & before need to leave pipe A & dpll A up */
-        { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+        /* 830/845 need to leave pipe A & dpll A up */
         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
 
@@ -8049,29 +8058,42 @@ static void intel_enable_pipe_a(struct drm_device *dev)
 
 }
 
+static bool
+intel_check_plane_mapping(struct intel_crtc *crtc)
+{
+        struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+        u32 reg, val;
+
+        if (dev_priv->num_pipe == 1)
+                return true;
+
+        reg = DSPCNTR(!crtc->plane);
+        val = I915_READ(reg);
+
+        if ((val & DISPLAY_PLANE_ENABLE) &&
+            (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
+                return false;
+
+        return true;
+}
+
 static void intel_sanitize_crtc(struct intel_crtc *crtc)
 {
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 reg, val;
+        u32 reg;
 
         /* Clear any frame start delays used for debugging left by the BIOS */
         reg = PIPECONF(crtc->pipe);
         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
 
         /* We need to sanitize the plane -> pipe mapping first because this will
-         * disable the crtc (and hence change the state) if it is wrong. */
-        if (!HAS_PCH_SPLIT(dev)) {
+         * disable the crtc (and hence change the state) if it is wrong. Note
+         * that gen4+ has a fixed plane -> pipe mapping.  */
+        if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
                 struct intel_connector *connector;
                 bool plane;
 
-                reg = DSPCNTR(crtc->plane);
-                val = I915_READ(reg);
-
-                if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
-                    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
-                        goto ok;
-
                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
                               crtc->base.base.id);
 
@@ -8095,7 +8117,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
                 WARN_ON(crtc->active);
                 crtc->base.enabled = false;
         }
-ok:
 
         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
             crtc->pipe == PIPE_A && !crtc->active) {