aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_display.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c87
1 files changed, 30 insertions, 57 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d6fce2133413..748ed50c55ca 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -666,7 +666,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
666 intel_clock_t clock; 666 intel_clock_t clock;
667 int err = target; 667 int err = target;
668 668
669 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 669 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
670 (I915_READ(LVDS)) != 0) { 670 (I915_READ(LVDS)) != 0) {
671 /* 671 /*
672 * For LVDS, if the panel is on, just rely on its current 672 * For LVDS, if the panel is on, just rely on its current
@@ -2005,7 +2005,21 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2005 return; 2005 return;
2006} 2006}
2007 2007
2008const static int latency_ns = 3000; /* default for non-igd platforms */ 2008/*
2009 * Latency for FIFO fetches is dependent on several factors:
2010 * - memory configuration (speed, channels)
2011 * - chipset
2012 * - current MCH state
2013 * It can be fairly high in some situations, so here we assume a fairly
2014 * pessimal value. It's a tradeoff between extra memory fetches (if we
2015 * set this value too high, the FIFO will fetch frequently to stay full)
2016 * and power consumption (set it too low to save power and we might see
2017 * FIFO underruns and display "flicker").
2018 *
2019 * A value of 5us seems to be a good balance; safe for very low end
2020 * platforms but not overly aggressive on lower latency configs.
2021 */
2022const static int latency_ns = 5000;
2009 2023
2010static int intel_get_fifo_size(struct drm_device *dev, int plane) 2024static int intel_get_fifo_size(struct drm_device *dev, int plane)
2011{ 2025{
@@ -2396,7 +2410,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2396 if (is_sdvo) { 2410 if (is_sdvo) {
2397 dpll |= DPLL_DVO_HIGH_SPEED; 2411 dpll |= DPLL_DVO_HIGH_SPEED;
2398 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 2412 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2399 if (IS_I945G(dev) || IS_I945GM(dev)) 2413 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2400 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 2414 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2401 else if (IS_IGDNG(dev)) 2415 else if (IS_IGDNG(dev))
2402 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 2416 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
@@ -3170,7 +3184,7 @@ static int intel_connector_clones(struct drm_device *dev, int type_mask)
3170 3184
3171 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 3185 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3172 struct intel_output *intel_output = to_intel_output(connector); 3186 struct intel_output *intel_output = to_intel_output(connector);
3173 if (type_mask & (1 << intel_output->type)) 3187 if (type_mask & intel_output->clone_mask)
3174 index_mask |= (1 << entry); 3188 index_mask |= (1 << entry);
3175 entry++; 3189 entry++;
3176 } 3190 }
@@ -3218,30 +3232,30 @@ static void intel_setup_outputs(struct drm_device *dev)
3218 intel_dp_init(dev, PCH_DP_D); 3232 intel_dp_init(dev, PCH_DP_D);
3219 3233
3220 } else if (IS_I9XX(dev)) { 3234 } else if (IS_I9XX(dev)) {
3221 int found; 3235 bool found = false;
3222 u32 reg;
3223 3236
3224 if (I915_READ(SDVOB) & SDVO_DETECTED) { 3237 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3225 found = intel_sdvo_init(dev, SDVOB); 3238 found = intel_sdvo_init(dev, SDVOB);
3226 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 3239 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3227 intel_hdmi_init(dev, SDVOB); 3240 intel_hdmi_init(dev, SDVOB);
3241
3228 if (!found && SUPPORTS_INTEGRATED_DP(dev)) 3242 if (!found && SUPPORTS_INTEGRATED_DP(dev))
3229 intel_dp_init(dev, DP_B); 3243 intel_dp_init(dev, DP_B);
3230 } 3244 }
3231 3245
3232 /* Before G4X SDVOC doesn't have its own detect register */ 3246 /* Before G4X SDVOC doesn't have its own detect register */
3233 if (IS_G4X(dev))
3234 reg = SDVOC;
3235 else
3236 reg = SDVOB;
3237 3247
3238 if (I915_READ(reg) & SDVO_DETECTED) { 3248 if (I915_READ(SDVOB) & SDVO_DETECTED)
3239 found = intel_sdvo_init(dev, SDVOC); 3249 found = intel_sdvo_init(dev, SDVOC);
3240 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 3250
3251 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
3252
3253 if (SUPPORTS_INTEGRATED_HDMI(dev))
3241 intel_hdmi_init(dev, SDVOC); 3254 intel_hdmi_init(dev, SDVOC);
3242 if (!found && SUPPORTS_INTEGRATED_DP(dev)) 3255 if (SUPPORTS_INTEGRATED_DP(dev))
3243 intel_dp_init(dev, DP_C); 3256 intel_dp_init(dev, DP_C);
3244 } 3257 }
3258
3245 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED)) 3259 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3246 intel_dp_init(dev, DP_D); 3260 intel_dp_init(dev, DP_D);
3247 } else 3261 } else
@@ -3253,51 +3267,10 @@ static void intel_setup_outputs(struct drm_device *dev)
3253 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 3267 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3254 struct intel_output *intel_output = to_intel_output(connector); 3268 struct intel_output *intel_output = to_intel_output(connector);
3255 struct drm_encoder *encoder = &intel_output->enc; 3269 struct drm_encoder *encoder = &intel_output->enc;
3256 int crtc_mask = 0, clone_mask = 0;
3257 3270
3258 /* valid crtcs */ 3271 encoder->possible_crtcs = intel_output->crtc_mask;
3259 switch(intel_output->type) { 3272 encoder->possible_clones = intel_connector_clones(dev,
3260 case INTEL_OUTPUT_HDMI: 3273 intel_output->clone_mask);
3261 crtc_mask = ((1 << 0)|
3262 (1 << 1));
3263 clone_mask = ((1 << INTEL_OUTPUT_HDMI));
3264 break;
3265 case INTEL_OUTPUT_DVO:
3266 case INTEL_OUTPUT_SDVO:
3267 crtc_mask = ((1 << 0)|
3268 (1 << 1));
3269 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3270 (1 << INTEL_OUTPUT_DVO) |
3271 (1 << INTEL_OUTPUT_SDVO));
3272 break;
3273 case INTEL_OUTPUT_ANALOG:
3274 crtc_mask = ((1 << 0)|
3275 (1 << 1));
3276 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3277 (1 << INTEL_OUTPUT_DVO) |
3278 (1 << INTEL_OUTPUT_SDVO));
3279 break;
3280 case INTEL_OUTPUT_LVDS:
3281 crtc_mask = (1 << 1);
3282 clone_mask = (1 << INTEL_OUTPUT_LVDS);
3283 break;
3284 case INTEL_OUTPUT_TVOUT:
3285 crtc_mask = ((1 << 0) |
3286 (1 << 1));
3287 clone_mask = (1 << INTEL_OUTPUT_TVOUT);
3288 break;
3289 case INTEL_OUTPUT_DISPLAYPORT:
3290 crtc_mask = ((1 << 0) |
3291 (1 << 1));
3292 clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
3293 break;
3294 case INTEL_OUTPUT_EDP:
3295 crtc_mask = (1 << 1);
3296 clone_mask = (1 << INTEL_OUTPUT_EDP);
3297 break;
3298 }
3299 encoder->possible_crtcs = crtc_mask;
3300 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
3301 } 3274 }
3302} 3275}
3303 3276