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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c947
1 files changed, 689 insertions, 258 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e7356fb6c918..4bb60af5bf2d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -742,12 +742,11 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742{ 742{
743 struct drm_device *dev = crtc->dev; 743 struct drm_device *dev = crtc->dev;
744 struct drm_mode_config *mode_config = &dev->mode_config; 744 struct drm_mode_config *mode_config = &dev->mode_config;
745 struct drm_connector *l_entry; 745 struct drm_encoder *l_entry;
746 746
747 list_for_each_entry(l_entry, &mode_config->connector_list, head) { 747 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748 if (l_entry->encoder && 748 if (l_entry && l_entry->crtc == crtc) {
749 l_entry->encoder->crtc == crtc) { 749 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750 struct intel_encoder *intel_encoder = to_intel_encoder(l_entry);
751 if (intel_encoder->type == type) 750 if (intel_encoder->type == type)
752 return true; 751 return true;
753 } 752 }
@@ -755,23 +754,6 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
755 return false; 754 return false;
756} 755}
757 756
758static struct drm_connector *
759intel_pipe_get_connector (struct drm_crtc *crtc)
760{
761 struct drm_device *dev = crtc->dev;
762 struct drm_mode_config *mode_config = &dev->mode_config;
763 struct drm_connector *l_entry, *ret = NULL;
764
765 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
766 if (l_entry->encoder &&
767 l_entry->encoder->crtc == crtc) {
768 ret = l_entry;
769 break;
770 }
771 }
772 return ret;
773}
774
775#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) 757#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
776/** 758/**
777 * Returns whether the given set of divisors are valid for a given refclk with 759 * Returns whether the given set of divisors are valid for a given refclk with
@@ -1510,6 +1492,219 @@ static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1510 udelay(500); 1492 udelay(500);
1511} 1493}
1512 1494
1495/* The FDI link training functions for ILK/Ibexpeak. */
1496static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1497{
1498 struct drm_device *dev = crtc->dev;
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1501 int pipe = intel_crtc->pipe;
1502 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1503 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1504 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1505 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1506 u32 temp, tries = 0;
1507
1508 /* enable CPU FDI TX and PCH FDI RX */
1509 temp = I915_READ(fdi_tx_reg);
1510 temp |= FDI_TX_ENABLE;
1511 temp &= ~(7 << 19);
1512 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1513 temp &= ~FDI_LINK_TRAIN_NONE;
1514 temp |= FDI_LINK_TRAIN_PATTERN_1;
1515 I915_WRITE(fdi_tx_reg, temp);
1516 I915_READ(fdi_tx_reg);
1517
1518 temp = I915_READ(fdi_rx_reg);
1519 temp &= ~FDI_LINK_TRAIN_NONE;
1520 temp |= FDI_LINK_TRAIN_PATTERN_1;
1521 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1522 I915_READ(fdi_rx_reg);
1523 udelay(150);
1524
1525 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1526 for train result */
1527 temp = I915_READ(fdi_rx_imr_reg);
1528 temp &= ~FDI_RX_SYMBOL_LOCK;
1529 temp &= ~FDI_RX_BIT_LOCK;
1530 I915_WRITE(fdi_rx_imr_reg, temp);
1531 I915_READ(fdi_rx_imr_reg);
1532 udelay(150);
1533
1534 for (;;) {
1535 temp = I915_READ(fdi_rx_iir_reg);
1536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1537
1538 if ((temp & FDI_RX_BIT_LOCK)) {
1539 DRM_DEBUG_KMS("FDI train 1 done.\n");
1540 I915_WRITE(fdi_rx_iir_reg,
1541 temp | FDI_RX_BIT_LOCK);
1542 break;
1543 }
1544
1545 tries++;
1546
1547 if (tries > 5) {
1548 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1549 break;
1550 }
1551 }
1552
1553 /* Train 2 */
1554 temp = I915_READ(fdi_tx_reg);
1555 temp &= ~FDI_LINK_TRAIN_NONE;
1556 temp |= FDI_LINK_TRAIN_PATTERN_2;
1557 I915_WRITE(fdi_tx_reg, temp);
1558
1559 temp = I915_READ(fdi_rx_reg);
1560 temp &= ~FDI_LINK_TRAIN_NONE;
1561 temp |= FDI_LINK_TRAIN_PATTERN_2;
1562 I915_WRITE(fdi_rx_reg, temp);
1563 udelay(150);
1564
1565 tries = 0;
1566
1567 for (;;) {
1568 temp = I915_READ(fdi_rx_iir_reg);
1569 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1570
1571 if (temp & FDI_RX_SYMBOL_LOCK) {
1572 I915_WRITE(fdi_rx_iir_reg,
1573 temp | FDI_RX_SYMBOL_LOCK);
1574 DRM_DEBUG_KMS("FDI train 2 done.\n");
1575 break;
1576 }
1577
1578 tries++;
1579
1580 if (tries > 5) {
1581 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1582 break;
1583 }
1584 }
1585
1586 DRM_DEBUG_KMS("FDI train done\n");
1587}
1588
1589static int snb_b_fdi_train_param [] = {
1590 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1591 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1592 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1593 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1594};
1595
1596/* The FDI link training functions for SNB/Cougarpoint. */
1597static void gen6_fdi_link_train(struct drm_crtc *crtc)
1598{
1599 struct drm_device *dev = crtc->dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1602 int pipe = intel_crtc->pipe;
1603 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1604 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1605 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1606 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1607 u32 temp, i;
1608
1609 /* enable CPU FDI TX and PCH FDI RX */
1610 temp = I915_READ(fdi_tx_reg);
1611 temp |= FDI_TX_ENABLE;
1612 temp &= ~(7 << 19);
1613 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1614 temp &= ~FDI_LINK_TRAIN_NONE;
1615 temp |= FDI_LINK_TRAIN_PATTERN_1;
1616 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1617 /* SNB-B */
1618 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1619 I915_WRITE(fdi_tx_reg, temp);
1620 I915_READ(fdi_tx_reg);
1621
1622 temp = I915_READ(fdi_rx_reg);
1623 if (HAS_PCH_CPT(dev)) {
1624 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1625 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1626 } else {
1627 temp &= ~FDI_LINK_TRAIN_NONE;
1628 temp |= FDI_LINK_TRAIN_PATTERN_1;
1629 }
1630 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1631 I915_READ(fdi_rx_reg);
1632 udelay(150);
1633
1634 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1635 for train result */
1636 temp = I915_READ(fdi_rx_imr_reg);
1637 temp &= ~FDI_RX_SYMBOL_LOCK;
1638 temp &= ~FDI_RX_BIT_LOCK;
1639 I915_WRITE(fdi_rx_imr_reg, temp);
1640 I915_READ(fdi_rx_imr_reg);
1641 udelay(150);
1642
1643 for (i = 0; i < 4; i++ ) {
1644 temp = I915_READ(fdi_tx_reg);
1645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1646 temp |= snb_b_fdi_train_param[i];
1647 I915_WRITE(fdi_tx_reg, temp);
1648 udelay(500);
1649
1650 temp = I915_READ(fdi_rx_iir_reg);
1651 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1652
1653 if (temp & FDI_RX_BIT_LOCK) {
1654 I915_WRITE(fdi_rx_iir_reg,
1655 temp | FDI_RX_BIT_LOCK);
1656 DRM_DEBUG_KMS("FDI train 1 done.\n");
1657 break;
1658 }
1659 }
1660 if (i == 4)
1661 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1662
1663 /* Train 2 */
1664 temp = I915_READ(fdi_tx_reg);
1665 temp &= ~FDI_LINK_TRAIN_NONE;
1666 temp |= FDI_LINK_TRAIN_PATTERN_2;
1667 if (IS_GEN6(dev)) {
1668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1669 /* SNB-B */
1670 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1671 }
1672 I915_WRITE(fdi_tx_reg, temp);
1673
1674 temp = I915_READ(fdi_rx_reg);
1675 if (HAS_PCH_CPT(dev)) {
1676 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1677 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1678 } else {
1679 temp &= ~FDI_LINK_TRAIN_NONE;
1680 temp |= FDI_LINK_TRAIN_PATTERN_2;
1681 }
1682 I915_WRITE(fdi_rx_reg, temp);
1683 udelay(150);
1684
1685 for (i = 0; i < 4; i++ ) {
1686 temp = I915_READ(fdi_tx_reg);
1687 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1688 temp |= snb_b_fdi_train_param[i];
1689 I915_WRITE(fdi_tx_reg, temp);
1690 udelay(500);
1691
1692 temp = I915_READ(fdi_rx_iir_reg);
1693 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1694
1695 if (temp & FDI_RX_SYMBOL_LOCK) {
1696 I915_WRITE(fdi_rx_iir_reg,
1697 temp | FDI_RX_SYMBOL_LOCK);
1698 DRM_DEBUG_KMS("FDI train 2 done.\n");
1699 break;
1700 }
1701 }
1702 if (i == 4)
1703 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1704
1705 DRM_DEBUG_KMS("FDI train done.\n");
1706}
1707
1513static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) 1708static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1514{ 1709{
1515 struct drm_device *dev = crtc->dev; 1710 struct drm_device *dev = crtc->dev;
@@ -1523,8 +1718,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1523 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; 1718 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1524 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; 1719 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1525 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; 1720 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1526 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1527 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1528 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; 1721 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1529 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1; 1722 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1530 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ; 1723 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
@@ -1541,8 +1734,9 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1541 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; 1734 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1542 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; 1735 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1543 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1736 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1737 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1544 u32 temp; 1738 u32 temp;
1545 int tries = 5, j, n; 1739 int n;
1546 u32 pipe_bpc; 1740 u32 pipe_bpc;
1547 1741
1548 temp = I915_READ(pipeconf_reg); 1742 temp = I915_READ(pipeconf_reg);
@@ -1569,12 +1763,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1569 /* enable eDP PLL */ 1763 /* enable eDP PLL */
1570 ironlake_enable_pll_edp(crtc); 1764 ironlake_enable_pll_edp(crtc);
1571 } else { 1765 } else {
1572 /* enable PCH DPLL */
1573 temp = I915_READ(pch_dpll_reg);
1574 if ((temp & DPLL_VCO_ENABLE) == 0) {
1575 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1576 I915_READ(pch_dpll_reg);
1577 }
1578 1766
1579 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1767 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1580 temp = I915_READ(fdi_rx_reg); 1768 temp = I915_READ(fdi_rx_reg);
@@ -1584,9 +1772,15 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1584 */ 1772 */
1585 temp &= ~(0x7 << 16); 1773 temp &= ~(0x7 << 16);
1586 temp |= (pipe_bpc << 11); 1774 temp |= (pipe_bpc << 11);
1587 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | 1775 temp &= ~(7 << 19);
1588 FDI_SEL_PCDCLK | 1776 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1589 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */ 1777 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1778 I915_READ(fdi_rx_reg);
1779 udelay(200);
1780
1781 /* Switch from Rawclk to PCDclk */
1782 temp = I915_READ(fdi_rx_reg);
1783 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1590 I915_READ(fdi_rx_reg); 1784 I915_READ(fdi_rx_reg);
1591 udelay(200); 1785 udelay(200);
1592 1786
@@ -1629,91 +1823,32 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1629 } 1823 }
1630 1824
1631 if (!HAS_eDP) { 1825 if (!HAS_eDP) {
1632 /* enable CPU FDI TX and PCH FDI RX */ 1826 /* For PCH output, training FDI link */
1633 temp = I915_READ(fdi_tx_reg); 1827 if (IS_GEN6(dev))
1634 temp |= FDI_TX_ENABLE; 1828 gen6_fdi_link_train(crtc);
1635 temp |= FDI_DP_PORT_WIDTH_X4; /* default */ 1829 else
1636 temp &= ~FDI_LINK_TRAIN_NONE; 1830 ironlake_fdi_link_train(crtc);
1637 temp |= FDI_LINK_TRAIN_PATTERN_1;
1638 I915_WRITE(fdi_tx_reg, temp);
1639 I915_READ(fdi_tx_reg);
1640
1641 temp = I915_READ(fdi_rx_reg);
1642 temp &= ~FDI_LINK_TRAIN_NONE;
1643 temp |= FDI_LINK_TRAIN_PATTERN_1;
1644 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1645 I915_READ(fdi_rx_reg);
1646
1647 udelay(150);
1648
1649 /* Train FDI. */
1650 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1651 for train result */
1652 temp = I915_READ(fdi_rx_imr_reg);
1653 temp &= ~FDI_RX_SYMBOL_LOCK;
1654 temp &= ~FDI_RX_BIT_LOCK;
1655 I915_WRITE(fdi_rx_imr_reg, temp);
1656 I915_READ(fdi_rx_imr_reg);
1657 udelay(150);
1658 1831
1659 temp = I915_READ(fdi_rx_iir_reg); 1832 /* enable PCH DPLL */
1660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 1833 temp = I915_READ(pch_dpll_reg);
1661 1834 if ((temp & DPLL_VCO_ENABLE) == 0) {
1662 if ((temp & FDI_RX_BIT_LOCK) == 0) { 1835 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1663 for (j = 0; j < tries; j++) { 1836 I915_READ(pch_dpll_reg);
1664 temp = I915_READ(fdi_rx_iir_reg);
1665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1666 temp);
1667 if (temp & FDI_RX_BIT_LOCK)
1668 break;
1669 udelay(200);
1670 }
1671 if (j != tries)
1672 I915_WRITE(fdi_rx_iir_reg,
1673 temp | FDI_RX_BIT_LOCK);
1674 else
1675 DRM_DEBUG_KMS("train 1 fail\n");
1676 } else {
1677 I915_WRITE(fdi_rx_iir_reg,
1678 temp | FDI_RX_BIT_LOCK);
1679 DRM_DEBUG_KMS("train 1 ok 2!\n");
1680 } 1837 }
1681 temp = I915_READ(fdi_tx_reg); 1838 udelay(200);
1682 temp &= ~FDI_LINK_TRAIN_NONE;
1683 temp |= FDI_LINK_TRAIN_PATTERN_2;
1684 I915_WRITE(fdi_tx_reg, temp);
1685
1686 temp = I915_READ(fdi_rx_reg);
1687 temp &= ~FDI_LINK_TRAIN_NONE;
1688 temp |= FDI_LINK_TRAIN_PATTERN_2;
1689 I915_WRITE(fdi_rx_reg, temp);
1690
1691 udelay(150);
1692 1839
1693 temp = I915_READ(fdi_rx_iir_reg); 1840 if (HAS_PCH_CPT(dev)) {
1694 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 1841 /* Be sure PCH DPLL SEL is set */
1695 1842 temp = I915_READ(PCH_DPLL_SEL);
1696 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { 1843 if (trans_dpll_sel == 0 &&
1697 for (j = 0; j < tries; j++) { 1844 (temp & TRANSA_DPLL_ENABLE) == 0)
1698 temp = I915_READ(fdi_rx_iir_reg); 1845 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1699 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", 1846 else if (trans_dpll_sel == 1 &&
1700 temp); 1847 (temp & TRANSB_DPLL_ENABLE) == 0)
1701 if (temp & FDI_RX_SYMBOL_LOCK) 1848 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1702 break; 1849 I915_WRITE(PCH_DPLL_SEL, temp);
1703 udelay(200); 1850 I915_READ(PCH_DPLL_SEL);
1704 }
1705 if (j != tries) {
1706 I915_WRITE(fdi_rx_iir_reg,
1707 temp | FDI_RX_SYMBOL_LOCK);
1708 DRM_DEBUG_KMS("train 2 ok 1!\n");
1709 } else
1710 DRM_DEBUG_KMS("train 2 fail\n");
1711 } else {
1712 I915_WRITE(fdi_rx_iir_reg,
1713 temp | FDI_RX_SYMBOL_LOCK);
1714 DRM_DEBUG_KMS("train 2 ok 2!\n");
1715 } 1851 }
1716 DRM_DEBUG_KMS("train done\n");
1717 1852
1718 /* set transcoder timing */ 1853 /* set transcoder timing */
1719 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); 1854 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
@@ -1724,6 +1859,60 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1724 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg)); 1859 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1725 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg)); 1860 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1726 1861
1862 /* enable normal train */
1863 temp = I915_READ(fdi_tx_reg);
1864 temp &= ~FDI_LINK_TRAIN_NONE;
1865 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1866 FDI_TX_ENHANCE_FRAME_ENABLE);
1867 I915_READ(fdi_tx_reg);
1868
1869 temp = I915_READ(fdi_rx_reg);
1870 if (HAS_PCH_CPT(dev)) {
1871 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1872 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1873 } else {
1874 temp &= ~FDI_LINK_TRAIN_NONE;
1875 temp |= FDI_LINK_TRAIN_NONE;
1876 }
1877 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1878 I915_READ(fdi_rx_reg);
1879
1880 /* wait one idle pattern time */
1881 udelay(100);
1882
1883 /* For PCH DP, enable TRANS_DP_CTL */
1884 if (HAS_PCH_CPT(dev) &&
1885 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1886 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1887 int reg;
1888
1889 reg = I915_READ(trans_dp_ctl);
1890 reg &= ~TRANS_DP_PORT_SEL_MASK;
1891 reg = TRANS_DP_OUTPUT_ENABLE |
1892 TRANS_DP_ENH_FRAMING |
1893 TRANS_DP_VSYNC_ACTIVE_HIGH |
1894 TRANS_DP_HSYNC_ACTIVE_HIGH;
1895
1896 switch (intel_trans_dp_port_sel(crtc)) {
1897 case PCH_DP_B:
1898 reg |= TRANS_DP_PORT_SEL_B;
1899 break;
1900 case PCH_DP_C:
1901 reg |= TRANS_DP_PORT_SEL_C;
1902 break;
1903 case PCH_DP_D:
1904 reg |= TRANS_DP_PORT_SEL_D;
1905 break;
1906 default:
1907 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1908 reg |= TRANS_DP_PORT_SEL_B;
1909 break;
1910 }
1911
1912 I915_WRITE(trans_dp_ctl, reg);
1913 POSTING_READ(trans_dp_ctl);
1914 }
1915
1727 /* enable PCH transcoder */ 1916 /* enable PCH transcoder */
1728 temp = I915_READ(transconf_reg); 1917 temp = I915_READ(transconf_reg);
1729 /* 1918 /*
@@ -1738,23 +1927,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1738 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) 1927 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1739 ; 1928 ;
1740 1929
1741 /* enable normal */
1742
1743 temp = I915_READ(fdi_tx_reg);
1744 temp &= ~FDI_LINK_TRAIN_NONE;
1745 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1746 FDI_TX_ENHANCE_FRAME_ENABLE);
1747 I915_READ(fdi_tx_reg);
1748
1749 temp = I915_READ(fdi_rx_reg);
1750 temp &= ~FDI_LINK_TRAIN_NONE;
1751 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1752 FDI_RX_ENHANCE_FRAME_ENABLE);
1753 I915_READ(fdi_rx_reg);
1754
1755 /* wait one idle pattern time */
1756 udelay(100);
1757
1758 } 1930 }
1759 1931
1760 intel_crtc_load_lut(crtc); 1932 intel_crtc_load_lut(crtc);
@@ -1805,6 +1977,8 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1805 I915_READ(pf_ctl_reg); 1977 I915_READ(pf_ctl_reg);
1806 } 1978 }
1807 I915_WRITE(pf_win_size, 0); 1979 I915_WRITE(pf_win_size, 0);
1980 POSTING_READ(pf_win_size);
1981
1808 1982
1809 /* disable CPU FDI tx and PCH FDI rx */ 1983 /* disable CPU FDI tx and PCH FDI rx */
1810 temp = I915_READ(fdi_tx_reg); 1984 temp = I915_READ(fdi_tx_reg);
@@ -1825,11 +1999,18 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1825 temp &= ~FDI_LINK_TRAIN_NONE; 1999 temp &= ~FDI_LINK_TRAIN_NONE;
1826 temp |= FDI_LINK_TRAIN_PATTERN_1; 2000 temp |= FDI_LINK_TRAIN_PATTERN_1;
1827 I915_WRITE(fdi_tx_reg, temp); 2001 I915_WRITE(fdi_tx_reg, temp);
2002 POSTING_READ(fdi_tx_reg);
1828 2003
1829 temp = I915_READ(fdi_rx_reg); 2004 temp = I915_READ(fdi_rx_reg);
1830 temp &= ~FDI_LINK_TRAIN_NONE; 2005 if (HAS_PCH_CPT(dev)) {
1831 temp |= FDI_LINK_TRAIN_PATTERN_1; 2006 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2007 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2008 } else {
2009 temp &= ~FDI_LINK_TRAIN_NONE;
2010 temp |= FDI_LINK_TRAIN_PATTERN_1;
2011 }
1832 I915_WRITE(fdi_rx_reg, temp); 2012 I915_WRITE(fdi_rx_reg, temp);
2013 POSTING_READ(fdi_rx_reg);
1833 2014
1834 udelay(100); 2015 udelay(100);
1835 2016
@@ -1859,6 +2040,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1859 } 2040 }
1860 } 2041 }
1861 } 2042 }
2043
1862 temp = I915_READ(transconf_reg); 2044 temp = I915_READ(transconf_reg);
1863 /* BPC in transcoder is consistent with that in pipeconf */ 2045 /* BPC in transcoder is consistent with that in pipeconf */
1864 temp &= ~PIPE_BPC_MASK; 2046 temp &= ~PIPE_BPC_MASK;
@@ -1867,35 +2049,53 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1867 I915_READ(transconf_reg); 2049 I915_READ(transconf_reg);
1868 udelay(100); 2050 udelay(100);
1869 2051
2052 if (HAS_PCH_CPT(dev)) {
2053 /* disable TRANS_DP_CTL */
2054 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2055 int reg;
2056
2057 reg = I915_READ(trans_dp_ctl);
2058 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2059 I915_WRITE(trans_dp_ctl, reg);
2060 POSTING_READ(trans_dp_ctl);
2061
2062 /* disable DPLL_SEL */
2063 temp = I915_READ(PCH_DPLL_SEL);
2064 if (trans_dpll_sel == 0)
2065 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2066 else
2067 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2068 I915_WRITE(PCH_DPLL_SEL, temp);
2069 I915_READ(PCH_DPLL_SEL);
2070
2071 }
2072
1870 /* disable PCH DPLL */ 2073 /* disable PCH DPLL */
1871 temp = I915_READ(pch_dpll_reg); 2074 temp = I915_READ(pch_dpll_reg);
1872 if ((temp & DPLL_VCO_ENABLE) != 0) { 2075 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1873 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); 2076 I915_READ(pch_dpll_reg);
1874 I915_READ(pch_dpll_reg);
1875 }
1876 2077
1877 if (HAS_eDP) { 2078 if (HAS_eDP) {
1878 ironlake_disable_pll_edp(crtc); 2079 ironlake_disable_pll_edp(crtc);
1879 } 2080 }
1880 2081
2082 /* Switch from PCDclk to Rawclk */
1881 temp = I915_READ(fdi_rx_reg); 2083 temp = I915_READ(fdi_rx_reg);
1882 temp &= ~FDI_SEL_PCDCLK; 2084 temp &= ~FDI_SEL_PCDCLK;
1883 I915_WRITE(fdi_rx_reg, temp); 2085 I915_WRITE(fdi_rx_reg, temp);
1884 I915_READ(fdi_rx_reg); 2086 I915_READ(fdi_rx_reg);
1885 2087
2088 /* Disable CPU FDI TX PLL */
2089 temp = I915_READ(fdi_tx_reg);
2090 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2091 I915_READ(fdi_tx_reg);
2092 udelay(100);
2093
1886 temp = I915_READ(fdi_rx_reg); 2094 temp = I915_READ(fdi_rx_reg);
1887 temp &= ~FDI_RX_PLL_ENABLE; 2095 temp &= ~FDI_RX_PLL_ENABLE;
1888 I915_WRITE(fdi_rx_reg, temp); 2096 I915_WRITE(fdi_rx_reg, temp);
1889 I915_READ(fdi_rx_reg); 2097 I915_READ(fdi_rx_reg);
1890 2098
1891 /* Disable CPU FDI TX PLL */
1892 temp = I915_READ(fdi_tx_reg);
1893 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1894 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1895 I915_READ(fdi_tx_reg);
1896 udelay(100);
1897 }
1898
1899 /* Wait for the clocks to turn off. */ 2099 /* Wait for the clocks to turn off. */
1900 udelay(100); 2100 udelay(100);
1901 break; 2101 break;
@@ -2331,6 +2531,30 @@ static struct intel_watermark_params i830_wm_info = {
2331 I830_FIFO_LINE_SIZE 2531 I830_FIFO_LINE_SIZE
2332}; 2532};
2333 2533
2534static struct intel_watermark_params ironlake_display_wm_info = {
2535 ILK_DISPLAY_FIFO,
2536 ILK_DISPLAY_MAXWM,
2537 ILK_DISPLAY_DFTWM,
2538 2,
2539 ILK_FIFO_LINE_SIZE
2540};
2541
2542static struct intel_watermark_params ironlake_display_srwm_info = {
2543 ILK_DISPLAY_SR_FIFO,
2544 ILK_DISPLAY_MAX_SRWM,
2545 ILK_DISPLAY_DFT_SRWM,
2546 2,
2547 ILK_FIFO_LINE_SIZE
2548};
2549
2550static struct intel_watermark_params ironlake_cursor_srwm_info = {
2551 ILK_CURSOR_SR_FIFO,
2552 ILK_CURSOR_MAX_SRWM,
2553 ILK_CURSOR_DFT_SRWM,
2554 2,
2555 ILK_FIFO_LINE_SIZE
2556};
2557
2334/** 2558/**
2335 * intel_calculate_wm - calculate watermark level 2559 * intel_calculate_wm - calculate watermark level
2336 * @clock_in_khz: pixel clock 2560 * @clock_in_khz: pixel clock
@@ -2449,66 +2673,6 @@ static void pineview_disable_cxsr(struct drm_device *dev)
2449 DRM_INFO("Big FIFO is disabled\n"); 2673 DRM_INFO("Big FIFO is disabled\n");
2450} 2674}
2451 2675
2452static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2453 int pixel_size)
2454{
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 u32 reg;
2457 unsigned long wm;
2458 struct cxsr_latency *latency;
2459
2460 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2461 dev_priv->mem_freq);
2462 if (!latency) {
2463 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2464 pineview_disable_cxsr(dev);
2465 return;
2466 }
2467
2468 /* Display SR */
2469 wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2470 latency->display_sr);
2471 reg = I915_READ(DSPFW1);
2472 reg &= 0x7fffff;
2473 reg |= wm << 23;
2474 I915_WRITE(DSPFW1, reg);
2475 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2476
2477 /* cursor SR */
2478 wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2479 latency->cursor_sr);
2480 reg = I915_READ(DSPFW3);
2481 reg &= ~(0x3f << 24);
2482 reg |= (wm & 0x3f) << 24;
2483 I915_WRITE(DSPFW3, reg);
2484
2485 /* Display HPLL off SR */
2486 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2487 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2488 reg = I915_READ(DSPFW3);
2489 reg &= 0xfffffe00;
2490 reg |= wm & 0x1ff;
2491 I915_WRITE(DSPFW3, reg);
2492
2493 /* cursor HPLL off SR */
2494 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2495 latency->cursor_hpll_disable);
2496 reg = I915_READ(DSPFW3);
2497 reg &= ~(0x3f << 16);
2498 reg |= (wm & 0x3f) << 16;
2499 I915_WRITE(DSPFW3, reg);
2500 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2501
2502 /* activate cxsr */
2503 reg = I915_READ(DSPFW3);
2504 reg |= PINEVIEW_SELF_REFRESH_EN;
2505 I915_WRITE(DSPFW3, reg);
2506
2507 DRM_INFO("Big FIFO is enabled\n");
2508
2509 return;
2510}
2511
2512/* 2676/*
2513 * Latency for FIFO fetches is dependent on several factors: 2677 * Latency for FIFO fetches is dependent on several factors:
2514 * - memory configuration (speed, channels) 2678 * - memory configuration (speed, channels)
@@ -2593,6 +2757,71 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
2593 return size; 2757 return size;
2594} 2758}
2595 2759
2760static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2761 int planeb_clock, int sr_hdisplay, int pixel_size)
2762{
2763 struct drm_i915_private *dev_priv = dev->dev_private;
2764 u32 reg;
2765 unsigned long wm;
2766 struct cxsr_latency *latency;
2767 int sr_clock;
2768
2769 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2770 dev_priv->mem_freq);
2771 if (!latency) {
2772 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2773 pineview_disable_cxsr(dev);
2774 return;
2775 }
2776
2777 if (!planea_clock || !planeb_clock) {
2778 sr_clock = planea_clock ? planea_clock : planeb_clock;
2779
2780 /* Display SR */
2781 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2782 pixel_size, latency->display_sr);
2783 reg = I915_READ(DSPFW1);
2784 reg &= ~DSPFW_SR_MASK;
2785 reg |= wm << DSPFW_SR_SHIFT;
2786 I915_WRITE(DSPFW1, reg);
2787 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2788
2789 /* cursor SR */
2790 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2791 pixel_size, latency->cursor_sr);
2792 reg = I915_READ(DSPFW3);
2793 reg &= ~DSPFW_CURSOR_SR_MASK;
2794 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2795 I915_WRITE(DSPFW3, reg);
2796
2797 /* Display HPLL off SR */
2798 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2799 pixel_size, latency->display_hpll_disable);
2800 reg = I915_READ(DSPFW3);
2801 reg &= ~DSPFW_HPLL_SR_MASK;
2802 reg |= wm & DSPFW_HPLL_SR_MASK;
2803 I915_WRITE(DSPFW3, reg);
2804
2805 /* cursor HPLL off SR */
2806 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2807 pixel_size, latency->cursor_hpll_disable);
2808 reg = I915_READ(DSPFW3);
2809 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2810 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2811 I915_WRITE(DSPFW3, reg);
2812 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2813
2814 /* activate cxsr */
2815 reg = I915_READ(DSPFW3);
2816 reg |= PINEVIEW_SELF_REFRESH_EN;
2817 I915_WRITE(DSPFW3, reg);
2818 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2819 } else {
2820 pineview_disable_cxsr(dev);
2821 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2822 }
2823}
2824
2596static void g4x_update_wm(struct drm_device *dev, int planea_clock, 2825static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2597 int planeb_clock, int sr_hdisplay, int pixel_size) 2826 int planeb_clock, int sr_hdisplay, int pixel_size)
2598{ 2827{
@@ -2813,6 +3042,108 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2813 I915_WRITE(FW_BLC, fwater_lo); 3042 I915_WRITE(FW_BLC, fwater_lo);
2814} 3043}
2815 3044
3045#define ILK_LP0_PLANE_LATENCY 700
3046
3047static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3048 int planeb_clock, int sr_hdisplay, int pixel_size)
3049{
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3052 int sr_wm, cursor_wm;
3053 unsigned long line_time_us;
3054 int sr_clock, entries_required;
3055 u32 reg_value;
3056
3057 /* Calculate and update the watermark for plane A */
3058 if (planea_clock) {
3059 entries_required = ((planea_clock / 1000) * pixel_size *
3060 ILK_LP0_PLANE_LATENCY) / 1000;
3061 entries_required = DIV_ROUND_UP(entries_required,
3062 ironlake_display_wm_info.cacheline_size);
3063 planea_wm = entries_required +
3064 ironlake_display_wm_info.guard_size;
3065
3066 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3067 planea_wm = ironlake_display_wm_info.max_wm;
3068
3069 cursora_wm = 16;
3070 reg_value = I915_READ(WM0_PIPEA_ILK);
3071 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3072 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3073 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3074 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3075 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3076 "cursor: %d\n", planea_wm, cursora_wm);
3077 }
3078 /* Calculate and update the watermark for plane B */
3079 if (planeb_clock) {
3080 entries_required = ((planeb_clock / 1000) * pixel_size *
3081 ILK_LP0_PLANE_LATENCY) / 1000;
3082 entries_required = DIV_ROUND_UP(entries_required,
3083 ironlake_display_wm_info.cacheline_size);
3084 planeb_wm = entries_required +
3085 ironlake_display_wm_info.guard_size;
3086
3087 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3088 planeb_wm = ironlake_display_wm_info.max_wm;
3089
3090 cursorb_wm = 16;
3091 reg_value = I915_READ(WM0_PIPEB_ILK);
3092 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3093 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3094 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3095 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3096 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3097 "cursor: %d\n", planeb_wm, cursorb_wm);
3098 }
3099
3100 /*
3101 * Calculate and update the self-refresh watermark only when one
3102 * display plane is used.
3103 */
3104 if (!planea_clock || !planeb_clock) {
3105 int line_count;
3106 /* Read the self-refresh latency. The unit is 0.5us */
3107 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3108
3109 sr_clock = planea_clock ? planea_clock : planeb_clock;
3110 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3111
3112 /* Use ns/us then divide to preserve precision */
3113 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3114 / 1000;
3115
3116 /* calculate the self-refresh watermark for display plane */
3117 entries_required = line_count * sr_hdisplay * pixel_size;
3118 entries_required = DIV_ROUND_UP(entries_required,
3119 ironlake_display_srwm_info.cacheline_size);
3120 sr_wm = entries_required +
3121 ironlake_display_srwm_info.guard_size;
3122
3123 /* calculate the self-refresh watermark for display cursor */
3124 entries_required = line_count * pixel_size * 64;
3125 entries_required = DIV_ROUND_UP(entries_required,
3126 ironlake_cursor_srwm_info.cacheline_size);
3127 cursor_wm = entries_required +
3128 ironlake_cursor_srwm_info.guard_size;
3129
3130 /* configure watermark and enable self-refresh */
3131 reg_value = I915_READ(WM1_LP_ILK);
3132 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3133 WM1_LP_CURSOR_MASK);
3134 reg_value |= WM1_LP_SR_EN |
3135 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3136 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3137
3138 I915_WRITE(WM1_LP_ILK, reg_value);
3139 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3140 "cursor %d\n", sr_wm, cursor_wm);
3141
3142 } else {
3143 /* Turn off self refresh if both pipes are enabled */
3144 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3145 }
3146}
2816/** 3147/**
2817 * intel_update_watermarks - update FIFO watermark values based on current modes 3148 * intel_update_watermarks - update FIFO watermark values based on current modes
2818 * 3149 *
@@ -2882,12 +3213,6 @@ static void intel_update_watermarks(struct drm_device *dev)
2882 if (enabled <= 0) 3213 if (enabled <= 0)
2883 return; 3214 return;
2884 3215
2885 /* Single plane configs can enable self refresh */
2886 if (enabled == 1 && IS_PINEVIEW(dev))
2887 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2888 else if (IS_PINEVIEW(dev))
2889 pineview_disable_cxsr(dev);
2890
2891 dev_priv->display.update_wm(dev, planea_clock, planeb_clock, 3216 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2892 sr_hdisplay, pixel_size); 3217 sr_hdisplay, pixel_size);
2893} 3218}
@@ -2924,7 +3249,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2924 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3249 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2925 bool is_edp = false; 3250 bool is_edp = false;
2926 struct drm_mode_config *mode_config = &dev->mode_config; 3251 struct drm_mode_config *mode_config = &dev->mode_config;
2927 struct drm_connector *connector; 3252 struct drm_encoder *encoder;
3253 struct intel_encoder *intel_encoder = NULL;
2928 const intel_limit_t *limit; 3254 const intel_limit_t *limit;
2929 int ret; 3255 int ret;
2930 struct fdi_m_n m_n = {0}; 3256 struct fdi_m_n m_n = {0};
@@ -2935,6 +3261,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2935 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0; 3261 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2936 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; 3262 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2937 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; 3263 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3264 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3265 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
2938 int lvds_reg = LVDS; 3266 int lvds_reg = LVDS;
2939 u32 temp; 3267 u32 temp;
2940 int sdvo_pixel_multiply; 3268 int sdvo_pixel_multiply;
@@ -2942,12 +3270,13 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2942 3270
2943 drm_vblank_pre_modeset(dev, pipe); 3271 drm_vblank_pre_modeset(dev, pipe);
2944 3272
2945 list_for_each_entry(connector, &mode_config->connector_list, head) { 3273 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2946 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2947 3274
2948 if (!connector->encoder || connector->encoder->crtc != crtc) 3275 if (!encoder || encoder->crtc != crtc)
2949 continue; 3276 continue;
2950 3277
3278 intel_encoder = enc_to_intel_encoder(encoder);
3279
2951 switch (intel_encoder->type) { 3280 switch (intel_encoder->type) {
2952 case INTEL_OUTPUT_LVDS: 3281 case INTEL_OUTPUT_LVDS:
2953 is_lvds = true; 3282 is_lvds = true;
@@ -3043,14 +3372,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3043 3372
3044 /* FDI link */ 3373 /* FDI link */
3045 if (HAS_PCH_SPLIT(dev)) { 3374 if (HAS_PCH_SPLIT(dev)) {
3046 int lane, link_bw, bpp; 3375 int lane = 0, link_bw, bpp;
3047 /* eDP doesn't require FDI link, so just set DP M/N 3376 /* eDP doesn't require FDI link, so just set DP M/N
3048 according to current link config */ 3377 according to current link config */
3049 if (is_edp) { 3378 if (is_edp) {
3050 struct drm_connector *edp;
3051 target_clock = mode->clock; 3379 target_clock = mode->clock;
3052 edp = intel_pipe_get_connector(crtc); 3380 intel_edp_link_config(intel_encoder,
3053 intel_edp_link_config(to_intel_encoder(edp),
3054 &lane, &link_bw); 3381 &lane, &link_bw);
3055 } else { 3382 } else {
3056 /* DP over FDI requires target mode clock 3383 /* DP over FDI requires target mode clock
@@ -3059,7 +3386,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3059 target_clock = mode->clock; 3386 target_clock = mode->clock;
3060 else 3387 else
3061 target_clock = adjusted_mode->clock; 3388 target_clock = adjusted_mode->clock;
3062 lane = 4;
3063 link_bw = 270000; 3389 link_bw = 270000;
3064 } 3390 }
3065 3391
@@ -3111,6 +3437,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3111 bpp = 24; 3437 bpp = 24;
3112 } 3438 }
3113 3439
3440 if (!lane) {
3441 /*
3442 * Account for spread spectrum to avoid
3443 * oversubscribing the link. Max center spread
3444 * is 2.5%; use 5% for safety's sake.
3445 */
3446 u32 bps = target_clock * bpp * 21 / 20;
3447 lane = bps / (link_bw * 8) + 1;
3448 }
3449
3450 intel_crtc->fdi_lanes = lane;
3451
3114 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); 3452 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3115 } 3453 }
3116 3454
@@ -3265,11 +3603,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3265 pipeconf &= ~PIPEACONF_DOUBLE_WIDE; 3603 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3266 } 3604 }
3267 3605
3268 dspcntr |= DISPLAY_PLANE_ENABLE;
3269 pipeconf |= PIPEACONF_ENABLE;
3270 dpll |= DPLL_VCO_ENABLE;
3271
3272
3273 /* Disable the panel fitter if it was on our pipe */ 3606 /* Disable the panel fitter if it was on our pipe */
3274 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe) 3607 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3275 I915_WRITE(PFIT_CONTROL, 0); 3608 I915_WRITE(PFIT_CONTROL, 0);
@@ -3292,6 +3625,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3292 udelay(150); 3625 udelay(150);
3293 } 3626 }
3294 3627
3628 /* enable transcoder DPLL */
3629 if (HAS_PCH_CPT(dev)) {
3630 temp = I915_READ(PCH_DPLL_SEL);
3631 if (trans_dpll_sel == 0)
3632 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3633 else
3634 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3635 I915_WRITE(PCH_DPLL_SEL, temp);
3636 I915_READ(PCH_DPLL_SEL);
3637 udelay(150);
3638 }
3639
3295 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 3640 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3296 * This is an exception to the general rule that mode_set doesn't turn 3641 * This is an exception to the general rule that mode_set doesn't turn
3297 * things on. 3642 * things on.
@@ -3303,7 +3648,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3303 lvds_reg = PCH_LVDS; 3648 lvds_reg = PCH_LVDS;
3304 3649
3305 lvds = I915_READ(lvds_reg); 3650 lvds = I915_READ(lvds_reg);
3306 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; 3651 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3652 if (pipe == 1) {
3653 if (HAS_PCH_CPT(dev))
3654 lvds |= PORT_TRANS_B_SEL_CPT;
3655 else
3656 lvds |= LVDS_PIPEB_SELECT;
3657 } else {
3658 if (HAS_PCH_CPT(dev))
3659 lvds &= ~PORT_TRANS_SEL_MASK;
3660 else
3661 lvds &= ~LVDS_PIPEB_SELECT;
3662 }
3307 /* set the corresponsding LVDS_BORDER bit */ 3663 /* set the corresponsding LVDS_BORDER bit */
3308 lvds |= dev_priv->lvds_border_bits; 3664 lvds |= dev_priv->lvds_border_bits;
3309 /* Set the B0-B3 data pairs corresponding to whether we're going to 3665 /* Set the B0-B3 data pairs corresponding to whether we're going to
@@ -3337,6 +3693,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3337 } 3693 }
3338 if (is_dp) 3694 if (is_dp)
3339 intel_dp_set_m_n(crtc, mode, adjusted_mode); 3695 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3696 else if (HAS_PCH_SPLIT(dev)) {
3697 /* For non-DP output, clear any trans DP clock recovery setting.*/
3698 if (pipe == 0) {
3699 I915_WRITE(TRANSA_DATA_M1, 0);
3700 I915_WRITE(TRANSA_DATA_N1, 0);
3701 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3702 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3703 } else {
3704 I915_WRITE(TRANSB_DATA_M1, 0);
3705 I915_WRITE(TRANSB_DATA_N1, 0);
3706 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3707 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3708 }
3709 }
3340 3710
3341 if (!is_edp) { 3711 if (!is_edp) {
3342 I915_WRITE(fp_reg, fp); 3712 I915_WRITE(fp_reg, fp);
@@ -3411,6 +3781,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3411 /* enable FDI RX PLL too */ 3781 /* enable FDI RX PLL too */
3412 temp = I915_READ(fdi_rx_reg); 3782 temp = I915_READ(fdi_rx_reg);
3413 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); 3783 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3784 I915_READ(fdi_rx_reg);
3785 udelay(200);
3786
3787 /* enable FDI TX PLL too */
3788 temp = I915_READ(fdi_tx_reg);
3789 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3790 I915_READ(fdi_tx_reg);
3791
3792 /* enable FDI RX PCDCLK */
3793 temp = I915_READ(fdi_rx_reg);
3794 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3795 I915_READ(fdi_rx_reg);
3414 udelay(200); 3796 udelay(200);
3415 } 3797 }
3416 } 3798 }
@@ -3671,6 +4053,7 @@ static struct drm_display_mode load_detect_mode = {
3671}; 4053};
3672 4054
3673struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 4055struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4056 struct drm_connector *connector,
3674 struct drm_display_mode *mode, 4057 struct drm_display_mode *mode,
3675 int *dpms_mode) 4058 int *dpms_mode)
3676{ 4059{
@@ -3729,7 +4112,7 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3729 } 4112 }
3730 4113
3731 encoder->crtc = crtc; 4114 encoder->crtc = crtc;
3732 intel_encoder->base.encoder = encoder; 4115 connector->encoder = encoder;
3733 intel_encoder->load_detect_temp = true; 4116 intel_encoder->load_detect_temp = true;
3734 4117
3735 intel_crtc = to_intel_crtc(crtc); 4118 intel_crtc = to_intel_crtc(crtc);
@@ -3755,7 +4138,8 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3755 return crtc; 4138 return crtc;
3756} 4139}
3757 4140
3758void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, int dpms_mode) 4141void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4142 struct drm_connector *connector, int dpms_mode)
3759{ 4143{
3760 struct drm_encoder *encoder = &intel_encoder->enc; 4144 struct drm_encoder *encoder = &intel_encoder->enc;
3761 struct drm_device *dev = encoder->dev; 4145 struct drm_device *dev = encoder->dev;
@@ -3765,7 +4149,7 @@ void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, int dpm
3765 4149
3766 if (intel_encoder->load_detect_temp) { 4150 if (intel_encoder->load_detect_temp) {
3767 encoder->crtc = NULL; 4151 encoder->crtc = NULL;
3768 intel_encoder->base.encoder = NULL; 4152 connector->encoder = NULL;
3769 intel_encoder->load_detect_temp = false; 4153 intel_encoder->load_detect_temp = false;
3770 crtc->enabled = drm_helper_crtc_in_use(crtc); 4154 crtc->enabled = drm_helper_crtc_in_use(crtc);
3771 drm_helper_disable_unused_functions(dev); 4155 drm_helper_disable_unused_functions(dev);
@@ -4392,14 +4776,14 @@ struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4392 return crtc; 4776 return crtc;
4393} 4777}
4394 4778
4395static int intel_connector_clones(struct drm_device *dev, int type_mask) 4779static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4396{ 4780{
4397 int index_mask = 0; 4781 int index_mask = 0;
4398 struct drm_connector *connector; 4782 struct drm_encoder *encoder;
4399 int entry = 0; 4783 int entry = 0;
4400 4784
4401 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 4785 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4402 struct intel_encoder *intel_encoder = to_intel_encoder(connector); 4786 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4403 if (type_mask & intel_encoder->clone_mask) 4787 if (type_mask & intel_encoder->clone_mask)
4404 index_mask |= (1 << entry); 4788 index_mask |= (1 << entry);
4405 entry++; 4789 entry++;
@@ -4411,7 +4795,7 @@ static int intel_connector_clones(struct drm_device *dev, int type_mask)
4411static void intel_setup_outputs(struct drm_device *dev) 4795static void intel_setup_outputs(struct drm_device *dev)
4412{ 4796{
4413 struct drm_i915_private *dev_priv = dev->dev_private; 4797 struct drm_i915_private *dev_priv = dev->dev_private;
4414 struct drm_connector *connector; 4798 struct drm_encoder *encoder;
4415 4799
4416 intel_crt_init(dev); 4800 intel_crt_init(dev);
4417 4801
@@ -4426,9 +4810,8 @@ static void intel_setup_outputs(struct drm_device *dev)
4426 intel_dp_init(dev, DP_A); 4810 intel_dp_init(dev, DP_A);
4427 4811
4428 if (I915_READ(HDMIB) & PORT_DETECTED) { 4812 if (I915_READ(HDMIB) & PORT_DETECTED) {
4429 /* check SDVOB */ 4813 /* PCH SDVOB multiplex with HDMIB */
4430 /* found = intel_sdvo_init(dev, HDMIB); */ 4814 found = intel_sdvo_init(dev, PCH_SDVOB);
4431 found = 0;
4432 if (!found) 4815 if (!found)
4433 intel_hdmi_init(dev, HDMIB); 4816 intel_hdmi_init(dev, HDMIB);
4434 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 4817 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
@@ -4494,12 +4877,11 @@ static void intel_setup_outputs(struct drm_device *dev)
4494 if (SUPPORTS_TV(dev)) 4877 if (SUPPORTS_TV(dev))
4495 intel_tv_init(dev); 4878 intel_tv_init(dev);
4496 4879
4497 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 4880 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4498 struct intel_encoder *intel_encoder = to_intel_encoder(connector); 4881 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4499 struct drm_encoder *encoder = &intel_encoder->enc;
4500 4882
4501 encoder->possible_crtcs = intel_encoder->crtc_mask; 4883 encoder->possible_crtcs = intel_encoder->crtc_mask;
4502 encoder->possible_clones = intel_connector_clones(dev, 4884 encoder->possible_clones = intel_encoder_clones(dev,
4503 intel_encoder->clone_mask); 4885 intel_encoder->clone_mask);
4504 } 4886 }
4505} 4887}
@@ -4732,6 +5114,25 @@ void intel_init_clock_gating(struct drm_device *dev)
4732 } 5114 }
4733 5115
4734 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); 5116 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5117
5118 /*
5119 * According to the spec the following bits should be set in
5120 * order to enable memory self-refresh
5121 * The bit 22/21 of 0x42004
5122 * The bit 5 of 0x42020
5123 * The bit 15 of 0x45000
5124 */
5125 if (IS_IRONLAKE(dev)) {
5126 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5127 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5128 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5129 I915_WRITE(ILK_DSPCLK_GATE,
5130 (I915_READ(ILK_DSPCLK_GATE) |
5131 ILK_DPARB_CLK_GATE));
5132 I915_WRITE(DISP_ARB_CTL,
5133 (I915_READ(DISP_ARB_CTL) |
5134 DISP_FBC_WM_DIS));
5135 }
4735 return; 5136 return;
4736 } else if (IS_G4X(dev)) { 5137 } else if (IS_G4X(dev)) {
4737 uint32_t dspclk_gate; 5138 uint32_t dspclk_gate;
@@ -4847,9 +5248,31 @@ static void intel_init_display(struct drm_device *dev)
4847 i830_get_display_clock_speed; 5248 i830_get_display_clock_speed;
4848 5249
4849 /* For FIFO watermark updates */ 5250 /* For FIFO watermark updates */
4850 if (HAS_PCH_SPLIT(dev)) 5251 if (HAS_PCH_SPLIT(dev)) {
4851 dev_priv->display.update_wm = NULL; 5252 if (IS_IRONLAKE(dev)) {
4852 else if (IS_G4X(dev)) 5253 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5254 dev_priv->display.update_wm = ironlake_update_wm;
5255 else {
5256 DRM_DEBUG_KMS("Failed to get proper latency. "
5257 "Disable CxSR\n");
5258 dev_priv->display.update_wm = NULL;
5259 }
5260 } else
5261 dev_priv->display.update_wm = NULL;
5262 } else if (IS_PINEVIEW(dev)) {
5263 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5264 dev_priv->fsb_freq,
5265 dev_priv->mem_freq)) {
5266 DRM_INFO("failed to find known CxSR latency "
5267 "(found fsb freq %d, mem freq %d), "
5268 "disabling CxSR\n",
5269 dev_priv->fsb_freq, dev_priv->mem_freq);
5270 /* Disable CxSR and never update its watermark again */
5271 pineview_disable_cxsr(dev);
5272 dev_priv->display.update_wm = NULL;
5273 } else
5274 dev_priv->display.update_wm = pineview_update_wm;
5275 } else if (IS_G4X(dev))
4853 dev_priv->display.update_wm = g4x_update_wm; 5276 dev_priv->display.update_wm = g4x_update_wm;
4854 else if (IS_I965G(dev)) 5277 else if (IS_I965G(dev))
4855 dev_priv->display.update_wm = i965_update_wm; 5278 dev_priv->display.update_wm = i965_update_wm;
@@ -4922,13 +5345,6 @@ void intel_modeset_init(struct drm_device *dev)
4922 (unsigned long)dev); 5345 (unsigned long)dev);
4923 5346
4924 intel_setup_overlay(dev); 5347 intel_setup_overlay(dev);
4925
4926 if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4927 dev_priv->fsb_freq,
4928 dev_priv->mem_freq))
4929 DRM_INFO("failed to find known CxSR latency "
4930 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4931 dev_priv->fsb_freq, dev_priv->mem_freq);
4932} 5348}
4933 5349
4934void intel_modeset_cleanup(struct drm_device *dev) 5350void intel_modeset_cleanup(struct drm_device *dev)
@@ -4973,14 +5389,29 @@ void intel_modeset_cleanup(struct drm_device *dev)
4973} 5389}
4974 5390
4975 5391
4976/* current intel driver doesn't take advantage of encoders 5392/*
4977 always give back the encoder for the connector 5393 * Return which encoder is currently attached for connector.
4978*/ 5394 */
4979struct drm_encoder *intel_best_encoder(struct drm_connector *connector) 5395struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
4980{ 5396{
4981 struct intel_encoder *intel_encoder = to_intel_encoder(connector); 5397 struct drm_mode_object *obj;
5398 struct drm_encoder *encoder;
5399 int i;
5400
5401 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5402 if (connector->encoder_ids[i] == 0)
5403 break;
4982 5404
4983 return &intel_encoder->enc; 5405 obj = drm_mode_object_find(connector->dev,
5406 connector->encoder_ids[i],
5407 DRM_MODE_OBJECT_ENCODER);
5408 if (!obj)
5409 continue;
5410
5411 encoder = obj_to_encoder(obj);
5412 return encoder;
5413 }
5414 return NULL;
4984} 5415}
4985 5416
4986/* 5417/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 09:28:32 -0400