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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c4391
1 files changed, 1083 insertions, 3308 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1b1cf3b3ff51..e0aa064def31 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -24,7 +24,7 @@
24 * Eric Anholt <eric@anholt.net> 24 * Eric Anholt <eric@anholt.net>
25 */ 25 */
26 26
27#include <linux/cpufreq.h> 27#include <linux/dmi.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/input.h> 29#include <linux/input.h>
30#include <linux/i2c.h> 30#include <linux/i2c.h>
@@ -44,7 +44,6 @@
44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45 45
46bool intel_pipe_has_type(struct drm_crtc *crtc, int type); 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47static void intel_update_watermarks(struct drm_device *dev);
48static void intel_increase_pllclock(struct drm_crtc *crtc); 47static void intel_increase_pllclock(struct drm_crtc *crtc);
49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50 49
@@ -360,6 +359,88 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
360 .find_pll = intel_find_pll_ironlake_dp, 359 .find_pll = intel_find_pll_ironlake_dp,
361}; 360};
362 361
362u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363{
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385}
386
387static void vlv_init_dpio(struct drm_device *dev)
388{
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396}
397
398static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399{
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402}
403
404static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414};
415
416static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418{
419 unsigned int val;
420
421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442}
443
363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, 444static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk) 445 int refclk)
365{ 446{
@@ -368,8 +449,7 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
368 const intel_limit_t *limit; 449 const intel_limit_t *limit;
369 450
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == 452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */ 453 /* LVDS dual channel */
374 if (refclk == 100000) 454 if (refclk == 100000)
375 limit = &intel_limits_ironlake_dual_lvds_100m; 455 limit = &intel_limits_ironlake_dual_lvds_100m;
@@ -397,8 +477,7 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
397 const intel_limit_t *limit; 477 const intel_limit_t *limit;
398 478
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 480 if (is_dual_link_lvds(dev_priv, LVDS))
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */ 481 /* LVDS with dual channel */
403 limit = &intel_limits_g4x_dual_channel_lvds; 482 limit = &intel_limits_g4x_dual_channel_lvds;
404 else 483 else
@@ -536,8 +615,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
536 * reliably set up different single/dual channel state, if we 615 * reliably set up different single/dual channel state, if we
537 * even can. 616 * even can.
538 */ 617 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 618 if (is_dual_link_lvds(dev_priv, LVDS))
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast; 619 clock.p2 = limit->p2.p2_fast;
542 else 620 else
543 clock.p2 = limit->p2.p2_slow; 621 clock.p2 = limit->p2.p2_slow;
@@ -706,6 +784,17 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
706 return true; 784 return true;
707} 785}
708 786
787static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 frame, frame_reg = PIPEFRAME(pipe);
791
792 frame = I915_READ(frame_reg);
793
794 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
709/** 798/**
710 * intel_wait_for_vblank - wait for vblank on a given pipe 799 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device 800 * @dev: drm device
@@ -719,6 +808,11 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
719 struct drm_i915_private *dev_priv = dev->dev_private; 808 struct drm_i915_private *dev_priv = dev->dev_private;
720 int pipestat_reg = PIPESTAT(pipe); 809 int pipestat_reg = PIPESTAT(pipe);
721 810
811 if (INTEL_INFO(dev)->gen >= 5) {
812 ironlake_wait_for_vblank(dev, pipe);
813 return;
814 }
815
722 /* Clear existing vblank status. Note this will clear any other 816 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well. 817 * sticky status fields as well.
724 * 818 *
@@ -771,15 +865,20 @@ void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
771 100)) 865 100))
772 DRM_DEBUG_KMS("pipe_off wait timed out\n"); 866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else { 867 } else {
774 u32 last_line; 868 u32 last_line, line_mask;
775 int reg = PIPEDSL(pipe); 869 int reg = PIPEDSL(pipe);
776 unsigned long timeout = jiffies + msecs_to_jiffies(100); 870 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777 871
872 if (IS_GEN2(dev))
873 line_mask = DSL_LINEMASK_GEN2;
874 else
875 line_mask = DSL_LINEMASK_GEN3;
876
778 /* Wait for the display line to settle */ 877 /* Wait for the display line to settle */
779 do { 878 do {
780 last_line = I915_READ(reg) & DSL_LINEMASK; 879 last_line = I915_READ(reg) & line_mask;
781 mdelay(5); 880 mdelay(5);
782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && 881 } while (((I915_READ(reg) & line_mask) != last_line) &&
783 time_after(timeout, jiffies)); 882 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout)) 883 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n"); 884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
@@ -811,34 +910,49 @@ static void assert_pll(struct drm_i915_private *dev_priv,
811 910
812/* For ILK+ */ 911/* For ILK+ */
813static void assert_pch_pll(struct drm_i915_private *dev_priv, 912static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state) 913 struct intel_pch_pll *pll,
914 struct intel_crtc *crtc,
915 bool state)
815{ 916{
816 int reg;
817 u32 val; 917 u32 val;
818 bool cur_state; 918 bool cur_state;
819 919
820 if (HAS_PCH_CPT(dev_priv->dev)) { 920 if (HAS_PCH_LPT(dev_priv->dev)) {
821 u32 pch_dpll; 921 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
822 922 return;
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 } 923 }
832 924
833 reg = PCH_DPLL(pipe); 925 if (WARN (!pll,
834 val = I915_READ(reg); 926 "asserting PCH PLL %s with no PLL\n", state_string(state)))
927 return;
928
929 val = I915_READ(pll->pll_reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE); 930 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state, 931 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n", 932 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
838 state_string(state), state_string(cur_state)); 933 pll->pll_reg, state_string(state), state_string(cur_state), val);
934
935 /* Make sure the selected PLL is correctly attached to the transcoder */
936 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
937 u32 pch_dpll;
938
939 pch_dpll = I915_READ(PCH_DPLL_SEL);
940 cur_state = pll->pll_reg == _PCH_DPLL_B;
941 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
942 "PLL[%d] not attached to this transcoder %d: %08x\n",
943 cur_state, crtc->pipe, pch_dpll)) {
944 cur_state = !!(val >> (4*crtc->pipe + 3));
945 WARN(cur_state != state,
946 "PLL[%d] not %s on this transcoder %d: %08x\n",
947 pll->pll_reg == _PCH_DPLL_B,
948 state_string(state),
949 crtc->pipe,
950 val);
951 }
952 }
839} 953}
840#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) 954#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
841#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) 955#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
842 956
843static void assert_fdi_tx(struct drm_i915_private *dev_priv, 957static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state) 958 enum pipe pipe, bool state)
@@ -847,9 +961,16 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
847 u32 val; 961 u32 val;
848 bool cur_state; 962 bool cur_state;
849 963
850 reg = FDI_TX_CTL(pipe); 964 if (IS_HASWELL(dev_priv->dev)) {
851 val = I915_READ(reg); 965 /* On Haswell, DDI is used instead of FDI_TX_CTL */
852 cur_state = !!(val & FDI_TX_ENABLE); 966 reg = DDI_FUNC_CTL(pipe);
967 val = I915_READ(reg);
968 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
969 } else {
970 reg = FDI_TX_CTL(pipe);
971 val = I915_READ(reg);
972 cur_state = !!(val & FDI_TX_ENABLE);
973 }
853 WARN(cur_state != state, 974 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n", 975 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state)); 976 state_string(state), state_string(cur_state));
@@ -864,9 +985,14 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
864 u32 val; 985 u32 val;
865 bool cur_state; 986 bool cur_state;
866 987
867 reg = FDI_RX_CTL(pipe); 988 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
868 val = I915_READ(reg); 989 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
869 cur_state = !!(val & FDI_RX_ENABLE); 990 return;
991 } else {
992 reg = FDI_RX_CTL(pipe);
993 val = I915_READ(reg);
994 cur_state = !!(val & FDI_RX_ENABLE);
995 }
870 WARN(cur_state != state, 996 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n", 997 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state)); 998 state_string(state), state_string(cur_state));
@@ -884,6 +1010,10 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
884 if (dev_priv->info->gen == 5) 1010 if (dev_priv->info->gen == 5)
885 return; 1011 return;
886 1012
1013 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1014 if (IS_HASWELL(dev_priv->dev))
1015 return;
1016
887 reg = FDI_TX_CTL(pipe); 1017 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg); 1018 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); 1019 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
@@ -895,6 +1025,10 @@ static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
895 int reg; 1025 int reg;
896 u32 val; 1026 u32 val;
897 1027
1028 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1029 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1030 return;
1031 }
898 reg = FDI_RX_CTL(pipe); 1032 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg); 1033 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); 1034 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
@@ -1000,6 +1134,11 @@ static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1000 u32 val; 1134 u32 val;
1001 bool enabled; 1135 bool enabled;
1002 1136
1137 if (HAS_PCH_LPT(dev_priv->dev)) {
1138 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1139 return;
1140 }
1141
1003 val = I915_READ(PCH_DREF_CONTROL); 1142 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | 1143 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK)); 1144 DREF_SUPERSPREAD_SOURCE_MASK));
@@ -1198,6 +1337,69 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1198 POSTING_READ(reg); 1337 POSTING_READ(reg);
1199} 1338}
1200 1339
1340/* SBI access */
1341static void
1342intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1343{
1344 unsigned long flags;
1345
1346 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1347 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1348 100)) {
1349 DRM_ERROR("timeout waiting for SBI to become ready\n");
1350 goto out_unlock;
1351 }
1352
1353 I915_WRITE(SBI_ADDR,
1354 (reg << 16));
1355 I915_WRITE(SBI_DATA,
1356 value);
1357 I915_WRITE(SBI_CTL_STAT,
1358 SBI_BUSY |
1359 SBI_CTL_OP_CRWR);
1360
1361 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1362 100)) {
1363 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1364 goto out_unlock;
1365 }
1366
1367out_unlock:
1368 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1369}
1370
1371static u32
1372intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1373{
1374 unsigned long flags;
1375 u32 value;
1376
1377 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1378 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1379 100)) {
1380 DRM_ERROR("timeout waiting for SBI to become ready\n");
1381 goto out_unlock;
1382 }
1383
1384 I915_WRITE(SBI_ADDR,
1385 (reg << 16));
1386 I915_WRITE(SBI_CTL_STAT,
1387 SBI_BUSY |
1388 SBI_CTL_OP_CRRD);
1389
1390 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1391 100)) {
1392 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1393 goto out_unlock;
1394 }
1395
1396 value = I915_READ(SBI_DATA);
1397
1398out_unlock:
1399 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1400 return value;
1401}
1402
1201/** 1403/**
1202 * intel_enable_pch_pll - enable PCH PLL 1404 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure 1405 * @dev_priv: i915 private structure
@@ -1206,60 +1408,88 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it 1408 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock. 1409 * drives the transcoder clock.
1208 */ 1410 */
1209static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, 1411static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1210 enum pipe pipe)
1211{ 1412{
1413 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1414 struct intel_pch_pll *pll;
1212 int reg; 1415 int reg;
1213 u32 val; 1416 u32 val;
1214 1417
1215 if (pipe > 1) 1418 /* PCH PLLs only available on ILK, SNB and IVB */
1419 BUG_ON(dev_priv->info->gen < 5);
1420 pll = intel_crtc->pch_pll;
1421 if (pll == NULL)
1422 return;
1423
1424 if (WARN_ON(pll->refcount == 0))
1216 return; 1425 return;
1217 1426
1218 /* PCH only available on ILK+ */ 1427 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1219 BUG_ON(dev_priv->info->gen < 5); 1428 pll->pll_reg, pll->active, pll->on,
1429 intel_crtc->base.base.id);
1220 1430
1221 /* PCH refclock must be enabled first */ 1431 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv); 1432 assert_pch_refclk_enabled(dev_priv);
1223 1433
1224 reg = PCH_DPLL(pipe); 1434 if (pll->active++ && pll->on) {
1435 assert_pch_pll_enabled(dev_priv, pll, NULL);
1436 return;
1437 }
1438
1439 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1440
1441 reg = pll->pll_reg;
1225 val = I915_READ(reg); 1442 val = I915_READ(reg);
1226 val |= DPLL_VCO_ENABLE; 1443 val |= DPLL_VCO_ENABLE;
1227 I915_WRITE(reg, val); 1444 I915_WRITE(reg, val);
1228 POSTING_READ(reg); 1445 POSTING_READ(reg);
1229 udelay(200); 1446 udelay(200);
1447
1448 pll->on = true;
1230} 1449}
1231 1450
1232static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, 1451static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1233 enum pipe pipe)
1234{ 1452{
1453 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1454 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1235 int reg; 1455 int reg;
1236 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL, 1456 u32 val;
1237 pll_sel = TRANSC_DPLL_ENABLE;
1238
1239 if (pipe > 1)
1240 return;
1241 1457
1242 /* PCH only available on ILK+ */ 1458 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5); 1459 BUG_ON(dev_priv->info->gen < 5);
1460 if (pll == NULL)
1461 return;
1244 1462
1245 /* Make sure transcoder isn't still depending on us */ 1463 if (WARN_ON(pll->refcount == 0))
1246 assert_transcoder_disabled(dev_priv, pipe); 1464 return;
1247 1465
1248 if (pipe == 0) 1466 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1249 pll_sel |= TRANSC_DPLLA_SEL; 1467 pll->pll_reg, pll->active, pll->on,
1250 else if (pipe == 1) 1468 intel_crtc->base.base.id);
1251 pll_sel |= TRANSC_DPLLB_SEL;
1252 1469
1470 if (WARN_ON(pll->active == 0)) {
1471 assert_pch_pll_disabled(dev_priv, pll, NULL);
1472 return;
1473 }
1253 1474
1254 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) 1475 if (--pll->active) {
1476 assert_pch_pll_enabled(dev_priv, pll, NULL);
1255 return; 1477 return;
1478 }
1479
1480 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1256 1481
1257 reg = PCH_DPLL(pipe); 1482 /* Make sure transcoder isn't still depending on us */
1483 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1484
1485 reg = pll->pll_reg;
1258 val = I915_READ(reg); 1486 val = I915_READ(reg);
1259 val &= ~DPLL_VCO_ENABLE; 1487 val &= ~DPLL_VCO_ENABLE;
1260 I915_WRITE(reg, val); 1488 I915_WRITE(reg, val);
1261 POSTING_READ(reg); 1489 POSTING_READ(reg);
1262 udelay(200); 1490 udelay(200);
1491
1492 pll->on = false;
1263} 1493}
1264 1494
1265static void intel_enable_transcoder(struct drm_i915_private *dev_priv, 1495static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
@@ -1273,12 +1503,18 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1273 BUG_ON(dev_priv->info->gen < 5); 1503 BUG_ON(dev_priv->info->gen < 5);
1274 1504
1275 /* Make sure PCH DPLL is enabled */ 1505 /* Make sure PCH DPLL is enabled */
1276 assert_pch_pll_enabled(dev_priv, pipe); 1506 assert_pch_pll_enabled(dev_priv,
1507 to_intel_crtc(crtc)->pch_pll,
1508 to_intel_crtc(crtc));
1277 1509
1278 /* FDI must be feeding us bits for PCH ports */ 1510 /* FDI must be feeding us bits for PCH ports */
1279 assert_fdi_tx_enabled(dev_priv, pipe); 1511 assert_fdi_tx_enabled(dev_priv, pipe);
1280 assert_fdi_rx_enabled(dev_priv, pipe); 1512 assert_fdi_rx_enabled(dev_priv, pipe);
1281 1513
1514 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1515 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1516 return;
1517 }
1282 reg = TRANSCONF(pipe); 1518 reg = TRANSCONF(pipe);
1283 val = I915_READ(reg); 1519 val = I915_READ(reg);
1284 pipeconf_val = I915_READ(PIPECONF(pipe)); 1520 pipeconf_val = I915_READ(PIPECONF(pipe));
@@ -1415,7 +1651,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1415 * Plane regs are double buffered, going from enabled->disabled needs a 1651 * Plane regs are double buffered, going from enabled->disabled needs a
1416 * trigger in order to latch. The display address reg provides this. 1652 * trigger in order to latch. The display address reg provides this.
1417 */ 1653 */
1418static void intel_flush_display_plane(struct drm_i915_private *dev_priv, 1654void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1419 enum plane plane) 1655 enum plane plane)
1420{ 1656{
1421 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); 1657 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
@@ -1526,490 +1762,6 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1526 disable_pch_hdmi(dev_priv, pipe, HDMID); 1762 disable_pch_hdmi(dev_priv, pipe, HDMID);
1527} 1763}
1528 1764
1529static void i8xx_disable_fbc(struct drm_device *dev)
1530{
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 u32 fbc_ctl;
1533
1534 /* Disable compression */
1535 fbc_ctl = I915_READ(FBC_CONTROL);
1536 if ((fbc_ctl & FBC_CTL_EN) == 0)
1537 return;
1538
1539 fbc_ctl &= ~FBC_CTL_EN;
1540 I915_WRITE(FBC_CONTROL, fbc_ctl);
1541
1542 /* Wait for compressing bit to clear */
1543 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1544 DRM_DEBUG_KMS("FBC idle timed out\n");
1545 return;
1546 }
1547
1548 DRM_DEBUG_KMS("disabled FBC\n");
1549}
1550
1551static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552{
1553 struct drm_device *dev = crtc->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_framebuffer *fb = crtc->fb;
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557 struct drm_i915_gem_object *obj = intel_fb->obj;
1558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559 int cfb_pitch;
1560 int plane, i;
1561 u32 fbc_ctl, fbc_ctl2;
1562
1563 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1564 if (fb->pitches[0] < cfb_pitch)
1565 cfb_pitch = fb->pitches[0];
1566
1567 /* FBC_CTL wants 64B units */
1568 cfb_pitch = (cfb_pitch / 64) - 1;
1569 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1570
1571 /* Clear old tags */
1572 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1573 I915_WRITE(FBC_TAG + (i * 4), 0);
1574
1575 /* Set it up... */
1576 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1577 fbc_ctl2 |= plane;
1578 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1579 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1580
1581 /* enable it... */
1582 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1583 if (IS_I945GM(dev))
1584 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1585 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1586 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1587 fbc_ctl |= obj->fence_reg;
1588 I915_WRITE(FBC_CONTROL, fbc_ctl);
1589
1590 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1591 cfb_pitch, crtc->y, intel_crtc->plane);
1592}
1593
1594static bool i8xx_fbc_enabled(struct drm_device *dev)
1595{
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1599}
1600
1601static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602{
1603 struct drm_device *dev = crtc->dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct drm_framebuffer *fb = crtc->fb;
1606 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1607 struct drm_i915_gem_object *obj = intel_fb->obj;
1608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1609 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1610 unsigned long stall_watermark = 200;
1611 u32 dpfc_ctl;
1612
1613 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1614 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1615 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1616
1617 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1618 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1619 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1620 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1621
1622 /* enable it... */
1623 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1624
1625 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1626}
1627
1628static void g4x_disable_fbc(struct drm_device *dev)
1629{
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 u32 dpfc_ctl;
1632
1633 /* Disable compression */
1634 dpfc_ctl = I915_READ(DPFC_CONTROL);
1635 if (dpfc_ctl & DPFC_CTL_EN) {
1636 dpfc_ctl &= ~DPFC_CTL_EN;
1637 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1638
1639 DRM_DEBUG_KMS("disabled FBC\n");
1640 }
1641}
1642
1643static bool g4x_fbc_enabled(struct drm_device *dev)
1644{
1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1648}
1649
1650static void sandybridge_blit_fbc_update(struct drm_device *dev)
1651{
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 u32 blt_ecoskpd;
1654
1655 /* Make sure blitter notifies FBC of writes */
1656 gen6_gt_force_wake_get(dev_priv);
1657 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1658 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1659 GEN6_BLITTER_LOCK_SHIFT;
1660 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1661 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1662 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1663 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1664 GEN6_BLITTER_LOCK_SHIFT);
1665 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1666 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1667 gen6_gt_force_wake_put(dev_priv);
1668}
1669
1670static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671{
1672 struct drm_device *dev = crtc->dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 struct drm_framebuffer *fb = crtc->fb;
1675 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1676 struct drm_i915_gem_object *obj = intel_fb->obj;
1677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1678 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1679 unsigned long stall_watermark = 200;
1680 u32 dpfc_ctl;
1681
1682 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1683 dpfc_ctl &= DPFC_RESERVED;
1684 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1685 /* Set persistent mode for front-buffer rendering, ala X. */
1686 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1687 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1688 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1689
1690 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1691 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1692 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1693 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1694 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1695 /* enable it... */
1696 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1697
1698 if (IS_GEN6(dev)) {
1699 I915_WRITE(SNB_DPFC_CTL_SA,
1700 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1701 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1702 sandybridge_blit_fbc_update(dev);
1703 }
1704
1705 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1706}
1707
1708static void ironlake_disable_fbc(struct drm_device *dev)
1709{
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 u32 dpfc_ctl;
1712
1713 /* Disable compression */
1714 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1715 if (dpfc_ctl & DPFC_CTL_EN) {
1716 dpfc_ctl &= ~DPFC_CTL_EN;
1717 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1718
1719 DRM_DEBUG_KMS("disabled FBC\n");
1720 }
1721}
1722
1723static bool ironlake_fbc_enabled(struct drm_device *dev)
1724{
1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1728}
1729
1730bool intel_fbc_enabled(struct drm_device *dev)
1731{
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734 if (!dev_priv->display.fbc_enabled)
1735 return false;
1736
1737 return dev_priv->display.fbc_enabled(dev);
1738}
1739
1740static void intel_fbc_work_fn(struct work_struct *__work)
1741{
1742 struct intel_fbc_work *work =
1743 container_of(to_delayed_work(__work),
1744 struct intel_fbc_work, work);
1745 struct drm_device *dev = work->crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748 mutex_lock(&dev->struct_mutex);
1749 if (work == dev_priv->fbc_work) {
1750 /* Double check that we haven't switched fb without cancelling
1751 * the prior work.
1752 */
1753 if (work->crtc->fb == work->fb) {
1754 dev_priv->display.enable_fbc(work->crtc,
1755 work->interval);
1756
1757 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1758 dev_priv->cfb_fb = work->crtc->fb->base.id;
1759 dev_priv->cfb_y = work->crtc->y;
1760 }
1761
1762 dev_priv->fbc_work = NULL;
1763 }
1764 mutex_unlock(&dev->struct_mutex);
1765
1766 kfree(work);
1767}
1768
1769static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1770{
1771 if (dev_priv->fbc_work == NULL)
1772 return;
1773
1774 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1775
1776 /* Synchronisation is provided by struct_mutex and checking of
1777 * dev_priv->fbc_work, so we can perform the cancellation
1778 * entirely asynchronously.
1779 */
1780 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1781 /* tasklet was killed before being run, clean up */
1782 kfree(dev_priv->fbc_work);
1783
1784 /* Mark the work as no longer wanted so that if it does
1785 * wake-up (because the work was already running and waiting
1786 * for our mutex), it will discover that is no longer
1787 * necessary to run.
1788 */
1789 dev_priv->fbc_work = NULL;
1790}
1791
1792static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1793{
1794 struct intel_fbc_work *work;
1795 struct drm_device *dev = crtc->dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797
1798 if (!dev_priv->display.enable_fbc)
1799 return;
1800
1801 intel_cancel_fbc_work(dev_priv);
1802
1803 work = kzalloc(sizeof *work, GFP_KERNEL);
1804 if (work == NULL) {
1805 dev_priv->display.enable_fbc(crtc, interval);
1806 return;
1807 }
1808
1809 work->crtc = crtc;
1810 work->fb = crtc->fb;
1811 work->interval = interval;
1812 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1813
1814 dev_priv->fbc_work = work;
1815
1816 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1817
1818 /* Delay the actual enabling to let pageflipping cease and the
1819 * display to settle before starting the compression. Note that
1820 * this delay also serves a second purpose: it allows for a
1821 * vblank to pass after disabling the FBC before we attempt
1822 * to modify the control registers.
1823 *
1824 * A more complicated solution would involve tracking vblanks
1825 * following the termination of the page-flipping sequence
1826 * and indeed performing the enable as a co-routine and not
1827 * waiting synchronously upon the vblank.
1828 */
1829 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1830}
1831
1832void intel_disable_fbc(struct drm_device *dev)
1833{
1834 struct drm_i915_private *dev_priv = dev->dev_private;
1835
1836 intel_cancel_fbc_work(dev_priv);
1837
1838 if (!dev_priv->display.disable_fbc)
1839 return;
1840
1841 dev_priv->display.disable_fbc(dev);
1842 dev_priv->cfb_plane = -1;
1843}
1844
1845/**
1846 * intel_update_fbc - enable/disable FBC as needed
1847 * @dev: the drm_device
1848 *
1849 * Set up the framebuffer compression hardware at mode set time. We
1850 * enable it if possible:
1851 * - plane A only (on pre-965)
1852 * - no pixel mulitply/line duplication
1853 * - no alpha buffer discard
1854 * - no dual wide
1855 * - framebuffer <= 2048 in width, 1536 in height
1856 *
1857 * We can't assume that any compression will take place (worst case),
1858 * so the compressed buffer has to be the same size as the uncompressed
1859 * one. It also must reside (along with the line length buffer) in
1860 * stolen memory.
1861 *
1862 * We need to enable/disable FBC on a global basis.
1863 */
1864static void intel_update_fbc(struct drm_device *dev)
1865{
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1867 struct drm_crtc *crtc = NULL, *tmp_crtc;
1868 struct intel_crtc *intel_crtc;
1869 struct drm_framebuffer *fb;
1870 struct intel_framebuffer *intel_fb;
1871 struct drm_i915_gem_object *obj;
1872 int enable_fbc;
1873
1874 DRM_DEBUG_KMS("\n");
1875
1876 if (!i915_powersave)
1877 return;
1878
1879 if (!I915_HAS_FBC(dev))
1880 return;
1881
1882 /*
1883 * If FBC is already on, we just have to verify that we can
1884 * keep it that way...
1885 * Need to disable if:
1886 * - more than one pipe is active
1887 * - changing FBC params (stride, fence, mode)
1888 * - new fb is too large to fit in compressed buffer
1889 * - going to an unsupported config (interlace, pixel multiply, etc.)
1890 */
1891 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1892 if (tmp_crtc->enabled && tmp_crtc->fb) {
1893 if (crtc) {
1894 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1895 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1896 goto out_disable;
1897 }
1898 crtc = tmp_crtc;
1899 }
1900 }
1901
1902 if (!crtc || crtc->fb == NULL) {
1903 DRM_DEBUG_KMS("no output, disabling\n");
1904 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1905 goto out_disable;
1906 }
1907
1908 intel_crtc = to_intel_crtc(crtc);
1909 fb = crtc->fb;
1910 intel_fb = to_intel_framebuffer(fb);
1911 obj = intel_fb->obj;
1912
1913 enable_fbc = i915_enable_fbc;
1914 if (enable_fbc < 0) {
1915 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1916 enable_fbc = 1;
1917 if (INTEL_INFO(dev)->gen <= 6)
1918 enable_fbc = 0;
1919 }
1920 if (!enable_fbc) {
1921 DRM_DEBUG_KMS("fbc disabled per module param\n");
1922 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1923 goto out_disable;
1924 }
1925 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1926 DRM_DEBUG_KMS("framebuffer too large, disabling "
1927 "compression\n");
1928 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1929 goto out_disable;
1930 }
1931 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1932 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1933 DRM_DEBUG_KMS("mode incompatible with compression, "
1934 "disabling\n");
1935 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1936 goto out_disable;
1937 }
1938 if ((crtc->mode.hdisplay > 2048) ||
1939 (crtc->mode.vdisplay > 1536)) {
1940 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1941 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1942 goto out_disable;
1943 }
1944 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1945 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1946 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1947 goto out_disable;
1948 }
1949
1950 /* The use of a CPU fence is mandatory in order to detect writes
1951 * by the CPU to the scanout and trigger updates to the FBC.
1952 */
1953 if (obj->tiling_mode != I915_TILING_X ||
1954 obj->fence_reg == I915_FENCE_REG_NONE) {
1955 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1956 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1957 goto out_disable;
1958 }
1959
1960 /* If the kernel debugger is active, always disable compression */
1961 if (in_dbg_master())
1962 goto out_disable;
1963
1964 /* If the scanout has not changed, don't modify the FBC settings.
1965 * Note that we make the fundamental assumption that the fb->obj
1966 * cannot be unpinned (and have its GTT offset and fence revoked)
1967 * without first being decoupled from the scanout and FBC disabled.
1968 */
1969 if (dev_priv->cfb_plane == intel_crtc->plane &&
1970 dev_priv->cfb_fb == fb->base.id &&
1971 dev_priv->cfb_y == crtc->y)
1972 return;
1973
1974 if (intel_fbc_enabled(dev)) {
1975 /* We update FBC along two paths, after changing fb/crtc
1976 * configuration (modeswitching) and after page-flipping
1977 * finishes. For the latter, we know that not only did
1978 * we disable the FBC at the start of the page-flip
1979 * sequence, but also more than one vblank has passed.
1980 *
1981 * For the former case of modeswitching, it is possible
1982 * to switch between two FBC valid configurations
1983 * instantaneously so we do need to disable the FBC
1984 * before we can modify its control registers. We also
1985 * have to wait for the next vblank for that to take
1986 * effect. However, since we delay enabling FBC we can
1987 * assume that a vblank has passed since disabling and
1988 * that we can safely alter the registers in the deferred
1989 * callback.
1990 *
1991 * In the scenario that we go from a valid to invalid
1992 * and then back to valid FBC configuration we have
1993 * no strict enforcement that a vblank occurred since
1994 * disabling the FBC. However, along all current pipe
1995 * disabling paths we do need to wait for a vblank at
1996 * some point. And we wait before enabling FBC anyway.
1997 */
1998 DRM_DEBUG_KMS("disabling active FBC for update\n");
1999 intel_disable_fbc(dev);
2000 }
2001
2002 intel_enable_fbc(crtc, 500);
2003 return;
2004
2005out_disable:
2006 /* Multiple disables should be harmless */
2007 if (intel_fbc_enabled(dev)) {
2008 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2009 intel_disable_fbc(dev);
2010 }
2011}
2012
2013int 1765int
2014intel_pin_and_fence_fb_obj(struct drm_device *dev, 1766intel_pin_and_fence_fb_obj(struct drm_device *dev,
2015 struct drm_i915_gem_object *obj, 1767 struct drm_i915_gem_object *obj,
@@ -2050,13 +1802,11 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
2050 * framebuffer compression. For simplicity, we always install 1802 * framebuffer compression. For simplicity, we always install
2051 * a fence as the cost is not that onerous. 1803 * a fence as the cost is not that onerous.
2052 */ 1804 */
2053 if (obj->tiling_mode != I915_TILING_NONE) { 1805 ret = i915_gem_object_get_fence(obj);
2054 ret = i915_gem_object_get_fence(obj, pipelined); 1806 if (ret)
2055 if (ret) 1807 goto err_unpin;
2056 goto err_unpin;
2057 1808
2058 i915_gem_object_pin_fence(obj); 1809 i915_gem_object_pin_fence(obj);
2059 }
2060 1810
2061 dev_priv->mm.interruptible = true; 1811 dev_priv->mm.interruptible = true;
2062 return 0; 1812 return 0;
@@ -2137,7 +1887,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2137 Start, Offset, x, y, fb->pitches[0]); 1887 Start, Offset, x, y, fb->pitches[0]);
2138 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 1888 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2139 if (INTEL_INFO(dev)->gen >= 4) { 1889 if (INTEL_INFO(dev)->gen >= 4) {
2140 I915_WRITE(DSPSURF(plane), Start); 1890 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
2141 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 1891 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142 I915_WRITE(DSPADDR(plane), Offset); 1892 I915_WRITE(DSPADDR(plane), Offset);
2143 } else 1893 } else
@@ -2217,7 +1967,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
2217 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 1967 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2218 Start, Offset, x, y, fb->pitches[0]); 1968 Start, Offset, x, y, fb->pitches[0]);
2219 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 1969 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2220 I915_WRITE(DSPSURF(plane), Start); 1970 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
2221 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 1971 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2222 I915_WRITE(DSPADDR(plane), Offset); 1972 I915_WRITE(DSPADDR(plane), Offset);
2223 POSTING_READ(reg); 1973 POSTING_READ(reg);
@@ -2232,16 +1982,12 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2232{ 1982{
2233 struct drm_device *dev = crtc->dev; 1983 struct drm_device *dev = crtc->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private; 1984 struct drm_i915_private *dev_priv = dev->dev_private;
2235 int ret;
2236
2237 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2238 if (ret)
2239 return ret;
2240 1985
2241 intel_update_fbc(dev); 1986 if (dev_priv->display.disable_fbc)
1987 dev_priv->display.disable_fbc(dev);
2242 intel_increase_pllclock(crtc); 1988 intel_increase_pllclock(crtc);
2243 1989
2244 return 0; 1990 return dev_priv->display.update_plane(crtc, fb, x, y);
2245} 1991}
2246 1992
2247static int 1993static int
@@ -2276,6 +2022,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2276 struct drm_framebuffer *old_fb) 2022 struct drm_framebuffer *old_fb)
2277{ 2023{
2278 struct drm_device *dev = crtc->dev; 2024 struct drm_device *dev = crtc->dev;
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2279 struct drm_i915_master_private *master_priv; 2026 struct drm_i915_master_private *master_priv;
2280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281 int ret; 2028 int ret;
@@ -2286,16 +2033,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2286 return 0; 2033 return 0;
2287 } 2034 }
2288 2035
2289 switch (intel_crtc->plane) { 2036 if(intel_crtc->plane > dev_priv->num_pipe) {
2290 case 0: 2037 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2291 case 1: 2038 intel_crtc->plane,
2292 break; 2039 dev_priv->num_pipe);
2293 case 2:
2294 if (IS_IVYBRIDGE(dev))
2295 break;
2296 /* fall through otherwise */
2297 default:
2298 DRM_ERROR("no plane for crtc\n");
2299 return -EINVAL; 2040 return -EINVAL;
2300 } 2041 }
2301 2042
@@ -2312,8 +2053,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2312 if (old_fb) 2053 if (old_fb)
2313 intel_finish_fb(old_fb); 2054 intel_finish_fb(old_fb);
2314 2055
2315 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, 2056 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2316 LEAVE_ATOMIC_MODE_SET);
2317 if (ret) { 2057 if (ret) {
2318 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); 2058 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2319 mutex_unlock(&dev->struct_mutex); 2059 mutex_unlock(&dev->struct_mutex);
@@ -2326,6 +2066,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2326 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); 2066 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2327 } 2067 }
2328 2068
2069 intel_update_fbc(dev);
2329 mutex_unlock(&dev->struct_mutex); 2070 mutex_unlock(&dev->struct_mutex);
2330 2071
2331 if (!dev->primary->master) 2072 if (!dev->primary->master)
@@ -2547,7 +2288,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
2547 struct drm_i915_private *dev_priv = dev->dev_private; 2288 struct drm_i915_private *dev_priv = dev->dev_private;
2548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2549 int pipe = intel_crtc->pipe; 2290 int pipe = intel_crtc->pipe;
2550 u32 reg, temp, i; 2291 u32 reg, temp, i, retry;
2551 2292
2552 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2293 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2553 for train result */ 2294 for train result */
@@ -2599,15 +2340,19 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
2599 POSTING_READ(reg); 2340 POSTING_READ(reg);
2600 udelay(500); 2341 udelay(500);
2601 2342
2602 reg = FDI_RX_IIR(pipe); 2343 for (retry = 0; retry < 5; retry++) {
2603 temp = I915_READ(reg); 2344 reg = FDI_RX_IIR(pipe);
2604 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2345 temp = I915_READ(reg);
2605 2346 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2606 if (temp & FDI_RX_BIT_LOCK) { 2347 if (temp & FDI_RX_BIT_LOCK) {
2607 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2348 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2608 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2349 DRM_DEBUG_KMS("FDI train 1 done.\n");
2609 break; 2350 break;
2351 }
2352 udelay(50);
2610 } 2353 }
2354 if (retry < 5)
2355 break;
2611 } 2356 }
2612 if (i == 4) 2357 if (i == 4)
2613 DRM_ERROR("FDI train 1 fail!\n"); 2358 DRM_ERROR("FDI train 1 fail!\n");
@@ -2648,15 +2393,19 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
2648 POSTING_READ(reg); 2393 POSTING_READ(reg);
2649 udelay(500); 2394 udelay(500);
2650 2395
2651 reg = FDI_RX_IIR(pipe); 2396 for (retry = 0; retry < 5; retry++) {
2652 temp = I915_READ(reg); 2397 reg = FDI_RX_IIR(pipe);
2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2398 temp = I915_READ(reg);
2654 2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2655 if (temp & FDI_RX_SYMBOL_LOCK) { 2400 if (temp & FDI_RX_SYMBOL_LOCK) {
2656 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2401 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2402 DRM_DEBUG_KMS("FDI train 2 done.\n");
2658 break; 2403 break;
2404 }
2405 udelay(50);
2659 } 2406 }
2407 if (retry < 5)
2408 break;
2660 } 2409 }
2661 if (i == 4) 2410 if (i == 4)
2662 DRM_ERROR("FDI train 2 fail!\n"); 2411 DRM_ERROR("FDI train 2 fail!\n");
@@ -2808,14 +2557,18 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2808 POSTING_READ(reg); 2557 POSTING_READ(reg);
2809 udelay(200); 2558 udelay(200);
2810 2559
2811 /* Enable CPU FDI TX PLL, always on for Ironlake */ 2560 /* On Haswell, the PLL configuration for ports and pipes is handled
2812 reg = FDI_TX_CTL(pipe); 2561 * separately, as part of DDI setup */
2813 temp = I915_READ(reg); 2562 if (!IS_HASWELL(dev)) {
2814 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 2563 /* Enable CPU FDI TX PLL, always on for Ironlake */
2815 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); 2564 reg = FDI_TX_CTL(pipe);
2565 temp = I915_READ(reg);
2566 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2567 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2816 2568
2817 POSTING_READ(reg); 2569 POSTING_READ(reg);
2818 udelay(100); 2570 udelay(100);
2571 }
2819 } 2572 }
2820} 2573}
2821 2574
@@ -2888,38 +2641,16 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
2888 udelay(100); 2641 udelay(100);
2889} 2642}
2890 2643
2891/*
2892 * When we disable a pipe, we need to clear any pending scanline wait events
2893 * to avoid hanging the ring, which we assume we are waiting on.
2894 */
2895static void intel_clear_scanline_wait(struct drm_device *dev)
2896{
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2898 struct intel_ring_buffer *ring;
2899 u32 tmp;
2900
2901 if (IS_GEN2(dev))
2902 /* Can't break the hang on i8xx */
2903 return;
2904
2905 ring = LP_RING(dev_priv);
2906 tmp = I915_READ_CTL(ring);
2907 if (tmp & RING_WAIT)
2908 I915_WRITE_CTL(ring, tmp);
2909}
2910
2911static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 2644static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2912{ 2645{
2913 struct drm_i915_gem_object *obj; 2646 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv;
2915 2647
2916 if (crtc->fb == NULL) 2648 if (crtc->fb == NULL)
2917 return; 2649 return;
2918 2650
2919 obj = to_intel_framebuffer(crtc->fb)->obj; 2651 mutex_lock(&dev->struct_mutex);
2920 dev_priv = crtc->dev->dev_private; 2652 intel_finish_fb(crtc->fb);
2921 wait_event(dev_priv->pending_flip_queue, 2653 mutex_unlock(&dev->struct_mutex);
2922 atomic_read(&obj->pending_flip) == 0);
2923} 2654}
2924 2655
2925static bool intel_crtc_driving_pch(struct drm_crtc *crtc) 2656static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
@@ -2936,6 +2667,22 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2936 if (encoder->base.crtc != crtc) 2667 if (encoder->base.crtc != crtc)
2937 continue; 2668 continue;
2938 2669
2670 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2671 * CPU handles all others */
2672 if (IS_HASWELL(dev)) {
2673 /* It is still unclear how this will work on PPT, so throw up a warning */
2674 WARN_ON(!HAS_PCH_LPT(dev));
2675
2676 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2677 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2678 return true;
2679 } else {
2680 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2681 encoder->type);
2682 return false;
2683 }
2684 }
2685
2939 switch (encoder->type) { 2686 switch (encoder->type) {
2940 case INTEL_OUTPUT_EDP: 2687 case INTEL_OUTPUT_EDP:
2941 if (!intel_encoder_is_pch_edp(&encoder->base)) 2688 if (!intel_encoder_is_pch_edp(&encoder->base))
@@ -2947,6 +2694,97 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2947 return true; 2694 return true;
2948} 2695}
2949 2696
2697/* Program iCLKIP clock to the desired frequency */
2698static void lpt_program_iclkip(struct drm_crtc *crtc)
2699{
2700 struct drm_device *dev = crtc->dev;
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2702 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2703 u32 temp;
2704
2705 /* It is necessary to ungate the pixclk gate prior to programming
2706 * the divisors, and gate it back when it is done.
2707 */
2708 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2709
2710 /* Disable SSCCTL */
2711 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2712 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2713 SBI_SSCCTL_DISABLE);
2714
2715 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2716 if (crtc->mode.clock == 20000) {
2717 auxdiv = 1;
2718 divsel = 0x41;
2719 phaseinc = 0x20;
2720 } else {
2721 /* The iCLK virtual clock root frequency is in MHz,
2722 * but the crtc->mode.clock in in KHz. To get the divisors,
2723 * it is necessary to divide one by another, so we
2724 * convert the virtual clock precision to KHz here for higher
2725 * precision.
2726 */
2727 u32 iclk_virtual_root_freq = 172800 * 1000;
2728 u32 iclk_pi_range = 64;
2729 u32 desired_divisor, msb_divisor_value, pi_value;
2730
2731 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2732 msb_divisor_value = desired_divisor / iclk_pi_range;
2733 pi_value = desired_divisor % iclk_pi_range;
2734
2735 auxdiv = 0;
2736 divsel = msb_divisor_value - 2;
2737 phaseinc = pi_value;
2738 }
2739
2740 /* This should not happen with any sane values */
2741 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2742 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2743 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2744 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2745
2746 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2747 crtc->mode.clock,
2748 auxdiv,
2749 divsel,
2750 phasedir,
2751 phaseinc);
2752
2753 /* Program SSCDIVINTPHASE6 */
2754 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2755 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2756 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2757 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2758 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2759 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2760 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2761
2762 intel_sbi_write(dev_priv,
2763 SBI_SSCDIVINTPHASE6,
2764 temp);
2765
2766 /* Program SSCAUXDIV */
2767 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2768 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2769 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2770 intel_sbi_write(dev_priv,
2771 SBI_SSCAUXDIV6,
2772 temp);
2773
2774
2775 /* Enable modulator and associated divider */
2776 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2777 temp &= ~SBI_SSCCTL_DISABLE;
2778 intel_sbi_write(dev_priv,
2779 SBI_SSCCTL6,
2780 temp);
2781
2782 /* Wait for initialization time */
2783 udelay(24);
2784
2785 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2786}
2787
2950/* 2788/*
2951 * Enable PCH resources required for PCH ports: 2789 * Enable PCH resources required for PCH ports:
2952 * - PCH PLLs 2790 * - PCH PLLs
@@ -2961,29 +2799,41 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
2961 struct drm_i915_private *dev_priv = dev->dev_private; 2799 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe; 2801 int pipe = intel_crtc->pipe;
2964 u32 reg, temp, transc_sel; 2802 u32 reg, temp;
2803
2804 assert_transcoder_disabled(dev_priv, pipe);
2965 2805
2966 /* For PCH output, training FDI link */ 2806 /* For PCH output, training FDI link */
2967 dev_priv->display.fdi_link_train(crtc); 2807 dev_priv->display.fdi_link_train(crtc);
2968 2808
2969 intel_enable_pch_pll(dev_priv, pipe); 2809 intel_enable_pch_pll(intel_crtc);
2970 2810
2971 if (HAS_PCH_CPT(dev)) { 2811 if (HAS_PCH_LPT(dev)) {
2972 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : 2812 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2973 TRANSC_DPLLB_SEL; 2813 lpt_program_iclkip(crtc);
2814 } else if (HAS_PCH_CPT(dev)) {
2815 u32 sel;
2974 2816
2975 /* Be sure PCH DPLL SEL is set */
2976 temp = I915_READ(PCH_DPLL_SEL); 2817 temp = I915_READ(PCH_DPLL_SEL);
2977 if (pipe == 0) { 2818 switch (pipe) {
2978 temp &= ~(TRANSA_DPLLB_SEL); 2819 default:
2979 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); 2820 case 0:
2980 } else if (pipe == 1) { 2821 temp |= TRANSA_DPLL_ENABLE;
2981 temp &= ~(TRANSB_DPLLB_SEL); 2822 sel = TRANSA_DPLLB_SEL;
2982 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 2823 break;
2983 } else if (pipe == 2) { 2824 case 1:
2984 temp &= ~(TRANSC_DPLLB_SEL); 2825 temp |= TRANSB_DPLL_ENABLE;
2985 temp |= (TRANSC_DPLL_ENABLE | transc_sel); 2826 sel = TRANSB_DPLLB_SEL;
2827 break;
2828 case 2:
2829 temp |= TRANSC_DPLL_ENABLE;
2830 sel = TRANSC_DPLLB_SEL;
2831 break;
2986 } 2832 }
2833 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2834 temp |= sel;
2835 else
2836 temp &= ~sel;
2987 I915_WRITE(PCH_DPLL_SEL, temp); 2837 I915_WRITE(PCH_DPLL_SEL, temp);
2988 } 2838 }
2989 2839
@@ -2998,7 +2848,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
2998 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); 2848 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2999 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); 2849 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3000 2850
3001 intel_fdi_normal_train(crtc); 2851 if (!IS_HASWELL(dev))
2852 intel_fdi_normal_train(crtc);
3002 2853
3003 /* For PCH DP, enable TRANS_DP_CTL */ 2854 /* For PCH DP, enable TRANS_DP_CTL */
3004 if (HAS_PCH_CPT(dev) && 2855 if (HAS_PCH_CPT(dev) &&
@@ -3041,6 +2892,93 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
3041 intel_enable_transcoder(dev_priv, pipe); 2892 intel_enable_transcoder(dev_priv, pipe);
3042} 2893}
3043 2894
2895static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2896{
2897 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2898
2899 if (pll == NULL)
2900 return;
2901
2902 if (pll->refcount == 0) {
2903 WARN(1, "bad PCH PLL refcount\n");
2904 return;
2905 }
2906
2907 --pll->refcount;
2908 intel_crtc->pch_pll = NULL;
2909}
2910
2911static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2912{
2913 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2914 struct intel_pch_pll *pll;
2915 int i;
2916
2917 pll = intel_crtc->pch_pll;
2918 if (pll) {
2919 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2920 intel_crtc->base.base.id, pll->pll_reg);
2921 goto prepare;
2922 }
2923
2924 if (HAS_PCH_IBX(dev_priv->dev)) {
2925 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
2926 i = intel_crtc->pipe;
2927 pll = &dev_priv->pch_plls[i];
2928
2929 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
2930 intel_crtc->base.base.id, pll->pll_reg);
2931
2932 goto found;
2933 }
2934
2935 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2936 pll = &dev_priv->pch_plls[i];
2937
2938 /* Only want to check enabled timings first */
2939 if (pll->refcount == 0)
2940 continue;
2941
2942 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2943 fp == I915_READ(pll->fp0_reg)) {
2944 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2945 intel_crtc->base.base.id,
2946 pll->pll_reg, pll->refcount, pll->active);
2947
2948 goto found;
2949 }
2950 }
2951
2952 /* Ok no matching timings, maybe there's a free one? */
2953 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2954 pll = &dev_priv->pch_plls[i];
2955 if (pll->refcount == 0) {
2956 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2957 intel_crtc->base.base.id, pll->pll_reg);
2958 goto found;
2959 }
2960 }
2961
2962 return NULL;
2963
2964found:
2965 intel_crtc->pch_pll = pll;
2966 pll->refcount++;
2967 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2968prepare: /* separate function? */
2969 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2970
2971 /* Wait for the clocks to stabilize before rewriting the regs */
2972 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2973 POSTING_READ(pll->pll_reg);
2974 udelay(150);
2975
2976 I915_WRITE(pll->fp0_reg, fp);
2977 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2978 pll->on = false;
2979 return pll;
2980}
2981
3044void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) 2982void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3045{ 2983{
3046 struct drm_i915_private *dev_priv = dev->dev_private; 2984 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3185,8 +3123,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
3185 } 3123 }
3186 3124
3187 /* disable PCH DPLL */ 3125 /* disable PCH DPLL */
3188 if (!intel_crtc->no_pll) 3126 intel_disable_pch_pll(intel_crtc);
3189 intel_disable_pch_pll(dev_priv, pipe);
3190 3127
3191 /* Switch from PCDclk to Rawclk */ 3128 /* Switch from PCDclk to Rawclk */
3192 reg = FDI_RX_CTL(pipe); 3129 reg = FDI_RX_CTL(pipe);
@@ -3214,7 +3151,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
3214 3151
3215 mutex_lock(&dev->struct_mutex); 3152 mutex_lock(&dev->struct_mutex);
3216 intel_update_fbc(dev); 3153 intel_update_fbc(dev);
3217 intel_clear_scanline_wait(dev);
3218 mutex_unlock(&dev->struct_mutex); 3154 mutex_unlock(&dev->struct_mutex);
3219} 3155}
3220 3156
@@ -3242,6 +3178,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3242 } 3178 }
3243} 3179}
3244 3180
3181static void ironlake_crtc_off(struct drm_crtc *crtc)
3182{
3183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184 intel_put_pch_pll(intel_crtc);
3185}
3186
3245static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) 3187static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3246{ 3188{
3247 if (!enable && intel_crtc->overlay) { 3189 if (!enable && intel_crtc->overlay) {
@@ -3313,7 +3255,6 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
3313 intel_crtc->active = false; 3255 intel_crtc->active = false;
3314 intel_update_fbc(dev); 3256 intel_update_fbc(dev);
3315 intel_update_watermarks(dev); 3257 intel_update_watermarks(dev);
3316 intel_clear_scanline_wait(dev);
3317} 3258}
3318 3259
3319static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) 3260static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
@@ -3333,6 +3274,10 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3333 } 3274 }
3334} 3275}
3335 3276
3277static void i9xx_crtc_off(struct drm_crtc *crtc)
3278{
3279}
3280
3336/** 3281/**
3337 * Sets the power management mode of the pipe and plane. 3282 * Sets the power management mode of the pipe and plane.
3338 */ 3283 */
@@ -3380,25 +3325,11 @@ static void intel_crtc_disable(struct drm_crtc *crtc)
3380{ 3325{
3381 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 3326 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3382 struct drm_device *dev = crtc->dev; 3327 struct drm_device *dev = crtc->dev;
3383 3328 struct drm_i915_private *dev_priv = dev->dev_private;
3384 /* Flush any pending WAITs before we disable the pipe. Note that
3385 * we need to drop the struct_mutex in order to acquire it again
3386 * during the lowlevel dpms routines around a couple of the
3387 * operations. It does not look trivial nor desirable to move
3388 * that locking higher. So instead we leave a window for the
3389 * submission of further commands on the fb before we can actually
3390 * disable it. This race with userspace exists anyway, and we can
3391 * only rely on the pipe being disabled by userspace after it
3392 * receives the hotplug notification and has flushed any pending
3393 * batches.
3394 */
3395 if (crtc->fb) {
3396 mutex_lock(&dev->struct_mutex);
3397 intel_finish_fb(crtc->fb);
3398 mutex_unlock(&dev->struct_mutex);
3399 }
3400 3329
3401 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 3330 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3331 dev_priv->display.off(crtc);
3332
3402 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); 3333 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3403 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); 3334 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3404 3335
@@ -3448,8 +3379,7 @@ void intel_encoder_commit(struct drm_encoder *encoder)
3448{ 3379{
3449 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3380 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3450 struct drm_device *dev = encoder->dev; 3381 struct drm_device *dev = encoder->dev;
3451 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3382 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3452 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3453 3383
3454 /* lvds has its own version of commit see intel_lvds_commit */ 3384 /* lvds has its own version of commit see intel_lvds_commit */
3455 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 3385 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
@@ -3487,6 +3417,11 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3487 return true; 3417 return true;
3488} 3418}
3489 3419
3420static int valleyview_get_display_clock_speed(struct drm_device *dev)
3421{
3422 return 400000; /* FIXME */
3423}
3424
3490static int i945_get_display_clock_speed(struct drm_device *dev) 3425static int i945_get_display_clock_speed(struct drm_device *dev)
3491{ 3426{
3492 return 400000; 3427 return 400000;
@@ -3584,1342 +3519,6 @@ ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3584 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); 3519 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3585} 3520}
3586 3521
3587
3588struct intel_watermark_params {
3589 unsigned long fifo_size;
3590 unsigned long max_wm;
3591 unsigned long default_wm;
3592 unsigned long guard_size;
3593 unsigned long cacheline_size;
3594};
3595
3596/* Pineview has different values for various configs */
3597static const struct intel_watermark_params pineview_display_wm = {
3598 PINEVIEW_DISPLAY_FIFO,
3599 PINEVIEW_MAX_WM,
3600 PINEVIEW_DFT_WM,
3601 PINEVIEW_GUARD_WM,
3602 PINEVIEW_FIFO_LINE_SIZE
3603};
3604static const struct intel_watermark_params pineview_display_hplloff_wm = {
3605 PINEVIEW_DISPLAY_FIFO,
3606 PINEVIEW_MAX_WM,
3607 PINEVIEW_DFT_HPLLOFF_WM,
3608 PINEVIEW_GUARD_WM,
3609 PINEVIEW_FIFO_LINE_SIZE
3610};
3611static const struct intel_watermark_params pineview_cursor_wm = {
3612 PINEVIEW_CURSOR_FIFO,
3613 PINEVIEW_CURSOR_MAX_WM,
3614 PINEVIEW_CURSOR_DFT_WM,
3615 PINEVIEW_CURSOR_GUARD_WM,
3616 PINEVIEW_FIFO_LINE_SIZE,
3617};
3618static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3619 PINEVIEW_CURSOR_FIFO,
3620 PINEVIEW_CURSOR_MAX_WM,
3621 PINEVIEW_CURSOR_DFT_WM,
3622 PINEVIEW_CURSOR_GUARD_WM,
3623 PINEVIEW_FIFO_LINE_SIZE
3624};
3625static const struct intel_watermark_params g4x_wm_info = {
3626 G4X_FIFO_SIZE,
3627 G4X_MAX_WM,
3628 G4X_MAX_WM,
3629 2,
3630 G4X_FIFO_LINE_SIZE,
3631};
3632static const struct intel_watermark_params g4x_cursor_wm_info = {
3633 I965_CURSOR_FIFO,
3634 I965_CURSOR_MAX_WM,
3635 I965_CURSOR_DFT_WM,
3636 2,
3637 G4X_FIFO_LINE_SIZE,
3638};
3639static const struct intel_watermark_params i965_cursor_wm_info = {
3640 I965_CURSOR_FIFO,
3641 I965_CURSOR_MAX_WM,
3642 I965_CURSOR_DFT_WM,
3643 2,
3644 I915_FIFO_LINE_SIZE,
3645};
3646static const struct intel_watermark_params i945_wm_info = {
3647 I945_FIFO_SIZE,
3648 I915_MAX_WM,
3649 1,
3650 2,
3651 I915_FIFO_LINE_SIZE
3652};
3653static const struct intel_watermark_params i915_wm_info = {
3654 I915_FIFO_SIZE,
3655 I915_MAX_WM,
3656 1,
3657 2,
3658 I915_FIFO_LINE_SIZE
3659};
3660static const struct intel_watermark_params i855_wm_info = {
3661 I855GM_FIFO_SIZE,
3662 I915_MAX_WM,
3663 1,
3664 2,
3665 I830_FIFO_LINE_SIZE
3666};
3667static const struct intel_watermark_params i830_wm_info = {
3668 I830_FIFO_SIZE,
3669 I915_MAX_WM,
3670 1,
3671 2,
3672 I830_FIFO_LINE_SIZE
3673};
3674
3675static const struct intel_watermark_params ironlake_display_wm_info = {
3676 ILK_DISPLAY_FIFO,
3677 ILK_DISPLAY_MAXWM,
3678 ILK_DISPLAY_DFTWM,
3679 2,
3680 ILK_FIFO_LINE_SIZE
3681};
3682static const struct intel_watermark_params ironlake_cursor_wm_info = {
3683 ILK_CURSOR_FIFO,
3684 ILK_CURSOR_MAXWM,
3685 ILK_CURSOR_DFTWM,
3686 2,
3687 ILK_FIFO_LINE_SIZE
3688};
3689static const struct intel_watermark_params ironlake_display_srwm_info = {
3690 ILK_DISPLAY_SR_FIFO,
3691 ILK_DISPLAY_MAX_SRWM,
3692 ILK_DISPLAY_DFT_SRWM,
3693 2,
3694 ILK_FIFO_LINE_SIZE
3695};
3696static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3697 ILK_CURSOR_SR_FIFO,
3698 ILK_CURSOR_MAX_SRWM,
3699 ILK_CURSOR_DFT_SRWM,
3700 2,
3701 ILK_FIFO_LINE_SIZE
3702};
3703
3704static const struct intel_watermark_params sandybridge_display_wm_info = {
3705 SNB_DISPLAY_FIFO,
3706 SNB_DISPLAY_MAXWM,
3707 SNB_DISPLAY_DFTWM,
3708 2,
3709 SNB_FIFO_LINE_SIZE
3710};
3711static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3712 SNB_CURSOR_FIFO,
3713 SNB_CURSOR_MAXWM,
3714 SNB_CURSOR_DFTWM,
3715 2,
3716 SNB_FIFO_LINE_SIZE
3717};
3718static const struct intel_watermark_params sandybridge_display_srwm_info = {
3719 SNB_DISPLAY_SR_FIFO,
3720 SNB_DISPLAY_MAX_SRWM,
3721 SNB_DISPLAY_DFT_SRWM,
3722 2,
3723 SNB_FIFO_LINE_SIZE
3724};
3725static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3726 SNB_CURSOR_SR_FIFO,
3727 SNB_CURSOR_MAX_SRWM,
3728 SNB_CURSOR_DFT_SRWM,
3729 2,
3730 SNB_FIFO_LINE_SIZE
3731};
3732
3733
3734/**
3735 * intel_calculate_wm - calculate watermark level
3736 * @clock_in_khz: pixel clock
3737 * @wm: chip FIFO params
3738 * @pixel_size: display pixel size
3739 * @latency_ns: memory latency for the platform
3740 *
3741 * Calculate the watermark level (the level at which the display plane will
3742 * start fetching from memory again). Each chip has a different display
3743 * FIFO size and allocation, so the caller needs to figure that out and pass
3744 * in the correct intel_watermark_params structure.
3745 *
3746 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3747 * on the pixel size. When it reaches the watermark level, it'll start
3748 * fetching FIFO line sized based chunks from memory until the FIFO fills
3749 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3750 * will occur, and a display engine hang could result.
3751 */
3752static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3753 const struct intel_watermark_params *wm,
3754 int fifo_size,
3755 int pixel_size,
3756 unsigned long latency_ns)
3757{
3758 long entries_required, wm_size;
3759
3760 /*
3761 * Note: we need to make sure we don't overflow for various clock &
3762 * latency values.
3763 * clocks go from a few thousand to several hundred thousand.
3764 * latency is usually a few thousand
3765 */
3766 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3767 1000;
3768 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3769
3770 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3771
3772 wm_size = fifo_size - (entries_required + wm->guard_size);
3773
3774 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3775
3776 /* Don't promote wm_size to unsigned... */
3777 if (wm_size > (long)wm->max_wm)
3778 wm_size = wm->max_wm;
3779 if (wm_size <= 0)
3780 wm_size = wm->default_wm;
3781 return wm_size;
3782}
3783
3784struct cxsr_latency {
3785 int is_desktop;
3786 int is_ddr3;
3787 unsigned long fsb_freq;
3788 unsigned long mem_freq;
3789 unsigned long display_sr;
3790 unsigned long display_hpll_disable;
3791 unsigned long cursor_sr;
3792 unsigned long cursor_hpll_disable;
3793};
3794
3795static const struct cxsr_latency cxsr_latency_table[] = {
3796 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3797 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3798 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3799 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3800 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3801
3802 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3803 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3804 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3805 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3806 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3807
3808 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3809 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3810 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3811 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3812 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3813
3814 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3815 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3816 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3817 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3818 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3819
3820 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3821 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3822 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3823 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3824 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3825
3826 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3827 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3828 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3829 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3830 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3831};
3832
3833static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3834 int is_ddr3,
3835 int fsb,
3836 int mem)
3837{
3838 const struct cxsr_latency *latency;
3839 int i;
3840
3841 if (fsb == 0 || mem == 0)
3842 return NULL;
3843
3844 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3845 latency = &cxsr_latency_table[i];
3846 if (is_desktop == latency->is_desktop &&
3847 is_ddr3 == latency->is_ddr3 &&
3848 fsb == latency->fsb_freq && mem == latency->mem_freq)
3849 return latency;
3850 }
3851
3852 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3853
3854 return NULL;
3855}
3856
3857static void pineview_disable_cxsr(struct drm_device *dev)
3858{
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3860
3861 /* deactivate cxsr */
3862 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3863}
3864
3865/*
3866 * Latency for FIFO fetches is dependent on several factors:
3867 * - memory configuration (speed, channels)
3868 * - chipset
3869 * - current MCH state
3870 * It can be fairly high in some situations, so here we assume a fairly
3871 * pessimal value. It's a tradeoff between extra memory fetches (if we
3872 * set this value too high, the FIFO will fetch frequently to stay full)
3873 * and power consumption (set it too low to save power and we might see
3874 * FIFO underruns and display "flicker").
3875 *
3876 * A value of 5us seems to be a good balance; safe for very low end
3877 * platforms but not overly aggressive on lower latency configs.
3878 */
3879static const int latency_ns = 5000;
3880
3881static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3882{
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884 uint32_t dsparb = I915_READ(DSPARB);
3885 int size;
3886
3887 size = dsparb & 0x7f;
3888 if (plane)
3889 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3890
3891 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3892 plane ? "B" : "A", size);
3893
3894 return size;
3895}
3896
3897static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3898{
3899 struct drm_i915_private *dev_priv = dev->dev_private;
3900 uint32_t dsparb = I915_READ(DSPARB);
3901 int size;
3902
3903 size = dsparb & 0x1ff;
3904 if (plane)
3905 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3906 size >>= 1; /* Convert to cachelines */
3907
3908 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3909 plane ? "B" : "A", size);
3910
3911 return size;
3912}
3913
3914static int i845_get_fifo_size(struct drm_device *dev, int plane)
3915{
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 uint32_t dsparb = I915_READ(DSPARB);
3918 int size;
3919
3920 size = dsparb & 0x7f;
3921 size >>= 2; /* Convert to cachelines */
3922
3923 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3924 plane ? "B" : "A",
3925 size);
3926
3927 return size;
3928}
3929
3930static int i830_get_fifo_size(struct drm_device *dev, int plane)
3931{
3932 struct drm_i915_private *dev_priv = dev->dev_private;
3933 uint32_t dsparb = I915_READ(DSPARB);
3934 int size;
3935
3936 size = dsparb & 0x7f;
3937 size >>= 1; /* Convert to cachelines */
3938
3939 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3940 plane ? "B" : "A", size);
3941
3942 return size;
3943}
3944
3945static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3946{
3947 struct drm_crtc *crtc, *enabled = NULL;
3948
3949 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3950 if (crtc->enabled && crtc->fb) {
3951 if (enabled)
3952 return NULL;
3953 enabled = crtc;
3954 }
3955 }
3956
3957 return enabled;
3958}
3959
3960static void pineview_update_wm(struct drm_device *dev)
3961{
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 struct drm_crtc *crtc;
3964 const struct cxsr_latency *latency;
3965 u32 reg;
3966 unsigned long wm;
3967
3968 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3969 dev_priv->fsb_freq, dev_priv->mem_freq);
3970 if (!latency) {
3971 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3972 pineview_disable_cxsr(dev);
3973 return;
3974 }
3975
3976 crtc = single_enabled_crtc(dev);
3977 if (crtc) {
3978 int clock = crtc->mode.clock;
3979 int pixel_size = crtc->fb->bits_per_pixel / 8;
3980
3981 /* Display SR */
3982 wm = intel_calculate_wm(clock, &pineview_display_wm,
3983 pineview_display_wm.fifo_size,
3984 pixel_size, latency->display_sr);
3985 reg = I915_READ(DSPFW1);
3986 reg &= ~DSPFW_SR_MASK;
3987 reg |= wm << DSPFW_SR_SHIFT;
3988 I915_WRITE(DSPFW1, reg);
3989 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3990
3991 /* cursor SR */
3992 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3993 pineview_display_wm.fifo_size,
3994 pixel_size, latency->cursor_sr);
3995 reg = I915_READ(DSPFW3);
3996 reg &= ~DSPFW_CURSOR_SR_MASK;
3997 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3998 I915_WRITE(DSPFW3, reg);
3999
4000 /* Display HPLL off SR */
4001 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4002 pineview_display_hplloff_wm.fifo_size,
4003 pixel_size, latency->display_hpll_disable);
4004 reg = I915_READ(DSPFW3);
4005 reg &= ~DSPFW_HPLL_SR_MASK;
4006 reg |= wm & DSPFW_HPLL_SR_MASK;
4007 I915_WRITE(DSPFW3, reg);
4008
4009 /* cursor HPLL off SR */
4010 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4011 pineview_display_hplloff_wm.fifo_size,
4012 pixel_size, latency->cursor_hpll_disable);
4013 reg = I915_READ(DSPFW3);
4014 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4015 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4016 I915_WRITE(DSPFW3, reg);
4017 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4018
4019 /* activate cxsr */
4020 I915_WRITE(DSPFW3,
4021 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4022 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4023 } else {
4024 pineview_disable_cxsr(dev);
4025 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4026 }
4027}
4028
4029static bool g4x_compute_wm0(struct drm_device *dev,
4030 int plane,
4031 const struct intel_watermark_params *display,
4032 int display_latency_ns,
4033 const struct intel_watermark_params *cursor,
4034 int cursor_latency_ns,
4035 int *plane_wm,
4036 int *cursor_wm)
4037{
4038 struct drm_crtc *crtc;
4039 int htotal, hdisplay, clock, pixel_size;
4040 int line_time_us, line_count;
4041 int entries, tlb_miss;
4042
4043 crtc = intel_get_crtc_for_plane(dev, plane);
4044 if (crtc->fb == NULL || !crtc->enabled) {
4045 *cursor_wm = cursor->guard_size;
4046 *plane_wm = display->guard_size;
4047 return false;
4048 }
4049
4050 htotal = crtc->mode.htotal;
4051 hdisplay = crtc->mode.hdisplay;
4052 clock = crtc->mode.clock;
4053 pixel_size = crtc->fb->bits_per_pixel / 8;
4054
4055 /* Use the small buffer method to calculate plane watermark */
4056 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4057 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4058 if (tlb_miss > 0)
4059 entries += tlb_miss;
4060 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4061 *plane_wm = entries + display->guard_size;
4062 if (*plane_wm > (int)display->max_wm)
4063 *plane_wm = display->max_wm;
4064
4065 /* Use the large buffer method to calculate cursor watermark */
4066 line_time_us = ((htotal * 1000) / clock);
4067 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4068 entries = line_count * 64 * pixel_size;
4069 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4070 if (tlb_miss > 0)
4071 entries += tlb_miss;
4072 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4073 *cursor_wm = entries + cursor->guard_size;
4074 if (*cursor_wm > (int)cursor->max_wm)
4075 *cursor_wm = (int)cursor->max_wm;
4076
4077 return true;
4078}
4079
4080/*
4081 * Check the wm result.
4082 *
4083 * If any calculated watermark values is larger than the maximum value that
4084 * can be programmed into the associated watermark register, that watermark
4085 * must be disabled.
4086 */
4087static bool g4x_check_srwm(struct drm_device *dev,
4088 int display_wm, int cursor_wm,
4089 const struct intel_watermark_params *display,
4090 const struct intel_watermark_params *cursor)
4091{
4092 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4093 display_wm, cursor_wm);
4094
4095 if (display_wm > display->max_wm) {
4096 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4097 display_wm, display->max_wm);
4098 return false;
4099 }
4100
4101 if (cursor_wm > cursor->max_wm) {
4102 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4103 cursor_wm, cursor->max_wm);
4104 return false;
4105 }
4106
4107 if (!(display_wm || cursor_wm)) {
4108 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4109 return false;
4110 }
4111
4112 return true;
4113}
4114
4115static bool g4x_compute_srwm(struct drm_device *dev,
4116 int plane,
4117 int latency_ns,
4118 const struct intel_watermark_params *display,
4119 const struct intel_watermark_params *cursor,
4120 int *display_wm, int *cursor_wm)
4121{
4122 struct drm_crtc *crtc;
4123 int hdisplay, htotal, pixel_size, clock;
4124 unsigned long line_time_us;
4125 int line_count, line_size;
4126 int small, large;
4127 int entries;
4128
4129 if (!latency_ns) {
4130 *display_wm = *cursor_wm = 0;
4131 return false;
4132 }
4133
4134 crtc = intel_get_crtc_for_plane(dev, plane);
4135 hdisplay = crtc->mode.hdisplay;
4136 htotal = crtc->mode.htotal;
4137 clock = crtc->mode.clock;
4138 pixel_size = crtc->fb->bits_per_pixel / 8;
4139
4140 line_time_us = (htotal * 1000) / clock;
4141 line_count = (latency_ns / line_time_us + 1000) / 1000;
4142 line_size = hdisplay * pixel_size;
4143
4144 /* Use the minimum of the small and large buffer method for primary */
4145 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4146 large = line_count * line_size;
4147
4148 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4149 *display_wm = entries + display->guard_size;
4150
4151 /* calculate the self-refresh watermark for display cursor */
4152 entries = line_count * pixel_size * 64;
4153 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4154 *cursor_wm = entries + cursor->guard_size;
4155
4156 return g4x_check_srwm(dev,
4157 *display_wm, *cursor_wm,
4158 display, cursor);
4159}
4160
4161#define single_plane_enabled(mask) is_power_of_2(mask)
4162
4163static void g4x_update_wm(struct drm_device *dev)
4164{
4165 static const int sr_latency_ns = 12000;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4168 int plane_sr, cursor_sr;
4169 unsigned int enabled = 0;
4170
4171 if (g4x_compute_wm0(dev, 0,
4172 &g4x_wm_info, latency_ns,
4173 &g4x_cursor_wm_info, latency_ns,
4174 &planea_wm, &cursora_wm))
4175 enabled |= 1;
4176
4177 if (g4x_compute_wm0(dev, 1,
4178 &g4x_wm_info, latency_ns,
4179 &g4x_cursor_wm_info, latency_ns,
4180 &planeb_wm, &cursorb_wm))
4181 enabled |= 2;
4182
4183 plane_sr = cursor_sr = 0;
4184 if (single_plane_enabled(enabled) &&
4185 g4x_compute_srwm(dev, ffs(enabled) - 1,
4186 sr_latency_ns,
4187 &g4x_wm_info,
4188 &g4x_cursor_wm_info,
4189 &plane_sr, &cursor_sr))
4190 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4191 else
4192 I915_WRITE(FW_BLC_SELF,
4193 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4194
4195 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4196 planea_wm, cursora_wm,
4197 planeb_wm, cursorb_wm,
4198 plane_sr, cursor_sr);
4199
4200 I915_WRITE(DSPFW1,
4201 (plane_sr << DSPFW_SR_SHIFT) |
4202 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4203 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4204 planea_wm);
4205 I915_WRITE(DSPFW2,
4206 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4207 (cursora_wm << DSPFW_CURSORA_SHIFT));
4208 /* HPLL off in SR has some issues on G4x... disable it */
4209 I915_WRITE(DSPFW3,
4210 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4211 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4212}
4213
4214static void i965_update_wm(struct drm_device *dev)
4215{
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217 struct drm_crtc *crtc;
4218 int srwm = 1;
4219 int cursor_sr = 16;
4220
4221 /* Calc sr entries for one plane configs */
4222 crtc = single_enabled_crtc(dev);
4223 if (crtc) {
4224 /* self-refresh has much higher latency */
4225 static const int sr_latency_ns = 12000;
4226 int clock = crtc->mode.clock;
4227 int htotal = crtc->mode.htotal;
4228 int hdisplay = crtc->mode.hdisplay;
4229 int pixel_size = crtc->fb->bits_per_pixel / 8;
4230 unsigned long line_time_us;
4231 int entries;
4232
4233 line_time_us = ((htotal * 1000) / clock);
4234
4235 /* Use ns/us then divide to preserve precision */
4236 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4237 pixel_size * hdisplay;
4238 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4239 srwm = I965_FIFO_SIZE - entries;
4240 if (srwm < 0)
4241 srwm = 1;
4242 srwm &= 0x1ff;
4243 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4244 entries, srwm);
4245
4246 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4247 pixel_size * 64;
4248 entries = DIV_ROUND_UP(entries,
4249 i965_cursor_wm_info.cacheline_size);
4250 cursor_sr = i965_cursor_wm_info.fifo_size -
4251 (entries + i965_cursor_wm_info.guard_size);
4252
4253 if (cursor_sr > i965_cursor_wm_info.max_wm)
4254 cursor_sr = i965_cursor_wm_info.max_wm;
4255
4256 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4257 "cursor %d\n", srwm, cursor_sr);
4258
4259 if (IS_CRESTLINE(dev))
4260 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4261 } else {
4262 /* Turn off self refresh if both pipes are enabled */
4263 if (IS_CRESTLINE(dev))
4264 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4265 & ~FW_BLC_SELF_EN);
4266 }
4267
4268 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4269 srwm);
4270
4271 /* 965 has limitations... */
4272 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4273 (8 << 16) | (8 << 8) | (8 << 0));
4274 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4275 /* update cursor SR watermark */
4276 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4277}
4278
4279static void i9xx_update_wm(struct drm_device *dev)
4280{
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282 const struct intel_watermark_params *wm_info;
4283 uint32_t fwater_lo;
4284 uint32_t fwater_hi;
4285 int cwm, srwm = 1;
4286 int fifo_size;
4287 int planea_wm, planeb_wm;
4288 struct drm_crtc *crtc, *enabled = NULL;
4289
4290 if (IS_I945GM(dev))
4291 wm_info = &i945_wm_info;
4292 else if (!IS_GEN2(dev))
4293 wm_info = &i915_wm_info;
4294 else
4295 wm_info = &i855_wm_info;
4296
4297 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4298 crtc = intel_get_crtc_for_plane(dev, 0);
4299 if (crtc->enabled && crtc->fb) {
4300 planea_wm = intel_calculate_wm(crtc->mode.clock,
4301 wm_info, fifo_size,
4302 crtc->fb->bits_per_pixel / 8,
4303 latency_ns);
4304 enabled = crtc;
4305 } else
4306 planea_wm = fifo_size - wm_info->guard_size;
4307
4308 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4309 crtc = intel_get_crtc_for_plane(dev, 1);
4310 if (crtc->enabled && crtc->fb) {
4311 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4312 wm_info, fifo_size,
4313 crtc->fb->bits_per_pixel / 8,
4314 latency_ns);
4315 if (enabled == NULL)
4316 enabled = crtc;
4317 else
4318 enabled = NULL;
4319 } else
4320 planeb_wm = fifo_size - wm_info->guard_size;
4321
4322 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4323
4324 /*
4325 * Overlay gets an aggressive default since video jitter is bad.
4326 */
4327 cwm = 2;
4328
4329 /* Play safe and disable self-refresh before adjusting watermarks. */
4330 if (IS_I945G(dev) || IS_I945GM(dev))
4331 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4332 else if (IS_I915GM(dev))
4333 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4334
4335 /* Calc sr entries for one plane configs */
4336 if (HAS_FW_BLC(dev) && enabled) {
4337 /* self-refresh has much higher latency */
4338 static const int sr_latency_ns = 6000;
4339 int clock = enabled->mode.clock;
4340 int htotal = enabled->mode.htotal;
4341 int hdisplay = enabled->mode.hdisplay;
4342 int pixel_size = enabled->fb->bits_per_pixel / 8;
4343 unsigned long line_time_us;
4344 int entries;
4345
4346 line_time_us = (htotal * 1000) / clock;
4347
4348 /* Use ns/us then divide to preserve precision */
4349 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4350 pixel_size * hdisplay;
4351 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4352 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4353 srwm = wm_info->fifo_size - entries;
4354 if (srwm < 0)
4355 srwm = 1;
4356
4357 if (IS_I945G(dev) || IS_I945GM(dev))
4358 I915_WRITE(FW_BLC_SELF,
4359 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4360 else if (IS_I915GM(dev))
4361 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4362 }
4363
4364 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4365 planea_wm, planeb_wm, cwm, srwm);
4366
4367 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4368 fwater_hi = (cwm & 0x1f);
4369
4370 /* Set request length to 8 cachelines per fetch */
4371 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4372 fwater_hi = fwater_hi | (1 << 8);
4373
4374 I915_WRITE(FW_BLC, fwater_lo);
4375 I915_WRITE(FW_BLC2, fwater_hi);
4376
4377 if (HAS_FW_BLC(dev)) {
4378 if (enabled) {
4379 if (IS_I945G(dev) || IS_I945GM(dev))
4380 I915_WRITE(FW_BLC_SELF,
4381 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4382 else if (IS_I915GM(dev))
4383 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4384 DRM_DEBUG_KMS("memory self refresh enabled\n");
4385 } else
4386 DRM_DEBUG_KMS("memory self refresh disabled\n");
4387 }
4388}
4389
4390static void i830_update_wm(struct drm_device *dev)
4391{
4392 struct drm_i915_private *dev_priv = dev->dev_private;
4393 struct drm_crtc *crtc;
4394 uint32_t fwater_lo;
4395 int planea_wm;
4396
4397 crtc = single_enabled_crtc(dev);
4398 if (crtc == NULL)
4399 return;
4400
4401 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4402 dev_priv->display.get_fifo_size(dev, 0),
4403 crtc->fb->bits_per_pixel / 8,
4404 latency_ns);
4405 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4406 fwater_lo |= (3<<8) | planea_wm;
4407
4408 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4409
4410 I915_WRITE(FW_BLC, fwater_lo);
4411}
4412
4413#define ILK_LP0_PLANE_LATENCY 700
4414#define ILK_LP0_CURSOR_LATENCY 1300
4415
4416/*
4417 * Check the wm result.
4418 *
4419 * If any calculated watermark values is larger than the maximum value that
4420 * can be programmed into the associated watermark register, that watermark
4421 * must be disabled.
4422 */
4423static bool ironlake_check_srwm(struct drm_device *dev, int level,
4424 int fbc_wm, int display_wm, int cursor_wm,
4425 const struct intel_watermark_params *display,
4426 const struct intel_watermark_params *cursor)
4427{
4428 struct drm_i915_private *dev_priv = dev->dev_private;
4429
4430 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4431 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4432
4433 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4434 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4435 fbc_wm, SNB_FBC_MAX_SRWM, level);
4436
4437 /* fbc has it's own way to disable FBC WM */
4438 I915_WRITE(DISP_ARB_CTL,
4439 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4440 return false;
4441 }
4442
4443 if (display_wm > display->max_wm) {
4444 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4445 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4446 return false;
4447 }
4448
4449 if (cursor_wm > cursor->max_wm) {
4450 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4451 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4452 return false;
4453 }
4454
4455 if (!(fbc_wm || display_wm || cursor_wm)) {
4456 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4457 return false;
4458 }
4459
4460 return true;
4461}
4462
4463/*
4464 * Compute watermark values of WM[1-3],
4465 */
4466static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4467 int latency_ns,
4468 const struct intel_watermark_params *display,
4469 const struct intel_watermark_params *cursor,
4470 int *fbc_wm, int *display_wm, int *cursor_wm)
4471{
4472 struct drm_crtc *crtc;
4473 unsigned long line_time_us;
4474 int hdisplay, htotal, pixel_size, clock;
4475 int line_count, line_size;
4476 int small, large;
4477 int entries;
4478
4479 if (!latency_ns) {
4480 *fbc_wm = *display_wm = *cursor_wm = 0;
4481 return false;
4482 }
4483
4484 crtc = intel_get_crtc_for_plane(dev, plane);
4485 hdisplay = crtc->mode.hdisplay;
4486 htotal = crtc->mode.htotal;
4487 clock = crtc->mode.clock;
4488 pixel_size = crtc->fb->bits_per_pixel / 8;
4489
4490 line_time_us = (htotal * 1000) / clock;
4491 line_count = (latency_ns / line_time_us + 1000) / 1000;
4492 line_size = hdisplay * pixel_size;
4493
4494 /* Use the minimum of the small and large buffer method for primary */
4495 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4496 large = line_count * line_size;
4497
4498 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4499 *display_wm = entries + display->guard_size;
4500
4501 /*
4502 * Spec says:
4503 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4504 */
4505 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4506
4507 /* calculate the self-refresh watermark for display cursor */
4508 entries = line_count * pixel_size * 64;
4509 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4510 *cursor_wm = entries + cursor->guard_size;
4511
4512 return ironlake_check_srwm(dev, level,
4513 *fbc_wm, *display_wm, *cursor_wm,
4514 display, cursor);
4515}
4516
4517static void ironlake_update_wm(struct drm_device *dev)
4518{
4519 struct drm_i915_private *dev_priv = dev->dev_private;
4520 int fbc_wm, plane_wm, cursor_wm;
4521 unsigned int enabled;
4522
4523 enabled = 0;
4524 if (g4x_compute_wm0(dev, 0,
4525 &ironlake_display_wm_info,
4526 ILK_LP0_PLANE_LATENCY,
4527 &ironlake_cursor_wm_info,
4528 ILK_LP0_CURSOR_LATENCY,
4529 &plane_wm, &cursor_wm)) {
4530 I915_WRITE(WM0_PIPEA_ILK,
4531 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4532 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4533 " plane %d, " "cursor: %d\n",
4534 plane_wm, cursor_wm);
4535 enabled |= 1;
4536 }
4537
4538 if (g4x_compute_wm0(dev, 1,
4539 &ironlake_display_wm_info,
4540 ILK_LP0_PLANE_LATENCY,
4541 &ironlake_cursor_wm_info,
4542 ILK_LP0_CURSOR_LATENCY,
4543 &plane_wm, &cursor_wm)) {
4544 I915_WRITE(WM0_PIPEB_ILK,
4545 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4546 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4547 " plane %d, cursor: %d\n",
4548 plane_wm, cursor_wm);
4549 enabled |= 2;
4550 }
4551
4552 /*
4553 * Calculate and update the self-refresh watermark only when one
4554 * display plane is used.
4555 */
4556 I915_WRITE(WM3_LP_ILK, 0);
4557 I915_WRITE(WM2_LP_ILK, 0);
4558 I915_WRITE(WM1_LP_ILK, 0);
4559
4560 if (!single_plane_enabled(enabled))
4561 return;
4562 enabled = ffs(enabled) - 1;
4563
4564 /* WM1 */
4565 if (!ironlake_compute_srwm(dev, 1, enabled,
4566 ILK_READ_WM1_LATENCY() * 500,
4567 &ironlake_display_srwm_info,
4568 &ironlake_cursor_srwm_info,
4569 &fbc_wm, &plane_wm, &cursor_wm))
4570 return;
4571
4572 I915_WRITE(WM1_LP_ILK,
4573 WM1_LP_SR_EN |
4574 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4575 (fbc_wm << WM1_LP_FBC_SHIFT) |
4576 (plane_wm << WM1_LP_SR_SHIFT) |
4577 cursor_wm);
4578
4579 /* WM2 */
4580 if (!ironlake_compute_srwm(dev, 2, enabled,
4581 ILK_READ_WM2_LATENCY() * 500,
4582 &ironlake_display_srwm_info,
4583 &ironlake_cursor_srwm_info,
4584 &fbc_wm, &plane_wm, &cursor_wm))
4585 return;
4586
4587 I915_WRITE(WM2_LP_ILK,
4588 WM2_LP_EN |
4589 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4590 (fbc_wm << WM1_LP_FBC_SHIFT) |
4591 (plane_wm << WM1_LP_SR_SHIFT) |
4592 cursor_wm);
4593
4594 /*
4595 * WM3 is unsupported on ILK, probably because we don't have latency
4596 * data for that power state
4597 */
4598}
4599
4600void sandybridge_update_wm(struct drm_device *dev)
4601{
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4604 u32 val;
4605 int fbc_wm, plane_wm, cursor_wm;
4606 unsigned int enabled;
4607
4608 enabled = 0;
4609 if (g4x_compute_wm0(dev, 0,
4610 &sandybridge_display_wm_info, latency,
4611 &sandybridge_cursor_wm_info, latency,
4612 &plane_wm, &cursor_wm)) {
4613 val = I915_READ(WM0_PIPEA_ILK);
4614 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4615 I915_WRITE(WM0_PIPEA_ILK, val |
4616 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4617 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4618 " plane %d, " "cursor: %d\n",
4619 plane_wm, cursor_wm);
4620 enabled |= 1;
4621 }
4622
4623 if (g4x_compute_wm0(dev, 1,
4624 &sandybridge_display_wm_info, latency,
4625 &sandybridge_cursor_wm_info, latency,
4626 &plane_wm, &cursor_wm)) {
4627 val = I915_READ(WM0_PIPEB_ILK);
4628 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4629 I915_WRITE(WM0_PIPEB_ILK, val |
4630 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4631 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4632 " plane %d, cursor: %d\n",
4633 plane_wm, cursor_wm);
4634 enabled |= 2;
4635 }
4636
4637 /* IVB has 3 pipes */
4638 if (IS_IVYBRIDGE(dev) &&
4639 g4x_compute_wm0(dev, 2,
4640 &sandybridge_display_wm_info, latency,
4641 &sandybridge_cursor_wm_info, latency,
4642 &plane_wm, &cursor_wm)) {
4643 val = I915_READ(WM0_PIPEC_IVB);
4644 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4645 I915_WRITE(WM0_PIPEC_IVB, val |
4646 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4647 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4648 " plane %d, cursor: %d\n",
4649 plane_wm, cursor_wm);
4650 enabled |= 3;
4651 }
4652
4653 /*
4654 * Calculate and update the self-refresh watermark only when one
4655 * display plane is used.
4656 *
4657 * SNB support 3 levels of watermark.
4658 *
4659 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4660 * and disabled in the descending order
4661 *
4662 */
4663 I915_WRITE(WM3_LP_ILK, 0);
4664 I915_WRITE(WM2_LP_ILK, 0);
4665 I915_WRITE(WM1_LP_ILK, 0);
4666
4667 if (!single_plane_enabled(enabled) ||
4668 dev_priv->sprite_scaling_enabled)
4669 return;
4670 enabled = ffs(enabled) - 1;
4671
4672 /* WM1 */
4673 if (!ironlake_compute_srwm(dev, 1, enabled,
4674 SNB_READ_WM1_LATENCY() * 500,
4675 &sandybridge_display_srwm_info,
4676 &sandybridge_cursor_srwm_info,
4677 &fbc_wm, &plane_wm, &cursor_wm))
4678 return;
4679
4680 I915_WRITE(WM1_LP_ILK,
4681 WM1_LP_SR_EN |
4682 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4683 (fbc_wm << WM1_LP_FBC_SHIFT) |
4684 (plane_wm << WM1_LP_SR_SHIFT) |
4685 cursor_wm);
4686
4687 /* WM2 */
4688 if (!ironlake_compute_srwm(dev, 2, enabled,
4689 SNB_READ_WM2_LATENCY() * 500,
4690 &sandybridge_display_srwm_info,
4691 &sandybridge_cursor_srwm_info,
4692 &fbc_wm, &plane_wm, &cursor_wm))
4693 return;
4694
4695 I915_WRITE(WM2_LP_ILK,
4696 WM2_LP_EN |
4697 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4698 (fbc_wm << WM1_LP_FBC_SHIFT) |
4699 (plane_wm << WM1_LP_SR_SHIFT) |
4700 cursor_wm);
4701
4702 /* WM3 */
4703 if (!ironlake_compute_srwm(dev, 3, enabled,
4704 SNB_READ_WM3_LATENCY() * 500,
4705 &sandybridge_display_srwm_info,
4706 &sandybridge_cursor_srwm_info,
4707 &fbc_wm, &plane_wm, &cursor_wm))
4708 return;
4709
4710 I915_WRITE(WM3_LP_ILK,
4711 WM3_LP_EN |
4712 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4713 (fbc_wm << WM1_LP_FBC_SHIFT) |
4714 (plane_wm << WM1_LP_SR_SHIFT) |
4715 cursor_wm);
4716}
4717
4718static bool
4719sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4720 uint32_t sprite_width, int pixel_size,
4721 const struct intel_watermark_params *display,
4722 int display_latency_ns, int *sprite_wm)
4723{
4724 struct drm_crtc *crtc;
4725 int clock;
4726 int entries, tlb_miss;
4727
4728 crtc = intel_get_crtc_for_plane(dev, plane);
4729 if (crtc->fb == NULL || !crtc->enabled) {
4730 *sprite_wm = display->guard_size;
4731 return false;
4732 }
4733
4734 clock = crtc->mode.clock;
4735
4736 /* Use the small buffer method to calculate the sprite watermark */
4737 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4738 tlb_miss = display->fifo_size*display->cacheline_size -
4739 sprite_width * 8;
4740 if (tlb_miss > 0)
4741 entries += tlb_miss;
4742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4743 *sprite_wm = entries + display->guard_size;
4744 if (*sprite_wm > (int)display->max_wm)
4745 *sprite_wm = display->max_wm;
4746
4747 return true;
4748}
4749
4750static bool
4751sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4752 uint32_t sprite_width, int pixel_size,
4753 const struct intel_watermark_params *display,
4754 int latency_ns, int *sprite_wm)
4755{
4756 struct drm_crtc *crtc;
4757 unsigned long line_time_us;
4758 int clock;
4759 int line_count, line_size;
4760 int small, large;
4761 int entries;
4762
4763 if (!latency_ns) {
4764 *sprite_wm = 0;
4765 return false;
4766 }
4767
4768 crtc = intel_get_crtc_for_plane(dev, plane);
4769 clock = crtc->mode.clock;
4770 if (!clock) {
4771 *sprite_wm = 0;
4772 return false;
4773 }
4774
4775 line_time_us = (sprite_width * 1000) / clock;
4776 if (!line_time_us) {
4777 *sprite_wm = 0;
4778 return false;
4779 }
4780
4781 line_count = (latency_ns / line_time_us + 1000) / 1000;
4782 line_size = sprite_width * pixel_size;
4783
4784 /* Use the minimum of the small and large buffer method for primary */
4785 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4786 large = line_count * line_size;
4787
4788 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4789 *sprite_wm = entries + display->guard_size;
4790
4791 return *sprite_wm > 0x3ff ? false : true;
4792}
4793
4794static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4795 uint32_t sprite_width, int pixel_size)
4796{
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4799 u32 val;
4800 int sprite_wm, reg;
4801 int ret;
4802
4803 switch (pipe) {
4804 case 0:
4805 reg = WM0_PIPEA_ILK;
4806 break;
4807 case 1:
4808 reg = WM0_PIPEB_ILK;
4809 break;
4810 case 2:
4811 reg = WM0_PIPEC_IVB;
4812 break;
4813 default:
4814 return; /* bad pipe */
4815 }
4816
4817 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4818 &sandybridge_display_wm_info,
4819 latency, &sprite_wm);
4820 if (!ret) {
4821 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4822 pipe);
4823 return;
4824 }
4825
4826 val = I915_READ(reg);
4827 val &= ~WM0_PIPE_SPRITE_MASK;
4828 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4829 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4830
4831
4832 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4833 pixel_size,
4834 &sandybridge_display_srwm_info,
4835 SNB_READ_WM1_LATENCY() * 500,
4836 &sprite_wm);
4837 if (!ret) {
4838 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4839 pipe);
4840 return;
4841 }
4842 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4843
4844 /* Only IVB has two more LP watermarks for sprite */
4845 if (!IS_IVYBRIDGE(dev))
4846 return;
4847
4848 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4849 pixel_size,
4850 &sandybridge_display_srwm_info,
4851 SNB_READ_WM2_LATENCY() * 500,
4852 &sprite_wm);
4853 if (!ret) {
4854 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4855 pipe);
4856 return;
4857 }
4858 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4859
4860 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4861 pixel_size,
4862 &sandybridge_display_srwm_info,
4863 SNB_READ_WM3_LATENCY() * 500,
4864 &sprite_wm);
4865 if (!ret) {
4866 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4867 pipe);
4868 return;
4869 }
4870 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4871}
4872
4873/**
4874 * intel_update_watermarks - update FIFO watermark values based on current modes
4875 *
4876 * Calculate watermark values for the various WM regs based on current mode
4877 * and plane configuration.
4878 *
4879 * There are several cases to deal with here:
4880 * - normal (i.e. non-self-refresh)
4881 * - self-refresh (SR) mode
4882 * - lines are large relative to FIFO size (buffer can hold up to 2)
4883 * - lines are small relative to FIFO size (buffer can hold more than 2
4884 * lines), so need to account for TLB latency
4885 *
4886 * The normal calculation is:
4887 * watermark = dotclock * bytes per pixel * latency
4888 * where latency is platform & configuration dependent (we assume pessimal
4889 * values here).
4890 *
4891 * The SR calculation is:
4892 * watermark = (trunc(latency/line time)+1) * surface width *
4893 * bytes per pixel
4894 * where
4895 * line time = htotal / dotclock
4896 * surface width = hdisplay for normal plane and 64 for cursor
4897 * and latency is assumed to be high, as above.
4898 *
4899 * The final value programmed to the register should always be rounded up,
4900 * and include an extra 2 entries to account for clock crossings.
4901 *
4902 * We don't use the sprite, so we can ignore that. And on Crestline we have
4903 * to set the non-SR watermarks to 8.
4904 */
4905static void intel_update_watermarks(struct drm_device *dev)
4906{
4907 struct drm_i915_private *dev_priv = dev->dev_private;
4908
4909 if (dev_priv->display.update_wm)
4910 dev_priv->display.update_wm(dev);
4911}
4912
4913void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4914 uint32_t sprite_width, int pixel_size)
4915{
4916 struct drm_i915_private *dev_priv = dev->dev_private;
4917
4918 if (dev_priv->display.update_sprite_wm)
4919 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4920 pixel_size);
4921}
4922
4923static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 3522static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4924{ 3523{
4925 if (i915_panel_use_ssc >= 0) 3524 if (i915_panel_use_ssc >= 0)
@@ -5143,6 +3742,222 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5143 } 3742 }
5144} 3743}
5145 3744
3745static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3746 struct drm_display_mode *adjusted_mode)
3747{
3748 struct drm_device *dev = crtc->dev;
3749 struct drm_i915_private *dev_priv = dev->dev_private;
3750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751 int pipe = intel_crtc->pipe;
3752 u32 temp;
3753
3754 temp = I915_READ(LVDS);
3755 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3756 if (pipe == 1) {
3757 temp |= LVDS_PIPEB_SELECT;
3758 } else {
3759 temp &= ~LVDS_PIPEB_SELECT;
3760 }
3761 /* set the corresponsding LVDS_BORDER bit */
3762 temp |= dev_priv->lvds_border_bits;
3763 /* Set the B0-B3 data pairs corresponding to whether we're going to
3764 * set the DPLLs for dual-channel mode or not.
3765 */
3766 if (clock->p2 == 7)
3767 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3768 else
3769 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3770
3771 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3772 * appropriately here, but we need to look more thoroughly into how
3773 * panels behave in the two modes.
3774 */
3775 /* set the dithering flag on LVDS as needed */
3776 if (INTEL_INFO(dev)->gen >= 4) {
3777 if (dev_priv->lvds_dither)
3778 temp |= LVDS_ENABLE_DITHER;
3779 else
3780 temp &= ~LVDS_ENABLE_DITHER;
3781 }
3782 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3783 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3784 temp |= LVDS_HSYNC_POLARITY;
3785 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3786 temp |= LVDS_VSYNC_POLARITY;
3787 I915_WRITE(LVDS, temp);
3788}
3789
3790static void i9xx_update_pll(struct drm_crtc *crtc,
3791 struct drm_display_mode *mode,
3792 struct drm_display_mode *adjusted_mode,
3793 intel_clock_t *clock, intel_clock_t *reduced_clock,
3794 int num_connectors)
3795{
3796 struct drm_device *dev = crtc->dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3799 int pipe = intel_crtc->pipe;
3800 u32 dpll;
3801 bool is_sdvo;
3802
3803 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3804 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3805
3806 dpll = DPLL_VGA_MODE_DIS;
3807
3808 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3809 dpll |= DPLLB_MODE_LVDS;
3810 else
3811 dpll |= DPLLB_MODE_DAC_SERIAL;
3812 if (is_sdvo) {
3813 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3814 if (pixel_multiplier > 1) {
3815 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3816 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3817 }
3818 dpll |= DPLL_DVO_HIGH_SPEED;
3819 }
3820 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3821 dpll |= DPLL_DVO_HIGH_SPEED;
3822
3823 /* compute bitmask from p1 value */
3824 if (IS_PINEVIEW(dev))
3825 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3826 else {
3827 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3828 if (IS_G4X(dev) && reduced_clock)
3829 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3830 }
3831 switch (clock->p2) {
3832 case 5:
3833 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3834 break;
3835 case 7:
3836 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3837 break;
3838 case 10:
3839 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3840 break;
3841 case 14:
3842 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3843 break;
3844 }
3845 if (INTEL_INFO(dev)->gen >= 4)
3846 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3847
3848 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3849 dpll |= PLL_REF_INPUT_TVCLKINBC;
3850 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3851 /* XXX: just matching BIOS for now */
3852 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3853 dpll |= 3;
3854 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3855 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3856 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3857 else
3858 dpll |= PLL_REF_INPUT_DREFCLK;
3859
3860 dpll |= DPLL_VCO_ENABLE;
3861 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3862 POSTING_READ(DPLL(pipe));
3863 udelay(150);
3864
3865 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3866 * This is an exception to the general rule that mode_set doesn't turn
3867 * things on.
3868 */
3869 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3870 intel_update_lvds(crtc, clock, adjusted_mode);
3871
3872 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3873 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3874
3875 I915_WRITE(DPLL(pipe), dpll);
3876
3877 /* Wait for the clocks to stabilize. */
3878 POSTING_READ(DPLL(pipe));
3879 udelay(150);
3880
3881 if (INTEL_INFO(dev)->gen >= 4) {
3882 u32 temp = 0;
3883 if (is_sdvo) {
3884 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3885 if (temp > 1)
3886 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3887 else
3888 temp = 0;
3889 }
3890 I915_WRITE(DPLL_MD(pipe), temp);
3891 } else {
3892 /* The pixel multiplier can only be updated once the
3893 * DPLL is enabled and the clocks are stable.
3894 *
3895 * So write it again.
3896 */
3897 I915_WRITE(DPLL(pipe), dpll);
3898 }
3899}
3900
3901static void i8xx_update_pll(struct drm_crtc *crtc,
3902 struct drm_display_mode *adjusted_mode,
3903 intel_clock_t *clock,
3904 int num_connectors)
3905{
3906 struct drm_device *dev = crtc->dev;
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3909 int pipe = intel_crtc->pipe;
3910 u32 dpll;
3911
3912 dpll = DPLL_VGA_MODE_DIS;
3913
3914 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3915 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3916 } else {
3917 if (clock->p1 == 2)
3918 dpll |= PLL_P1_DIVIDE_BY_TWO;
3919 else
3920 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3921 if (clock->p2 == 4)
3922 dpll |= PLL_P2_DIVIDE_BY_4;
3923 }
3924
3925 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3926 /* XXX: just matching BIOS for now */
3927 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3928 dpll |= 3;
3929 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3930 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3931 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3932 else
3933 dpll |= PLL_REF_INPUT_DREFCLK;
3934
3935 dpll |= DPLL_VCO_ENABLE;
3936 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3937 POSTING_READ(DPLL(pipe));
3938 udelay(150);
3939
3940 I915_WRITE(DPLL(pipe), dpll);
3941
3942 /* Wait for the clocks to stabilize. */
3943 POSTING_READ(DPLL(pipe));
3944 udelay(150);
3945
3946 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3947 * This is an exception to the general rule that mode_set doesn't turn
3948 * things on.
3949 */
3950 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3951 intel_update_lvds(crtc, clock, adjusted_mode);
3952
3953 /* The pixel multiplier can only be updated once the
3954 * DPLL is enabled and the clocks are stable.
3955 *
3956 * So write it again.
3957 */
3958 I915_WRITE(DPLL(pipe), dpll);
3959}
3960
5146static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 3961static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5147 struct drm_display_mode *mode, 3962 struct drm_display_mode *mode,
5148 struct drm_display_mode *adjusted_mode, 3963 struct drm_display_mode *adjusted_mode,
@@ -5156,15 +3971,13 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5156 int plane = intel_crtc->plane; 3971 int plane = intel_crtc->plane;
5157 int refclk, num_connectors = 0; 3972 int refclk, num_connectors = 0;
5158 intel_clock_t clock, reduced_clock; 3973 intel_clock_t clock, reduced_clock;
5159 u32 dpll, dspcntr, pipeconf, vsyncshift; 3974 u32 dspcntr, pipeconf, vsyncshift;
5160 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 3975 bool ok, has_reduced_clock = false, is_sdvo = false;
5161 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3976 bool is_lvds = false, is_tv = false, is_dp = false;
5162 struct drm_mode_config *mode_config = &dev->mode_config; 3977 struct drm_mode_config *mode_config = &dev->mode_config;
5163 struct intel_encoder *encoder; 3978 struct intel_encoder *encoder;
5164 const intel_limit_t *limit; 3979 const intel_limit_t *limit;
5165 int ret; 3980 int ret;
5166 u32 temp;
5167 u32 lvds_sync = 0;
5168 3981
5169 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 3982 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5170 if (encoder->base.crtc != crtc) 3983 if (encoder->base.crtc != crtc)
@@ -5180,15 +3993,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5180 if (encoder->needs_tv_clock) 3993 if (encoder->needs_tv_clock)
5181 is_tv = true; 3994 is_tv = true;
5182 break; 3995 break;
5183 case INTEL_OUTPUT_DVO:
5184 is_dvo = true;
5185 break;
5186 case INTEL_OUTPUT_TVOUT: 3996 case INTEL_OUTPUT_TVOUT:
5187 is_tv = true; 3997 is_tv = true;
5188 break; 3998 break;
5189 case INTEL_OUTPUT_ANALOG:
5190 is_crt = true;
5191 break;
5192 case INTEL_OUTPUT_DISPLAYPORT: 3999 case INTEL_OUTPUT_DISPLAYPORT:
5193 is_dp = true; 4000 is_dp = true;
5194 break; 4001 break;
@@ -5235,71 +4042,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5235 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? 4042 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5236 &reduced_clock : NULL); 4043 &reduced_clock : NULL);
5237 4044
5238 dpll = DPLL_VGA_MODE_DIS; 4045 if (IS_GEN2(dev))
5239 4046 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
5240 if (!IS_GEN2(dev)) {
5241 if (is_lvds)
5242 dpll |= DPLLB_MODE_LVDS;
5243 else
5244 dpll |= DPLLB_MODE_DAC_SERIAL;
5245 if (is_sdvo) {
5246 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5247 if (pixel_multiplier > 1) {
5248 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5249 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5250 }
5251 dpll |= DPLL_DVO_HIGH_SPEED;
5252 }
5253 if (is_dp)
5254 dpll |= DPLL_DVO_HIGH_SPEED;
5255
5256 /* compute bitmask from p1 value */
5257 if (IS_PINEVIEW(dev))
5258 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5259 else {
5260 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5261 if (IS_G4X(dev) && has_reduced_clock)
5262 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5263 }
5264 switch (clock.p2) {
5265 case 5:
5266 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5267 break;
5268 case 7:
5269 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5270 break;
5271 case 10:
5272 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5273 break;
5274 case 14:
5275 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5276 break;
5277 }
5278 if (INTEL_INFO(dev)->gen >= 4)
5279 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5280 } else {
5281 if (is_lvds) {
5282 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5283 } else {
5284 if (clock.p1 == 2)
5285 dpll |= PLL_P1_DIVIDE_BY_TWO;
5286 else
5287 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5288 if (clock.p2 == 4)
5289 dpll |= PLL_P2_DIVIDE_BY_4;
5290 }
5291 }
5292
5293 if (is_sdvo && is_tv)
5294 dpll |= PLL_REF_INPUT_TVCLKINBC;
5295 else if (is_tv)
5296 /* XXX: just matching BIOS for now */
5297 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5298 dpll |= 3;
5299 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5300 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5301 else 4047 else
5302 dpll |= PLL_REF_INPUT_DREFCLK; 4048 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4049 has_reduced_clock ? &reduced_clock : NULL,
4050 num_connectors);
5303 4051
5304 /* setup pipeconf */ 4052 /* setup pipeconf */
5305 pipeconf = I915_READ(PIPECONF(pipe)); 4053 pipeconf = I915_READ(PIPECONF(pipe));
@@ -5336,97 +4084,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5336 } 4084 }
5337 } 4085 }
5338 4086
5339 dpll |= DPLL_VCO_ENABLE;
5340
5341 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 4087 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5342 drm_mode_debug_printmodeline(mode); 4088 drm_mode_debug_printmodeline(mode);
5343 4089
5344 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5345
5346 POSTING_READ(DPLL(pipe));
5347 udelay(150);
5348
5349 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5350 * This is an exception to the general rule that mode_set doesn't turn
5351 * things on.
5352 */
5353 if (is_lvds) {
5354 temp = I915_READ(LVDS);
5355 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5356 if (pipe == 1) {
5357 temp |= LVDS_PIPEB_SELECT;
5358 } else {
5359 temp &= ~LVDS_PIPEB_SELECT;
5360 }
5361 /* set the corresponsding LVDS_BORDER bit */
5362 temp |= dev_priv->lvds_border_bits;
5363 /* Set the B0-B3 data pairs corresponding to whether we're going to
5364 * set the DPLLs for dual-channel mode or not.
5365 */
5366 if (clock.p2 == 7)
5367 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5368 else
5369 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5370
5371 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5372 * appropriately here, but we need to look more thoroughly into how
5373 * panels behave in the two modes.
5374 */
5375 /* set the dithering flag on LVDS as needed */
5376 if (INTEL_INFO(dev)->gen >= 4) {
5377 if (dev_priv->lvds_dither)
5378 temp |= LVDS_ENABLE_DITHER;
5379 else
5380 temp &= ~LVDS_ENABLE_DITHER;
5381 }
5382 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5383 lvds_sync |= LVDS_HSYNC_POLARITY;
5384 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5385 lvds_sync |= LVDS_VSYNC_POLARITY;
5386 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5387 != lvds_sync) {
5388 char flags[2] = "-+";
5389 DRM_INFO("Changing LVDS panel from "
5390 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5391 flags[!(temp & LVDS_HSYNC_POLARITY)],
5392 flags[!(temp & LVDS_VSYNC_POLARITY)],
5393 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5394 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5395 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5396 temp |= lvds_sync;
5397 }
5398 I915_WRITE(LVDS, temp);
5399 }
5400
5401 if (is_dp) {
5402 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5403 }
5404
5405 I915_WRITE(DPLL(pipe), dpll);
5406
5407 /* Wait for the clocks to stabilize. */
5408 POSTING_READ(DPLL(pipe));
5409 udelay(150);
5410
5411 if (INTEL_INFO(dev)->gen >= 4) {
5412 temp = 0;
5413 if (is_sdvo) {
5414 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5415 if (temp > 1)
5416 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5417 else
5418 temp = 0;
5419 }
5420 I915_WRITE(DPLL_MD(pipe), temp);
5421 } else {
5422 /* The pixel multiplier can only be updated once the
5423 * DPLL is enabled and the clocks are stable.
5424 *
5425 * So write it again.
5426 */
5427 I915_WRITE(DPLL(pipe), dpll);
5428 }
5429
5430 if (HAS_PIPE_CXSR(dev)) { 4090 if (HAS_PIPE_CXSR(dev)) {
5431 if (intel_crtc->lowfreq_avail) { 4091 if (intel_crtc->lowfreq_avail) {
5432 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 4092 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
@@ -5492,7 +4152,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5492 4152
5493 I915_WRITE(DSPCNTR(plane), dspcntr); 4153 I915_WRITE(DSPCNTR(plane), dspcntr);
5494 POSTING_READ(DSPCNTR(plane)); 4154 POSTING_READ(DSPCNTR(plane));
5495 intel_enable_plane(dev_priv, plane, pipe);
5496 4155
5497 ret = intel_pipe_set_base(crtc, x, y, old_fb); 4156 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5498 4157
@@ -5668,17 +4327,16 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5668 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; 4327 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5669 bool ok, has_reduced_clock = false, is_sdvo = false; 4328 bool ok, has_reduced_clock = false, is_sdvo = false;
5670 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 4329 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5671 struct intel_encoder *has_edp_encoder = NULL;
5672 struct drm_mode_config *mode_config = &dev->mode_config; 4330 struct drm_mode_config *mode_config = &dev->mode_config;
5673 struct intel_encoder *encoder; 4331 struct intel_encoder *encoder, *edp_encoder = NULL;
5674 const intel_limit_t *limit; 4332 const intel_limit_t *limit;
5675 int ret; 4333 int ret;
5676 struct fdi_m_n m_n = {0}; 4334 struct fdi_m_n m_n = {0};
5677 u32 temp; 4335 u32 temp;
5678 u32 lvds_sync = 0;
5679 int target_clock, pixel_multiplier, lane, link_bw, factor; 4336 int target_clock, pixel_multiplier, lane, link_bw, factor;
5680 unsigned int pipe_bpp; 4337 unsigned int pipe_bpp;
5681 bool dither; 4338 bool dither;
4339 bool is_cpu_edp = false, is_pch_edp = false;
5682 4340
5683 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 4341 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5684 if (encoder->base.crtc != crtc) 4342 if (encoder->base.crtc != crtc)
@@ -5704,7 +4362,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5704 is_dp = true; 4362 is_dp = true;
5705 break; 4363 break;
5706 case INTEL_OUTPUT_EDP: 4364 case INTEL_OUTPUT_EDP:
5707 has_edp_encoder = encoder; 4365 is_dp = true;
4366 if (intel_encoder_is_pch_edp(&encoder->base))
4367 is_pch_edp = true;
4368 else
4369 is_cpu_edp = true;
4370 edp_encoder = encoder;
5708 break; 4371 break;
5709 } 4372 }
5710 4373
@@ -5767,15 +4430,13 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5767 lane = 0; 4430 lane = 0;
5768 /* CPU eDP doesn't require FDI link, so just set DP M/N 4431 /* CPU eDP doesn't require FDI link, so just set DP M/N
5769 according to current link config */ 4432 according to current link config */
5770 if (has_edp_encoder && 4433 if (is_cpu_edp) {
5771 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5772 target_clock = mode->clock; 4434 target_clock = mode->clock;
5773 intel_edp_link_config(has_edp_encoder, 4435 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5774 &lane, &link_bw);
5775 } else { 4436 } else {
5776 /* [e]DP over FDI requires target mode clock 4437 /* [e]DP over FDI requires target mode clock
5777 instead of link clock */ 4438 instead of link clock */
5778 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) 4439 if (is_dp)
5779 target_clock = mode->clock; 4440 target_clock = mode->clock;
5780 else 4441 else
5781 target_clock = adjusted_mode->clock; 4442 target_clock = adjusted_mode->clock;
@@ -5866,7 +4527,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5866 } 4527 }
5867 dpll |= DPLL_DVO_HIGH_SPEED; 4528 dpll |= DPLL_DVO_HIGH_SPEED;
5868 } 4529 }
5869 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) 4530 if (is_dp && !is_cpu_edp)
5870 dpll |= DPLL_DVO_HIGH_SPEED; 4531 dpll |= DPLL_DVO_HIGH_SPEED;
5871 4532
5872 /* compute bitmask from p1 value */ 4533 /* compute bitmask from p1 value */
@@ -5909,30 +4570,22 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5909 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 4570 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5910 drm_mode_debug_printmodeline(mode); 4571 drm_mode_debug_printmodeline(mode);
5911 4572
5912 /* PCH eDP needs FDI, but CPU eDP does not */ 4573 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
5913 if (!intel_crtc->no_pll) { 4574 * pre-Haswell/LPT generation */
5914 if (!has_edp_encoder || 4575 if (HAS_PCH_LPT(dev)) {
5915 intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4576 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
5916 I915_WRITE(PCH_FP0(pipe), fp); 4577 pipe);
5917 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 4578 } else if (!is_cpu_edp) {
5918 4579 struct intel_pch_pll *pll;
5919 POSTING_READ(PCH_DPLL(pipe)); 4580
5920 udelay(150); 4581 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5921 } 4582 if (pll == NULL) {
5922 } else { 4583 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5923 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) && 4584 pipe);
5924 fp == I915_READ(PCH_FP0(0))) {
5925 intel_crtc->use_pll_a = true;
5926 DRM_DEBUG_KMS("using pipe a dpll\n");
5927 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5928 fp == I915_READ(PCH_FP0(1))) {
5929 intel_crtc->use_pll_a = false;
5930 DRM_DEBUG_KMS("using pipe b dpll\n");
5931 } else {
5932 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5933 return -EINVAL; 4585 return -EINVAL;
5934 } 4586 }
5935 } 4587 } else
4588 intel_put_pch_pll(intel_crtc);
5936 4589
5937 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 4590 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5938 * This is an exception to the general rule that mode_set doesn't turn 4591 * This is an exception to the general rule that mode_set doesn't turn
@@ -5965,22 +4618,11 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5965 * appropriately here, but we need to look more thoroughly into how 4618 * appropriately here, but we need to look more thoroughly into how
5966 * panels behave in the two modes. 4619 * panels behave in the two modes.
5967 */ 4620 */
4621 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5968 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 4622 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5969 lvds_sync |= LVDS_HSYNC_POLARITY; 4623 temp |= LVDS_HSYNC_POLARITY;
5970 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 4624 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5971 lvds_sync |= LVDS_VSYNC_POLARITY; 4625 temp |= LVDS_VSYNC_POLARITY;
5972 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5973 != lvds_sync) {
5974 char flags[2] = "-+";
5975 DRM_INFO("Changing LVDS panel from "
5976 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5977 flags[!(temp & LVDS_HSYNC_POLARITY)],
5978 flags[!(temp & LVDS_VSYNC_POLARITY)],
5979 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5980 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5981 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5982 temp |= lvds_sync;
5983 }
5984 I915_WRITE(PCH_LVDS, temp); 4626 I915_WRITE(PCH_LVDS, temp);
5985 } 4627 }
5986 4628
@@ -5990,7 +4632,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5990 pipeconf |= PIPECONF_DITHER_EN; 4632 pipeconf |= PIPECONF_DITHER_EN;
5991 pipeconf |= PIPECONF_DITHER_TYPE_SP; 4633 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5992 } 4634 }
5993 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4635 if (is_dp && !is_cpu_edp) {
5994 intel_dp_set_m_n(crtc, mode, adjusted_mode); 4636 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5995 } else { 4637 } else {
5996 /* For non-DP output, clear any trans DP clock recovery setting.*/ 4638 /* For non-DP output, clear any trans DP clock recovery setting.*/
@@ -6000,13 +4642,11 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6000 I915_WRITE(TRANSDPLINK_N1(pipe), 0); 4642 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6001 } 4643 }
6002 4644
6003 if (!intel_crtc->no_pll && 4645 if (intel_crtc->pch_pll) {
6004 (!has_edp_encoder || 4646 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
6005 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6006 I915_WRITE(PCH_DPLL(pipe), dpll);
6007 4647
6008 /* Wait for the clocks to stabilize. */ 4648 /* Wait for the clocks to stabilize. */
6009 POSTING_READ(PCH_DPLL(pipe)); 4649 POSTING_READ(intel_crtc->pch_pll->pll_reg);
6010 udelay(150); 4650 udelay(150);
6011 4651
6012 /* The pixel multiplier can only be updated once the 4652 /* The pixel multiplier can only be updated once the
@@ -6014,20 +4654,20 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6014 * 4654 *
6015 * So write it again. 4655 * So write it again.
6016 */ 4656 */
6017 I915_WRITE(PCH_DPLL(pipe), dpll); 4657 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
6018 } 4658 }
6019 4659
6020 intel_crtc->lowfreq_avail = false; 4660 intel_crtc->lowfreq_avail = false;
6021 if (!intel_crtc->no_pll) { 4661 if (intel_crtc->pch_pll) {
6022 if (is_lvds && has_reduced_clock && i915_powersave) { 4662 if (is_lvds && has_reduced_clock && i915_powersave) {
6023 I915_WRITE(PCH_FP1(pipe), fp2); 4663 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
6024 intel_crtc->lowfreq_avail = true; 4664 intel_crtc->lowfreq_avail = true;
6025 if (HAS_PIPE_CXSR(dev)) { 4665 if (HAS_PIPE_CXSR(dev)) {
6026 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 4666 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6027 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 4667 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6028 } 4668 }
6029 } else { 4669 } else {
6030 I915_WRITE(PCH_FP1(pipe), fp); 4670 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
6031 if (HAS_PIPE_CXSR(dev)) { 4671 if (HAS_PIPE_CXSR(dev)) {
6032 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 4672 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6033 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 4673 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
@@ -6080,10 +4720,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6080 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); 4720 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6081 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); 4721 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6082 4722
6083 if (has_edp_encoder && 4723 if (is_cpu_edp)
6084 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6085 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 4724 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6086 }
6087 4725
6088 I915_WRITE(PIPECONF(pipe), pipeconf); 4726 I915_WRITE(PIPECONF(pipe), pipeconf);
6089 POSTING_READ(PIPECONF(pipe)); 4727 POSTING_READ(PIPECONF(pipe));
@@ -6097,6 +4735,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6097 4735
6098 intel_update_watermarks(dev); 4736 intel_update_watermarks(dev);
6099 4737
4738 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4739
6100 return ret; 4740 return ret;
6101} 4741}
6102 4742
@@ -6451,7 +5091,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6451 if (!visible && !intel_crtc->cursor_visible) 5091 if (!visible && !intel_crtc->cursor_visible)
6452 return; 5092 return;
6453 5093
6454 if (IS_IVYBRIDGE(dev)) { 5094 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6455 I915_WRITE(CURPOS_IVB(pipe), pos); 5095 I915_WRITE(CURPOS_IVB(pipe), pos);
6456 ivb_update_cursor(crtc, base); 5096 ivb_update_cursor(crtc, base);
6457 } else { 5097 } else {
@@ -6461,9 +5101,6 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6461 else 5101 else
6462 i9xx_update_cursor(crtc, base); 5102 i9xx_update_cursor(crtc, base);
6463 } 5103 }
6464
6465 if (visible)
6466 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6467} 5104}
6468 5105
6469static int intel_crtc_cursor_set(struct drm_crtc *crtc, 5106static int intel_crtc_cursor_set(struct drm_crtc *crtc,
@@ -6987,7 +5624,6 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6987 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 5624 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6988 5625
6989 drm_mode_set_name(mode); 5626 drm_mode_set_name(mode);
6990 drm_mode_set_crtcinfo(mode, 0);
6991 5627
6992 return mode; 5628 return mode;
6993} 5629}
@@ -7086,7 +5722,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
7086 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 5722 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7087 int pipe = intel_crtc->pipe; 5723 int pipe = intel_crtc->pipe;
7088 int dpll_reg = DPLL(pipe); 5724 int dpll_reg = DPLL(pipe);
7089 u32 dpll; 5725 int dpll;
7090 5726
7091 DRM_DEBUG_DRIVER("downclocking LVDS\n"); 5727 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7092 5728
@@ -7100,6 +5736,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
7100 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 5736 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7101 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); 5737 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7102 } 5738 }
5739
7103} 5740}
7104 5741
7105/** 5742/**
@@ -7158,12 +5795,16 @@ void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7158 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 5795 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7159 return; 5796 return;
7160 5797
7161 if (!dev_priv->busy) 5798 if (!dev_priv->busy) {
5799 intel_sanitize_pm(dev);
7162 dev_priv->busy = true; 5800 dev_priv->busy = true;
7163 else 5801 } else
7164 mod_timer(&dev_priv->idle_timer, jiffies + 5802 mod_timer(&dev_priv->idle_timer, jiffies +
7165 msecs_to_jiffies(GPU_IDLE_TIMEOUT)); 5803 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7166 5804
5805 if (obj == NULL)
5806 return;
5807
7167 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5808 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7168 if (!crtc->fb) 5809 if (!crtc->fb)
7169 continue; 5810 continue;
@@ -7336,18 +5977,19 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
7336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7337 unsigned long offset; 5978 unsigned long offset;
7338 u32 flip_mask; 5979 u32 flip_mask;
5980 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7339 int ret; 5981 int ret;
7340 5982
7341 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5983 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7342 if (ret) 5984 if (ret)
7343 goto out; 5985 goto err;
7344 5986
7345 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5987 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7346 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; 5988 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7347 5989
7348 ret = BEGIN_LP_RING(6); 5990 ret = intel_ring_begin(ring, 6);
7349 if (ret) 5991 if (ret)
7350 goto out; 5992 goto err_unpin;
7351 5993
7352 /* Can't queue multiple flips, so wait for the previous 5994 /* Can't queue multiple flips, so wait for the previous
7353 * one to finish before executing the next. 5995 * one to finish before executing the next.
@@ -7356,15 +5998,19 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
7356 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 5998 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7357 else 5999 else
7358 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 6000 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7359 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); 6001 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7360 OUT_RING(MI_NOOP); 6002 intel_ring_emit(ring, MI_NOOP);
7361 OUT_RING(MI_DISPLAY_FLIP | 6003 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7362 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 6004 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7363 OUT_RING(fb->pitches[0]); 6005 intel_ring_emit(ring, fb->pitches[0]);
7364 OUT_RING(obj->gtt_offset + offset); 6006 intel_ring_emit(ring, obj->gtt_offset + offset);
7365 OUT_RING(0); /* aux display base address, unused */ 6007 intel_ring_emit(ring, 0); /* aux display base address, unused */
7366 ADVANCE_LP_RING(); 6008 intel_ring_advance(ring);
7367out: 6009 return 0;
6010
6011err_unpin:
6012 intel_unpin_fb_obj(obj);
6013err:
7368 return ret; 6014 return ret;
7369} 6015}
7370 6016
@@ -7377,33 +6023,38 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
7377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7378 unsigned long offset; 6024 unsigned long offset;
7379 u32 flip_mask; 6025 u32 flip_mask;
6026 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7380 int ret; 6027 int ret;
7381 6028
7382 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 6029 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7383 if (ret) 6030 if (ret)
7384 goto out; 6031 goto err;
7385 6032
7386 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 6033 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7387 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; 6034 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7388 6035
7389 ret = BEGIN_LP_RING(6); 6036 ret = intel_ring_begin(ring, 6);
7390 if (ret) 6037 if (ret)
7391 goto out; 6038 goto err_unpin;
7392 6039
7393 if (intel_crtc->plane) 6040 if (intel_crtc->plane)
7394 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 6041 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7395 else 6042 else
7396 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 6043 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7397 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); 6044 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7398 OUT_RING(MI_NOOP); 6045 intel_ring_emit(ring, MI_NOOP);
7399 OUT_RING(MI_DISPLAY_FLIP_I915 | 6046 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7400 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 6047 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7401 OUT_RING(fb->pitches[0]); 6048 intel_ring_emit(ring, fb->pitches[0]);
7402 OUT_RING(obj->gtt_offset + offset); 6049 intel_ring_emit(ring, obj->gtt_offset + offset);
7403 OUT_RING(MI_NOOP); 6050 intel_ring_emit(ring, MI_NOOP);
7404 6051
7405 ADVANCE_LP_RING(); 6052 intel_ring_advance(ring);
7406out: 6053 return 0;
6054
6055err_unpin:
6056 intel_unpin_fb_obj(obj);
6057err:
7407 return ret; 6058 return ret;
7408} 6059}
7409 6060
@@ -7415,24 +6066,25 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
7415 struct drm_i915_private *dev_priv = dev->dev_private; 6066 struct drm_i915_private *dev_priv = dev->dev_private;
7416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7417 uint32_t pf, pipesrc; 6068 uint32_t pf, pipesrc;
6069 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7418 int ret; 6070 int ret;
7419 6071
7420 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 6072 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7421 if (ret) 6073 if (ret)
7422 goto out; 6074 goto err;
7423 6075
7424 ret = BEGIN_LP_RING(4); 6076 ret = intel_ring_begin(ring, 4);
7425 if (ret) 6077 if (ret)
7426 goto out; 6078 goto err_unpin;
7427 6079
7428 /* i965+ uses the linear or tiled offsets from the 6080 /* i965+ uses the linear or tiled offsets from the
7429 * Display Registers (which do not change across a page-flip) 6081 * Display Registers (which do not change across a page-flip)
7430 * so we need only reprogram the base address. 6082 * so we need only reprogram the base address.
7431 */ 6083 */
7432 OUT_RING(MI_DISPLAY_FLIP | 6084 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7433 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 6085 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7434 OUT_RING(fb->pitches[0]); 6086 intel_ring_emit(ring, fb->pitches[0]);
7435 OUT_RING(obj->gtt_offset | obj->tiling_mode); 6087 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
7436 6088
7437 /* XXX Enabling the panel-fitter across page-flip is so far 6089 /* XXX Enabling the panel-fitter across page-flip is so far
7438 * untested on non-native modes, so ignore it for now. 6090 * untested on non-native modes, so ignore it for now.
@@ -7440,9 +6092,13 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
7440 */ 6092 */
7441 pf = 0; 6093 pf = 0;
7442 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 6094 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7443 OUT_RING(pf | pipesrc); 6095 intel_ring_emit(ring, pf | pipesrc);
7444 ADVANCE_LP_RING(); 6096 intel_ring_advance(ring);
7445out: 6097 return 0;
6098
6099err_unpin:
6100 intel_unpin_fb_obj(obj);
6101err:
7446 return ret; 6102 return ret;
7447} 6103}
7448 6104
@@ -7453,21 +6109,22 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
7453{ 6109{
7454 struct drm_i915_private *dev_priv = dev->dev_private; 6110 struct drm_i915_private *dev_priv = dev->dev_private;
7455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6112 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7456 uint32_t pf, pipesrc; 6113 uint32_t pf, pipesrc;
7457 int ret; 6114 int ret;
7458 6115
7459 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 6116 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7460 if (ret) 6117 if (ret)
7461 goto out; 6118 goto err;
7462 6119
7463 ret = BEGIN_LP_RING(4); 6120 ret = intel_ring_begin(ring, 4);
7464 if (ret) 6121 if (ret)
7465 goto out; 6122 goto err_unpin;
7466 6123
7467 OUT_RING(MI_DISPLAY_FLIP | 6124 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7468 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 6125 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7469 OUT_RING(fb->pitches[0] | obj->tiling_mode); 6126 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7470 OUT_RING(obj->gtt_offset); 6127 intel_ring_emit(ring, obj->gtt_offset);
7471 6128
7472 /* Contrary to the suggestions in the documentation, 6129 /* Contrary to the suggestions in the documentation,
7473 * "Enable Panel Fitter" does not seem to be required when page 6130 * "Enable Panel Fitter" does not seem to be required when page
@@ -7477,9 +6134,13 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
7477 */ 6134 */
7478 pf = 0; 6135 pf = 0;
7479 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 6136 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7480 OUT_RING(pf | pipesrc); 6137 intel_ring_emit(ring, pf | pipesrc);
7481 ADVANCE_LP_RING(); 6138 intel_ring_advance(ring);
7482out: 6139 return 0;
6140
6141err_unpin:
6142 intel_unpin_fb_obj(obj);
6143err:
7483 return ret; 6144 return ret;
7484} 6145}
7485 6146
@@ -7497,22 +6158,43 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
7497 struct drm_i915_private *dev_priv = dev->dev_private; 6158 struct drm_i915_private *dev_priv = dev->dev_private;
7498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7499 struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; 6160 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6161 uint32_t plane_bit = 0;
7500 int ret; 6162 int ret;
7501 6163
7502 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 6164 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7503 if (ret) 6165 if (ret)
7504 goto out; 6166 goto err;
6167
6168 switch(intel_crtc->plane) {
6169 case PLANE_A:
6170 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6171 break;
6172 case PLANE_B:
6173 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6174 break;
6175 case PLANE_C:
6176 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6177 break;
6178 default:
6179 WARN_ONCE(1, "unknown plane in flip command\n");
6180 ret = -ENODEV;
6181 goto err;
6182 }
7505 6183
7506 ret = intel_ring_begin(ring, 4); 6184 ret = intel_ring_begin(ring, 4);
7507 if (ret) 6185 if (ret)
7508 goto out; 6186 goto err_unpin;
7509 6187
7510 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); 6188 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7511 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); 6189 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7512 intel_ring_emit(ring, (obj->gtt_offset)); 6190 intel_ring_emit(ring, (obj->gtt_offset));
7513 intel_ring_emit(ring, (MI_NOOP)); 6191 intel_ring_emit(ring, (MI_NOOP));
7514 intel_ring_advance(ring); 6192 intel_ring_advance(ring);
7515out: 6193 return 0;
6194
6195err_unpin:
6196 intel_unpin_fb_obj(obj);
6197err:
7516 return ret; 6198 return ret;
7517} 6199}
7518 6200
@@ -7589,6 +6271,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
7589 goto cleanup_pending; 6271 goto cleanup_pending;
7590 6272
7591 intel_disable_fbc(dev); 6273 intel_disable_fbc(dev);
6274 intel_mark_busy(dev, obj);
7592 mutex_unlock(&dev->struct_mutex); 6275 mutex_unlock(&dev->struct_mutex);
7593 6276
7594 trace_i915_flip_request(intel_crtc->plane, obj); 6277 trace_i915_flip_request(intel_crtc->plane, obj);
@@ -7617,10 +6300,11 @@ static void intel_sanitize_modesetting(struct drm_device *dev,
7617{ 6300{
7618 struct drm_i915_private *dev_priv = dev->dev_private; 6301 struct drm_i915_private *dev_priv = dev->dev_private;
7619 u32 reg, val; 6302 u32 reg, val;
6303 int i;
7620 6304
7621 /* Clear any frame start delays used for debugging left by the BIOS */ 6305 /* Clear any frame start delays used for debugging left by the BIOS */
7622 for_each_pipe(pipe) { 6306 for_each_pipe(i) {
7623 reg = PIPECONF(pipe); 6307 reg = PIPECONF(i);
7624 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 6308 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7625 } 6309 }
7626 6310
@@ -7690,6 +6374,23 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
7690 .page_flip = intel_crtc_page_flip, 6374 .page_flip = intel_crtc_page_flip,
7691}; 6375};
7692 6376
6377static void intel_pch_pll_init(struct drm_device *dev)
6378{
6379 drm_i915_private_t *dev_priv = dev->dev_private;
6380 int i;
6381
6382 if (dev_priv->num_pch_pll == 0) {
6383 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6384 return;
6385 }
6386
6387 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6388 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6389 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6390 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6391 }
6392}
6393
7693static void intel_crtc_init(struct drm_device *dev, int pipe) 6394static void intel_crtc_init(struct drm_device *dev, int pipe)
7694{ 6395{
7695 drm_i915_private_t *dev_priv = dev->dev_private; 6396 drm_i915_private_t *dev_priv = dev->dev_private;
@@ -7727,8 +6428,6 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
7727 intel_crtc->bpp = 24; /* default for pre-Ironlake */ 6428 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7728 6429
7729 if (HAS_PCH_SPLIT(dev)) { 6430 if (HAS_PCH_SPLIT(dev)) {
7730 if (pipe == 2 && IS_IVYBRIDGE(dev))
7731 intel_crtc->no_pll = true;
7732 intel_helper_funcs.prepare = ironlake_crtc_prepare; 6431 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7733 intel_helper_funcs.commit = ironlake_crtc_commit; 6432 intel_helper_funcs.commit = ironlake_crtc_commit;
7734 } else { 6433 } else {
@@ -7747,15 +6446,12 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
7747int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 6446int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7748 struct drm_file *file) 6447 struct drm_file *file)
7749{ 6448{
7750 drm_i915_private_t *dev_priv = dev->dev_private;
7751 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 6449 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7752 struct drm_mode_object *drmmode_obj; 6450 struct drm_mode_object *drmmode_obj;
7753 struct intel_crtc *crtc; 6451 struct intel_crtc *crtc;
7754 6452
7755 if (!dev_priv) { 6453 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7756 DRM_ERROR("called with no initialization\n"); 6454 return -ENODEV;
7757 return -EINVAL;
7758 }
7759 6455
7760 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, 6456 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7761 DRM_MODE_OBJECT_CRTC); 6457 DRM_MODE_OBJECT_CRTC);
@@ -7828,12 +6524,31 @@ static void intel_setup_outputs(struct drm_device *dev)
7828 6524
7829 intel_crt_init(dev); 6525 intel_crt_init(dev);
7830 6526
7831 if (HAS_PCH_SPLIT(dev)) { 6527 if (IS_HASWELL(dev)) {
6528 int found;
6529
6530 /* Haswell uses DDI functions to detect digital outputs */
6531 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6532 /* DDI A only supports eDP */
6533 if (found)
6534 intel_ddi_init(dev, PORT_A);
6535
6536 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6537 * register */
6538 found = I915_READ(SFUSE_STRAP);
6539
6540 if (found & SFUSE_STRAP_DDIB_DETECTED)
6541 intel_ddi_init(dev, PORT_B);
6542 if (found & SFUSE_STRAP_DDIC_DETECTED)
6543 intel_ddi_init(dev, PORT_C);
6544 if (found & SFUSE_STRAP_DDID_DETECTED)
6545 intel_ddi_init(dev, PORT_D);
6546 } else if (HAS_PCH_SPLIT(dev)) {
7832 int found; 6547 int found;
7833 6548
7834 if (I915_READ(HDMIB) & PORT_DETECTED) { 6549 if (I915_READ(HDMIB) & PORT_DETECTED) {
7835 /* PCH SDVOB multiplex with HDMIB */ 6550 /* PCH SDVOB multiplex with HDMIB */
7836 found = intel_sdvo_init(dev, PCH_SDVOB); 6551 found = intel_sdvo_init(dev, PCH_SDVOB, true);
7837 if (!found) 6552 if (!found)
7838 intel_hdmi_init(dev, HDMIB); 6553 intel_hdmi_init(dev, HDMIB);
7839 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 6554 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
@@ -7857,7 +6572,7 @@ static void intel_setup_outputs(struct drm_device *dev)
7857 6572
7858 if (I915_READ(SDVOB) & SDVO_DETECTED) { 6573 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7859 DRM_DEBUG_KMS("probing SDVOB\n"); 6574 DRM_DEBUG_KMS("probing SDVOB\n");
7860 found = intel_sdvo_init(dev, SDVOB); 6575 found = intel_sdvo_init(dev, SDVOB, true);
7861 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { 6576 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7862 DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); 6577 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7863 intel_hdmi_init(dev, SDVOB); 6578 intel_hdmi_init(dev, SDVOB);
@@ -7873,7 +6588,7 @@ static void intel_setup_outputs(struct drm_device *dev)
7873 6588
7874 if (I915_READ(SDVOB) & SDVO_DETECTED) { 6589 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7875 DRM_DEBUG_KMS("probing SDVOC\n"); 6590 DRM_DEBUG_KMS("probing SDVOC\n");
7876 found = intel_sdvo_init(dev, SDVOC); 6591 found = intel_sdvo_init(dev, SDVOC, false);
7877 } 6592 }
7878 6593
7879 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { 6594 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
@@ -8002,882 +6717,6 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
8002 .output_poll_changed = intel_fb_output_poll_changed, 6717 .output_poll_changed = intel_fb_output_poll_changed,
8003}; 6718};
8004 6719
8005static struct drm_i915_gem_object *
8006intel_alloc_context_page(struct drm_device *dev)
8007{
8008 struct drm_i915_gem_object *ctx;
8009 int ret;
8010
8011 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8012
8013 ctx = i915_gem_alloc_object(dev, 4096);
8014 if (!ctx) {
8015 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8016 return NULL;
8017 }
8018
8019 ret = i915_gem_object_pin(ctx, 4096, true);
8020 if (ret) {
8021 DRM_ERROR("failed to pin power context: %d\n", ret);
8022 goto err_unref;
8023 }
8024
8025 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8026 if (ret) {
8027 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8028 goto err_unpin;
8029 }
8030
8031 return ctx;
8032
8033err_unpin:
8034 i915_gem_object_unpin(ctx);
8035err_unref:
8036 drm_gem_object_unreference(&ctx->base);
8037 mutex_unlock(&dev->struct_mutex);
8038 return NULL;
8039}
8040
8041bool ironlake_set_drps(struct drm_device *dev, u8 val)
8042{
8043 struct drm_i915_private *dev_priv = dev->dev_private;
8044 u16 rgvswctl;
8045
8046 rgvswctl = I915_READ16(MEMSWCTL);
8047 if (rgvswctl & MEMCTL_CMD_STS) {
8048 DRM_DEBUG("gpu busy, RCS change rejected\n");
8049 return false; /* still busy with another command */
8050 }
8051
8052 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8053 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8054 I915_WRITE16(MEMSWCTL, rgvswctl);
8055 POSTING_READ16(MEMSWCTL);
8056
8057 rgvswctl |= MEMCTL_CMD_STS;
8058 I915_WRITE16(MEMSWCTL, rgvswctl);
8059
8060 return true;
8061}
8062
8063void ironlake_enable_drps(struct drm_device *dev)
8064{
8065 struct drm_i915_private *dev_priv = dev->dev_private;
8066 u32 rgvmodectl = I915_READ(MEMMODECTL);
8067 u8 fmax, fmin, fstart, vstart;
8068
8069 /* Enable temp reporting */
8070 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8071 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8072
8073 /* 100ms RC evaluation intervals */
8074 I915_WRITE(RCUPEI, 100000);
8075 I915_WRITE(RCDNEI, 100000);
8076
8077 /* Set max/min thresholds to 90ms and 80ms respectively */
8078 I915_WRITE(RCBMAXAVG, 90000);
8079 I915_WRITE(RCBMINAVG, 80000);
8080
8081 I915_WRITE(MEMIHYST, 1);
8082
8083 /* Set up min, max, and cur for interrupt handling */
8084 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8085 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8086 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8087 MEMMODE_FSTART_SHIFT;
8088
8089 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8090 PXVFREQ_PX_SHIFT;
8091
8092 dev_priv->fmax = fmax; /* IPS callback will increase this */
8093 dev_priv->fstart = fstart;
8094
8095 dev_priv->max_delay = fstart;
8096 dev_priv->min_delay = fmin;
8097 dev_priv->cur_delay = fstart;
8098
8099 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8100 fmax, fmin, fstart);
8101
8102 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8103
8104 /*
8105 * Interrupts will be enabled in ironlake_irq_postinstall
8106 */
8107
8108 I915_WRITE(VIDSTART, vstart);
8109 POSTING_READ(VIDSTART);
8110
8111 rgvmodectl |= MEMMODE_SWMODE_EN;
8112 I915_WRITE(MEMMODECTL, rgvmodectl);
8113
8114 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8115 DRM_ERROR("stuck trying to change perf mode\n");
8116 msleep(1);
8117
8118 ironlake_set_drps(dev, fstart);
8119
8120 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8121 I915_READ(0x112e0);
8122 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8123 dev_priv->last_count2 = I915_READ(0x112f4);
8124 getrawmonotonic(&dev_priv->last_time2);
8125}
8126
8127void ironlake_disable_drps(struct drm_device *dev)
8128{
8129 struct drm_i915_private *dev_priv = dev->dev_private;
8130 u16 rgvswctl = I915_READ16(MEMSWCTL);
8131
8132 /* Ack interrupts, disable EFC interrupt */
8133 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8134 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8135 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8136 I915_WRITE(DEIIR, DE_PCU_EVENT);
8137 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8138
8139 /* Go back to the starting frequency */
8140 ironlake_set_drps(dev, dev_priv->fstart);
8141 msleep(1);
8142 rgvswctl |= MEMCTL_CMD_STS;
8143 I915_WRITE(MEMSWCTL, rgvswctl);
8144 msleep(1);
8145
8146}
8147
8148void gen6_set_rps(struct drm_device *dev, u8 val)
8149{
8150 struct drm_i915_private *dev_priv = dev->dev_private;
8151 u32 swreq;
8152
8153 swreq = (val & 0x3ff) << 25;
8154 I915_WRITE(GEN6_RPNSWREQ, swreq);
8155}
8156
8157void gen6_disable_rps(struct drm_device *dev)
8158{
8159 struct drm_i915_private *dev_priv = dev->dev_private;
8160
8161 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8162 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8163 I915_WRITE(GEN6_PMIER, 0);
8164 /* Complete PM interrupt masking here doesn't race with the rps work
8165 * item again unmasking PM interrupts because that is using a different
8166 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8167 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8168
8169 spin_lock_irq(&dev_priv->rps_lock);
8170 dev_priv->pm_iir = 0;
8171 spin_unlock_irq(&dev_priv->rps_lock);
8172
8173 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8174}
8175
8176static unsigned long intel_pxfreq(u32 vidfreq)
8177{
8178 unsigned long freq;
8179 int div = (vidfreq & 0x3f0000) >> 16;
8180 int post = (vidfreq & 0x3000) >> 12;
8181 int pre = (vidfreq & 0x7);
8182
8183 if (!pre)
8184 return 0;
8185
8186 freq = ((div * 133333) / ((1<<post) * pre));
8187
8188 return freq;
8189}
8190
8191void intel_init_emon(struct drm_device *dev)
8192{
8193 struct drm_i915_private *dev_priv = dev->dev_private;
8194 u32 lcfuse;
8195 u8 pxw[16];
8196 int i;
8197
8198 /* Disable to program */
8199 I915_WRITE(ECR, 0);
8200 POSTING_READ(ECR);
8201
8202 /* Program energy weights for various events */
8203 I915_WRITE(SDEW, 0x15040d00);
8204 I915_WRITE(CSIEW0, 0x007f0000);
8205 I915_WRITE(CSIEW1, 0x1e220004);
8206 I915_WRITE(CSIEW2, 0x04000004);
8207
8208 for (i = 0; i < 5; i++)
8209 I915_WRITE(PEW + (i * 4), 0);
8210 for (i = 0; i < 3; i++)
8211 I915_WRITE(DEW + (i * 4), 0);
8212
8213 /* Program P-state weights to account for frequency power adjustment */
8214 for (i = 0; i < 16; i++) {
8215 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8216 unsigned long freq = intel_pxfreq(pxvidfreq);
8217 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8218 PXVFREQ_PX_SHIFT;
8219 unsigned long val;
8220
8221 val = vid * vid;
8222 val *= (freq / 1000);
8223 val *= 255;
8224 val /= (127*127*900);
8225 if (val > 0xff)
8226 DRM_ERROR("bad pxval: %ld\n", val);
8227 pxw[i] = val;
8228 }
8229 /* Render standby states get 0 weight */
8230 pxw[14] = 0;
8231 pxw[15] = 0;
8232
8233 for (i = 0; i < 4; i++) {
8234 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8235 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8236 I915_WRITE(PXW + (i * 4), val);
8237 }
8238
8239 /* Adjust magic regs to magic values (more experimental results) */
8240 I915_WRITE(OGW0, 0);
8241 I915_WRITE(OGW1, 0);
8242 I915_WRITE(EG0, 0x00007f00);
8243 I915_WRITE(EG1, 0x0000000e);
8244 I915_WRITE(EG2, 0x000e0000);
8245 I915_WRITE(EG3, 0x68000300);
8246 I915_WRITE(EG4, 0x42000000);
8247 I915_WRITE(EG5, 0x00140031);
8248 I915_WRITE(EG6, 0);
8249 I915_WRITE(EG7, 0);
8250
8251 for (i = 0; i < 8; i++)
8252 I915_WRITE(PXWL + (i * 4), 0);
8253
8254 /* Enable PMON + select events */
8255 I915_WRITE(ECR, 0x80000019);
8256
8257 lcfuse = I915_READ(LCFUSE02);
8258
8259 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8260}
8261
8262static int intel_enable_rc6(struct drm_device *dev)
8263{
8264 /*
8265 * Respect the kernel parameter if it is set
8266 */
8267 if (i915_enable_rc6 >= 0)
8268 return i915_enable_rc6;
8269
8270 /*
8271 * Disable RC6 on Ironlake
8272 */
8273 if (INTEL_INFO(dev)->gen == 5)
8274 return 0;
8275
8276 /*
8277 * Disable rc6 on Sandybridge
8278 */
8279 if (INTEL_INFO(dev)->gen == 6) {
8280 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
8281 return INTEL_RC6_ENABLE;
8282 }
8283 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8284 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8285}
8286
8287void gen6_enable_rps(struct drm_i915_private *dev_priv)
8288{
8289 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8290 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8291 u32 pcu_mbox, rc6_mask = 0;
8292 u32 gtfifodbg;
8293 int cur_freq, min_freq, max_freq;
8294 int rc6_mode;
8295 int i;
8296
8297 /* Here begins a magic sequence of register writes to enable
8298 * auto-downclocking.
8299 *
8300 * Perhaps there might be some value in exposing these to
8301 * userspace...
8302 */
8303 I915_WRITE(GEN6_RC_STATE, 0);
8304 mutex_lock(&dev_priv->dev->struct_mutex);
8305
8306 /* Clear the DBG now so we don't confuse earlier errors */
8307 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8308 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8309 I915_WRITE(GTFIFODBG, gtfifodbg);
8310 }
8311
8312 gen6_gt_force_wake_get(dev_priv);
8313
8314 /* disable the counters and set deterministic thresholds */
8315 I915_WRITE(GEN6_RC_CONTROL, 0);
8316
8317 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8318 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8319 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8320 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8321 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8322
8323 for (i = 0; i < I915_NUM_RINGS; i++)
8324 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8325
8326 I915_WRITE(GEN6_RC_SLEEP, 0);
8327 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8328 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8329 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8330 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8331
8332 rc6_mode = intel_enable_rc6(dev_priv->dev);
8333 if (rc6_mode & INTEL_RC6_ENABLE)
8334 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
8335
8336 if (rc6_mode & INTEL_RC6p_ENABLE)
8337 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
8338
8339 if (rc6_mode & INTEL_RC6pp_ENABLE)
8340 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
8341
8342 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8343 (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
8344 (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
8345 (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
8346
8347 I915_WRITE(GEN6_RC_CONTROL,
8348 rc6_mask |
8349 GEN6_RC_CTL_EI_MODE(1) |
8350 GEN6_RC_CTL_HW_ENABLE);
8351
8352 I915_WRITE(GEN6_RPNSWREQ,
8353 GEN6_FREQUENCY(10) |
8354 GEN6_OFFSET(0) |
8355 GEN6_AGGRESSIVE_TURBO);
8356 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8357 GEN6_FREQUENCY(12));
8358
8359 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8360 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8361 18 << 24 |
8362 6 << 16);
8363 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8364 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8365 I915_WRITE(GEN6_RP_UP_EI, 100000);
8366 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8367 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8368 I915_WRITE(GEN6_RP_CONTROL,
8369 GEN6_RP_MEDIA_TURBO |
8370 GEN6_RP_MEDIA_HW_MODE |
8371 GEN6_RP_MEDIA_IS_GFX |
8372 GEN6_RP_ENABLE |
8373 GEN6_RP_UP_BUSY_AVG |
8374 GEN6_RP_DOWN_IDLE_CONT);
8375
8376 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8377 500))
8378 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8379
8380 I915_WRITE(GEN6_PCODE_DATA, 0);
8381 I915_WRITE(GEN6_PCODE_MAILBOX,
8382 GEN6_PCODE_READY |
8383 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8384 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8385 500))
8386 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8387
8388 min_freq = (rp_state_cap & 0xff0000) >> 16;
8389 max_freq = rp_state_cap & 0xff;
8390 cur_freq = (gt_perf_status & 0xff00) >> 8;
8391
8392 /* Check for overclock support */
8393 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8394 500))
8395 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8396 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8397 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8398 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8399 500))
8400 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8401 if (pcu_mbox & (1<<31)) { /* OC supported */
8402 max_freq = pcu_mbox & 0xff;
8403 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8404 }
8405
8406 /* In units of 100MHz */
8407 dev_priv->max_delay = max_freq;
8408 dev_priv->min_delay = min_freq;
8409 dev_priv->cur_delay = cur_freq;
8410
8411 /* requires MSI enabled */
8412 I915_WRITE(GEN6_PMIER,
8413 GEN6_PM_MBOX_EVENT |
8414 GEN6_PM_THERMAL_EVENT |
8415 GEN6_PM_RP_DOWN_TIMEOUT |
8416 GEN6_PM_RP_UP_THRESHOLD |
8417 GEN6_PM_RP_DOWN_THRESHOLD |
8418 GEN6_PM_RP_UP_EI_EXPIRED |
8419 GEN6_PM_RP_DOWN_EI_EXPIRED);
8420 spin_lock_irq(&dev_priv->rps_lock);
8421 WARN_ON(dev_priv->pm_iir != 0);
8422 I915_WRITE(GEN6_PMIMR, 0);
8423 spin_unlock_irq(&dev_priv->rps_lock);
8424 /* enable all PM interrupts */
8425 I915_WRITE(GEN6_PMINTRMSK, 0);
8426
8427 gen6_gt_force_wake_put(dev_priv);
8428 mutex_unlock(&dev_priv->dev->struct_mutex);
8429}
8430
8431void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8432{
8433 int min_freq = 15;
8434 int gpu_freq, ia_freq, max_ia_freq;
8435 int scaling_factor = 180;
8436
8437 max_ia_freq = cpufreq_quick_get_max(0);
8438 /*
8439 * Default to measured freq if none found, PCU will ensure we don't go
8440 * over
8441 */
8442 if (!max_ia_freq)
8443 max_ia_freq = tsc_khz;
8444
8445 /* Convert from kHz to MHz */
8446 max_ia_freq /= 1000;
8447
8448 mutex_lock(&dev_priv->dev->struct_mutex);
8449
8450 /*
8451 * For each potential GPU frequency, load a ring frequency we'd like
8452 * to use for memory access. We do this by specifying the IA frequency
8453 * the PCU should use as a reference to determine the ring frequency.
8454 */
8455 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8456 gpu_freq--) {
8457 int diff = dev_priv->max_delay - gpu_freq;
8458
8459 /*
8460 * For GPU frequencies less than 750MHz, just use the lowest
8461 * ring freq.
8462 */
8463 if (gpu_freq < min_freq)
8464 ia_freq = 800;
8465 else
8466 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8467 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8468
8469 I915_WRITE(GEN6_PCODE_DATA,
8470 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8471 gpu_freq);
8472 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8473 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8474 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8475 GEN6_PCODE_READY) == 0, 10)) {
8476 DRM_ERROR("pcode write of freq table timed out\n");
8477 continue;
8478 }
8479 }
8480
8481 mutex_unlock(&dev_priv->dev->struct_mutex);
8482}
8483
8484static void ironlake_init_clock_gating(struct drm_device *dev)
8485{
8486 struct drm_i915_private *dev_priv = dev->dev_private;
8487 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8488
8489 /* Required for FBC */
8490 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8491 DPFCRUNIT_CLOCK_GATE_DISABLE |
8492 DPFDUNIT_CLOCK_GATE_DISABLE;
8493 /* Required for CxSR */
8494 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8495
8496 I915_WRITE(PCH_3DCGDIS0,
8497 MARIUNIT_CLOCK_GATE_DISABLE |
8498 SVSMUNIT_CLOCK_GATE_DISABLE);
8499 I915_WRITE(PCH_3DCGDIS1,
8500 VFMUNIT_CLOCK_GATE_DISABLE);
8501
8502 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8503
8504 /*
8505 * According to the spec the following bits should be set in
8506 * order to enable memory self-refresh
8507 * The bit 22/21 of 0x42004
8508 * The bit 5 of 0x42020
8509 * The bit 15 of 0x45000
8510 */
8511 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8512 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8513 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8514 I915_WRITE(ILK_DSPCLK_GATE,
8515 (I915_READ(ILK_DSPCLK_GATE) |
8516 ILK_DPARB_CLK_GATE));
8517 I915_WRITE(DISP_ARB_CTL,
8518 (I915_READ(DISP_ARB_CTL) |
8519 DISP_FBC_WM_DIS));
8520 I915_WRITE(WM3_LP_ILK, 0);
8521 I915_WRITE(WM2_LP_ILK, 0);
8522 I915_WRITE(WM1_LP_ILK, 0);
8523
8524 /*
8525 * Based on the document from hardware guys the following bits
8526 * should be set unconditionally in order to enable FBC.
8527 * The bit 22 of 0x42000
8528 * The bit 22 of 0x42004
8529 * The bit 7,8,9 of 0x42020.
8530 */
8531 if (IS_IRONLAKE_M(dev)) {
8532 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8533 I915_READ(ILK_DISPLAY_CHICKEN1) |
8534 ILK_FBCQ_DIS);
8535 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8536 I915_READ(ILK_DISPLAY_CHICKEN2) |
8537 ILK_DPARB_GATE);
8538 I915_WRITE(ILK_DSPCLK_GATE,
8539 I915_READ(ILK_DSPCLK_GATE) |
8540 ILK_DPFC_DIS1 |
8541 ILK_DPFC_DIS2 |
8542 ILK_CLK_FBC);
8543 }
8544
8545 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8546 I915_READ(ILK_DISPLAY_CHICKEN2) |
8547 ILK_ELPIN_409_SELECT);
8548 I915_WRITE(_3D_CHICKEN2,
8549 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8550 _3D_CHICKEN2_WM_READ_PIPELINED);
8551}
8552
8553static void gen6_init_clock_gating(struct drm_device *dev)
8554{
8555 struct drm_i915_private *dev_priv = dev->dev_private;
8556 int pipe;
8557 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8558
8559 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8560
8561 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8562 I915_READ(ILK_DISPLAY_CHICKEN2) |
8563 ILK_ELPIN_409_SELECT);
8564
8565 I915_WRITE(WM3_LP_ILK, 0);
8566 I915_WRITE(WM2_LP_ILK, 0);
8567 I915_WRITE(WM1_LP_ILK, 0);
8568
8569 I915_WRITE(GEN6_UCGCTL1,
8570 I915_READ(GEN6_UCGCTL1) |
8571 GEN6_BLBUNIT_CLOCK_GATE_DISABLE);
8572
8573 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8574 * gating disable must be set. Failure to set it results in
8575 * flickering pixels due to Z write ordering failures after
8576 * some amount of runtime in the Mesa "fire" demo, and Unigine
8577 * Sanctuary and Tropics, and apparently anything else with
8578 * alpha test or pixel discard.
8579 *
8580 * According to the spec, bit 11 (RCCUNIT) must also be set,
8581 * but we didn't debug actual testcases to find it out.
8582 */
8583 I915_WRITE(GEN6_UCGCTL2,
8584 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8585 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8586
8587 /*
8588 * According to the spec the following bits should be
8589 * set in order to enable memory self-refresh and fbc:
8590 * The bit21 and bit22 of 0x42000
8591 * The bit21 and bit22 of 0x42004
8592 * The bit5 and bit7 of 0x42020
8593 * The bit14 of 0x70180
8594 * The bit14 of 0x71180
8595 */
8596 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8597 I915_READ(ILK_DISPLAY_CHICKEN1) |
8598 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8599 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8600 I915_READ(ILK_DISPLAY_CHICKEN2) |
8601 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8602 I915_WRITE(ILK_DSPCLK_GATE,
8603 I915_READ(ILK_DSPCLK_GATE) |
8604 ILK_DPARB_CLK_GATE |
8605 ILK_DPFD_CLK_GATE);
8606
8607 for_each_pipe(pipe) {
8608 I915_WRITE(DSPCNTR(pipe),
8609 I915_READ(DSPCNTR(pipe)) |
8610 DISPPLANE_TRICKLE_FEED_DISABLE);
8611 intel_flush_display_plane(dev_priv, pipe);
8612 }
8613}
8614
8615static void ivybridge_init_clock_gating(struct drm_device *dev)
8616{
8617 struct drm_i915_private *dev_priv = dev->dev_private;
8618 int pipe;
8619 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8620
8621 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8622
8623 I915_WRITE(WM3_LP_ILK, 0);
8624 I915_WRITE(WM2_LP_ILK, 0);
8625 I915_WRITE(WM1_LP_ILK, 0);
8626
8627 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8628 * This implements the WaDisableRCZUnitClockGating workaround.
8629 */
8630 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8631
8632 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8633
8634 I915_WRITE(IVB_CHICKEN3,
8635 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8636 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8637
8638 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8639 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8640 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8641
8642 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8643 I915_WRITE(GEN7_L3CNTLREG1,
8644 GEN7_WA_FOR_GEN7_L3_CONTROL);
8645 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8646 GEN7_WA_L3_CHICKEN_MODE);
8647
8648 /* This is required by WaCatErrorRejectionIssue */
8649 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8650 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8651 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8652
8653 for_each_pipe(pipe) {
8654 I915_WRITE(DSPCNTR(pipe),
8655 I915_READ(DSPCNTR(pipe)) |
8656 DISPPLANE_TRICKLE_FEED_DISABLE);
8657 intel_flush_display_plane(dev_priv, pipe);
8658 }
8659}
8660
8661static void g4x_init_clock_gating(struct drm_device *dev)
8662{
8663 struct drm_i915_private *dev_priv = dev->dev_private;
8664 uint32_t dspclk_gate;
8665
8666 I915_WRITE(RENCLK_GATE_D1, 0);
8667 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8668 GS_UNIT_CLOCK_GATE_DISABLE |
8669 CL_UNIT_CLOCK_GATE_DISABLE);
8670 I915_WRITE(RAMCLK_GATE_D, 0);
8671 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8672 OVRUNIT_CLOCK_GATE_DISABLE |
8673 OVCUNIT_CLOCK_GATE_DISABLE;
8674 if (IS_GM45(dev))
8675 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8676 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8677}
8678
8679static void crestline_init_clock_gating(struct drm_device *dev)
8680{
8681 struct drm_i915_private *dev_priv = dev->dev_private;
8682
8683 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8684 I915_WRITE(RENCLK_GATE_D2, 0);
8685 I915_WRITE(DSPCLK_GATE_D, 0);
8686 I915_WRITE(RAMCLK_GATE_D, 0);
8687 I915_WRITE16(DEUC, 0);
8688}
8689
8690static void broadwater_init_clock_gating(struct drm_device *dev)
8691{
8692 struct drm_i915_private *dev_priv = dev->dev_private;
8693
8694 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8695 I965_RCC_CLOCK_GATE_DISABLE |
8696 I965_RCPB_CLOCK_GATE_DISABLE |
8697 I965_ISC_CLOCK_GATE_DISABLE |
8698 I965_FBC_CLOCK_GATE_DISABLE);
8699 I915_WRITE(RENCLK_GATE_D2, 0);
8700}
8701
8702static void gen3_init_clock_gating(struct drm_device *dev)
8703{
8704 struct drm_i915_private *dev_priv = dev->dev_private;
8705 u32 dstate = I915_READ(D_STATE);
8706
8707 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8708 DSTATE_DOT_CLOCK_GATING;
8709 I915_WRITE(D_STATE, dstate);
8710}
8711
8712static void i85x_init_clock_gating(struct drm_device *dev)
8713{
8714 struct drm_i915_private *dev_priv = dev->dev_private;
8715
8716 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8717}
8718
8719static void i830_init_clock_gating(struct drm_device *dev)
8720{
8721 struct drm_i915_private *dev_priv = dev->dev_private;
8722
8723 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8724}
8725
8726static void ibx_init_clock_gating(struct drm_device *dev)
8727{
8728 struct drm_i915_private *dev_priv = dev->dev_private;
8729
8730 /*
8731 * On Ibex Peak and Cougar Point, we need to disable clock
8732 * gating for the panel power sequencer or it will fail to
8733 * start up when no ports are active.
8734 */
8735 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8736}
8737
8738static void cpt_init_clock_gating(struct drm_device *dev)
8739{
8740 struct drm_i915_private *dev_priv = dev->dev_private;
8741 int pipe;
8742
8743 /*
8744 * On Ibex Peak and Cougar Point, we need to disable clock
8745 * gating for the panel power sequencer or it will fail to
8746 * start up when no ports are active.
8747 */
8748 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8749 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8750 DPLS_EDP_PPS_FIX_DIS);
8751 /* Without this, mode sets may fail silently on FDI */
8752 for_each_pipe(pipe)
8753 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8754}
8755
8756static void ironlake_teardown_rc6(struct drm_device *dev)
8757{
8758 struct drm_i915_private *dev_priv = dev->dev_private;
8759
8760 if (dev_priv->renderctx) {
8761 i915_gem_object_unpin(dev_priv->renderctx);
8762 drm_gem_object_unreference(&dev_priv->renderctx->base);
8763 dev_priv->renderctx = NULL;
8764 }
8765
8766 if (dev_priv->pwrctx) {
8767 i915_gem_object_unpin(dev_priv->pwrctx);
8768 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8769 dev_priv->pwrctx = NULL;
8770 }
8771}
8772
8773static void ironlake_disable_rc6(struct drm_device *dev)
8774{
8775 struct drm_i915_private *dev_priv = dev->dev_private;
8776
8777 if (I915_READ(PWRCTXA)) {
8778 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8779 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8780 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8781 50);
8782
8783 I915_WRITE(PWRCTXA, 0);
8784 POSTING_READ(PWRCTXA);
8785
8786 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8787 POSTING_READ(RSTDBYCTL);
8788 }
8789
8790 ironlake_teardown_rc6(dev);
8791}
8792
8793static int ironlake_setup_rc6(struct drm_device *dev)
8794{
8795 struct drm_i915_private *dev_priv = dev->dev_private;
8796
8797 if (dev_priv->renderctx == NULL)
8798 dev_priv->renderctx = intel_alloc_context_page(dev);
8799 if (!dev_priv->renderctx)
8800 return -ENOMEM;
8801
8802 if (dev_priv->pwrctx == NULL)
8803 dev_priv->pwrctx = intel_alloc_context_page(dev);
8804 if (!dev_priv->pwrctx) {
8805 ironlake_teardown_rc6(dev);
8806 return -ENOMEM;
8807 }
8808
8809 return 0;
8810}
8811
8812void ironlake_enable_rc6(struct drm_device *dev)
8813{
8814 struct drm_i915_private *dev_priv = dev->dev_private;
8815 int ret;
8816
8817 /* rc6 disabled by default due to repeated reports of hanging during
8818 * boot and resume.
8819 */
8820 if (!intel_enable_rc6(dev))
8821 return;
8822
8823 mutex_lock(&dev->struct_mutex);
8824 ret = ironlake_setup_rc6(dev);
8825 if (ret) {
8826 mutex_unlock(&dev->struct_mutex);
8827 return;
8828 }
8829
8830 /*
8831 * GPU can automatically power down the render unit if given a page
8832 * to save state.
8833 */
8834 ret = BEGIN_LP_RING(6);
8835 if (ret) {
8836 ironlake_teardown_rc6(dev);
8837 mutex_unlock(&dev->struct_mutex);
8838 return;
8839 }
8840
8841 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8842 OUT_RING(MI_SET_CONTEXT);
8843 OUT_RING(dev_priv->renderctx->gtt_offset |
8844 MI_MM_SPACE_GTT |
8845 MI_SAVE_EXT_STATE_EN |
8846 MI_RESTORE_EXT_STATE_EN |
8847 MI_RESTORE_INHIBIT);
8848 OUT_RING(MI_SUSPEND_FLUSH);
8849 OUT_RING(MI_NOOP);
8850 OUT_RING(MI_FLUSH);
8851 ADVANCE_LP_RING();
8852
8853 /*
8854 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8855 * does an implicit flush, combined with MI_FLUSH above, it should be
8856 * safe to assume that renderctx is valid
8857 */
8858 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8859 if (ret) {
8860 DRM_ERROR("failed to enable ironlake power power savings\n");
8861 ironlake_teardown_rc6(dev);
8862 mutex_unlock(&dev->struct_mutex);
8863 return;
8864 }
8865
8866 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8867 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8868 mutex_unlock(&dev->struct_mutex);
8869}
8870
8871void intel_init_clock_gating(struct drm_device *dev)
8872{
8873 struct drm_i915_private *dev_priv = dev->dev_private;
8874
8875 dev_priv->display.init_clock_gating(dev);
8876
8877 if (dev_priv->display.init_pch_clock_gating)
8878 dev_priv->display.init_pch_clock_gating(dev);
8879}
8880
8881/* Set up chip specific display functions */ 6720/* Set up chip specific display functions */
8882static void intel_init_display(struct drm_device *dev) 6721static void intel_init_display(struct drm_device *dev)
8883{ 6722{
@@ -8887,32 +6726,20 @@ static void intel_init_display(struct drm_device *dev)
8887 if (HAS_PCH_SPLIT(dev)) { 6726 if (HAS_PCH_SPLIT(dev)) {
8888 dev_priv->display.dpms = ironlake_crtc_dpms; 6727 dev_priv->display.dpms = ironlake_crtc_dpms;
8889 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; 6728 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6729 dev_priv->display.off = ironlake_crtc_off;
8890 dev_priv->display.update_plane = ironlake_update_plane; 6730 dev_priv->display.update_plane = ironlake_update_plane;
8891 } else { 6731 } else {
8892 dev_priv->display.dpms = i9xx_crtc_dpms; 6732 dev_priv->display.dpms = i9xx_crtc_dpms;
8893 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; 6733 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6734 dev_priv->display.off = i9xx_crtc_off;
8894 dev_priv->display.update_plane = i9xx_update_plane; 6735 dev_priv->display.update_plane = i9xx_update_plane;
8895 } 6736 }
8896 6737
8897 if (I915_HAS_FBC(dev)) {
8898 if (HAS_PCH_SPLIT(dev)) {
8899 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8900 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8901 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8902 } else if (IS_GM45(dev)) {
8903 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8904 dev_priv->display.enable_fbc = g4x_enable_fbc;
8905 dev_priv->display.disable_fbc = g4x_disable_fbc;
8906 } else if (IS_CRESTLINE(dev)) {
8907 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8908 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8909 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8910 }
8911 /* 855GM needs testing */
8912 }
8913
8914 /* Returns the core display clock speed */ 6738 /* Returns the core display clock speed */
8915 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) 6739 if (IS_VALLEYVIEW(dev))
6740 dev_priv->display.get_display_clock_speed =
6741 valleyview_get_display_clock_speed;
6742 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8916 dev_priv->display.get_display_clock_speed = 6743 dev_priv->display.get_display_clock_speed =
8917 i945_get_display_clock_speed; 6744 i945_get_display_clock_speed;
8918 else if (IS_I915G(dev)) 6745 else if (IS_I915G(dev))
@@ -8934,124 +6761,27 @@ static void intel_init_display(struct drm_device *dev)
8934 dev_priv->display.get_display_clock_speed = 6761 dev_priv->display.get_display_clock_speed =
8935 i830_get_display_clock_speed; 6762 i830_get_display_clock_speed;
8936 6763
8937 /* For FIFO watermark updates */
8938 if (HAS_PCH_SPLIT(dev)) { 6764 if (HAS_PCH_SPLIT(dev)) {
8939 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8940 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8941
8942 /* IVB configs may use multi-threaded forcewake */
8943 if (IS_IVYBRIDGE(dev)) {
8944 u32 ecobus;
8945
8946 /* A small trick here - if the bios hasn't configured MT forcewake,
8947 * and if the device is in RC6, then force_wake_mt_get will not wake
8948 * the device and the ECOBUS read will return zero. Which will be
8949 * (correctly) interpreted by the test below as MT forcewake being
8950 * disabled.
8951 */
8952 mutex_lock(&dev->struct_mutex);
8953 __gen6_gt_force_wake_mt_get(dev_priv);
8954 ecobus = I915_READ_NOTRACE(ECOBUS);
8955 __gen6_gt_force_wake_mt_put(dev_priv);
8956 mutex_unlock(&dev->struct_mutex);
8957
8958 if (ecobus & FORCEWAKE_MT_ENABLE) {
8959 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8960 dev_priv->display.force_wake_get =
8961 __gen6_gt_force_wake_mt_get;
8962 dev_priv->display.force_wake_put =
8963 __gen6_gt_force_wake_mt_put;
8964 }
8965 }
8966
8967 if (HAS_PCH_IBX(dev))
8968 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8969 else if (HAS_PCH_CPT(dev))
8970 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8971
8972 if (IS_GEN5(dev)) { 6765 if (IS_GEN5(dev)) {
8973 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8974 dev_priv->display.update_wm = ironlake_update_wm;
8975 else {
8976 DRM_DEBUG_KMS("Failed to get proper latency. "
8977 "Disable CxSR\n");
8978 dev_priv->display.update_wm = NULL;
8979 }
8980 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; 6766 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8981 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8982 dev_priv->display.write_eld = ironlake_write_eld; 6767 dev_priv->display.write_eld = ironlake_write_eld;
8983 } else if (IS_GEN6(dev)) { 6768 } else if (IS_GEN6(dev)) {
8984 if (SNB_READ_WM0_LATENCY()) {
8985 dev_priv->display.update_wm = sandybridge_update_wm;
8986 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8987 } else {
8988 DRM_DEBUG_KMS("Failed to read display plane latency. "
8989 "Disable CxSR\n");
8990 dev_priv->display.update_wm = NULL;
8991 }
8992 dev_priv->display.fdi_link_train = gen6_fdi_link_train; 6769 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8993 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8994 dev_priv->display.write_eld = ironlake_write_eld; 6770 dev_priv->display.write_eld = ironlake_write_eld;
8995 } else if (IS_IVYBRIDGE(dev)) { 6771 } else if (IS_IVYBRIDGE(dev)) {
8996 /* FIXME: detect B0+ stepping and use auto training */ 6772 /* FIXME: detect B0+ stepping and use auto training */
8997 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; 6773 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8998 if (SNB_READ_WM0_LATENCY()) { 6774 dev_priv->display.write_eld = ironlake_write_eld;
8999 dev_priv->display.update_wm = sandybridge_update_wm; 6775 } else if (IS_HASWELL(dev)) {
9000 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 6776 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9001 } else {
9002 DRM_DEBUG_KMS("Failed to read display plane latency. "
9003 "Disable CxSR\n");
9004 dev_priv->display.update_wm = NULL;
9005 }
9006 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
9007 dev_priv->display.write_eld = ironlake_write_eld; 6777 dev_priv->display.write_eld = ironlake_write_eld;
9008 } else 6778 } else
9009 dev_priv->display.update_wm = NULL; 6779 dev_priv->display.update_wm = NULL;
9010 } else if (IS_PINEVIEW(dev)) { 6780 } else if (IS_VALLEYVIEW(dev)) {
9011 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 6781 dev_priv->display.force_wake_get = vlv_force_wake_get;
9012 dev_priv->is_ddr3, 6782 dev_priv->display.force_wake_put = vlv_force_wake_put;
9013 dev_priv->fsb_freq,
9014 dev_priv->mem_freq)) {
9015 DRM_INFO("failed to find known CxSR latency "
9016 "(found ddr%s fsb freq %d, mem freq %d), "
9017 "disabling CxSR\n",
9018 (dev_priv->is_ddr3 == 1) ? "3" : "2",
9019 dev_priv->fsb_freq, dev_priv->mem_freq);
9020 /* Disable CxSR and never update its watermark again */
9021 pineview_disable_cxsr(dev);
9022 dev_priv->display.update_wm = NULL;
9023 } else
9024 dev_priv->display.update_wm = pineview_update_wm;
9025 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9026 } else if (IS_G4X(dev)) { 6783 } else if (IS_G4X(dev)) {
9027 dev_priv->display.write_eld = g4x_write_eld; 6784 dev_priv->display.write_eld = g4x_write_eld;
9028 dev_priv->display.update_wm = g4x_update_wm;
9029 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9030 } else if (IS_GEN4(dev)) {
9031 dev_priv->display.update_wm = i965_update_wm;
9032 if (IS_CRESTLINE(dev))
9033 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9034 else if (IS_BROADWATER(dev))
9035 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9036 } else if (IS_GEN3(dev)) {
9037 dev_priv->display.update_wm = i9xx_update_wm;
9038 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9039 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9040 } else if (IS_I865G(dev)) {
9041 dev_priv->display.update_wm = i830_update_wm;
9042 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9043 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9044 } else if (IS_I85X(dev)) {
9045 dev_priv->display.update_wm = i9xx_update_wm;
9046 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
9047 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9048 } else {
9049 dev_priv->display.update_wm = i830_update_wm;
9050 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9051 if (IS_845G(dev))
9052 dev_priv->display.get_fifo_size = i845_get_fifo_size;
9053 else
9054 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9055 } 6785 }
9056 6786
9057 /* Default just returns -ENODEV to indicate unsupported */ 6787 /* Default just returns -ENODEV to indicate unsupported */
@@ -9090,7 +6820,7 @@ static void quirk_pipea_force(struct drm_device *dev)
9090 struct drm_i915_private *dev_priv = dev->dev_private; 6820 struct drm_i915_private *dev_priv = dev->dev_private;
9091 6821
9092 dev_priv->quirks |= QUIRK_PIPEA_FORCE; 6822 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9093 DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); 6823 DRM_INFO("applying pipe a force quirk\n");
9094} 6824}
9095 6825
9096/* 6826/*
@@ -9100,6 +6830,18 @@ static void quirk_ssc_force_disable(struct drm_device *dev)
9100{ 6830{
9101 struct drm_i915_private *dev_priv = dev->dev_private; 6831 struct drm_i915_private *dev_priv = dev->dev_private;
9102 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 6832 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6833 DRM_INFO("applying lvds SSC disable quirk\n");
6834}
6835
6836/*
6837 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6838 * brightness value
6839 */
6840static void quirk_invert_brightness(struct drm_device *dev)
6841{
6842 struct drm_i915_private *dev_priv = dev->dev_private;
6843 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6844 DRM_INFO("applying inverted panel brightness quirk\n");
9103} 6845}
9104 6846
9105struct intel_quirk { 6847struct intel_quirk {
@@ -9109,7 +6851,7 @@ struct intel_quirk {
9109 void (*hook)(struct drm_device *dev); 6851 void (*hook)(struct drm_device *dev);
9110}; 6852};
9111 6853
9112struct intel_quirk intel_quirks[] = { 6854static struct intel_quirk intel_quirks[] = {
9113 /* HP Mini needs pipe A force quirk (LP: #322104) */ 6855 /* HP Mini needs pipe A force quirk (LP: #322104) */
9114 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, 6856 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9115 6857
@@ -9134,6 +6876,9 @@ struct intel_quirk intel_quirks[] = {
9134 6876
9135 /* Sony Vaio Y cannot use SSC on LVDS */ 6877 /* Sony Vaio Y cannot use SSC on LVDS */
9136 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, 6878 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6879
6880 /* Acer Aspire 5734Z must invert backlight brightness */
6881 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9137}; 6882};
9138 6883
9139static void intel_init_quirks(struct drm_device *dev) 6884static void intel_init_quirks(struct drm_device *dev)
@@ -9166,7 +6911,7 @@ static void i915_disable_vga(struct drm_device *dev)
9166 vga_reg = VGACNTRL; 6911 vga_reg = VGACNTRL;
9167 6912
9168 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 6913 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9169 outb(1, VGA_SR_INDEX); 6914 outb(SR01, VGA_SR_INDEX);
9170 sr1 = inb(VGA_SR_DATA); 6915 sr1 = inb(VGA_SR_DATA);
9171 outb(sr1 | 1<<5, VGA_SR_DATA); 6916 outb(sr1 | 1<<5, VGA_SR_DATA);
9172 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 6917 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
@@ -9176,6 +6921,40 @@ static void i915_disable_vga(struct drm_device *dev)
9176 POSTING_READ(vga_reg); 6921 POSTING_READ(vga_reg);
9177} 6922}
9178 6923
6924static void ivb_pch_pwm_override(struct drm_device *dev)
6925{
6926 struct drm_i915_private *dev_priv = dev->dev_private;
6927
6928 /*
6929 * IVB has CPU eDP backlight regs too, set things up to let the
6930 * PCH regs control the backlight
6931 */
6932 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6933 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6934 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6935}
6936
6937void intel_modeset_init_hw(struct drm_device *dev)
6938{
6939 struct drm_i915_private *dev_priv = dev->dev_private;
6940
6941 intel_init_clock_gating(dev);
6942
6943 if (IS_IRONLAKE_M(dev)) {
6944 ironlake_enable_drps(dev);
6945 ironlake_enable_rc6(dev);
6946 intel_init_emon(dev);
6947 }
6948
6949 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6950 gen6_enable_rps(dev_priv);
6951 gen6_update_ring_freq(dev_priv);
6952 }
6953
6954 if (IS_IVYBRIDGE(dev))
6955 ivb_pch_pwm_override(dev);
6956}
6957
9179void intel_modeset_init(struct drm_device *dev) 6958void intel_modeset_init(struct drm_device *dev)
9180{ 6959{
9181 struct drm_i915_private *dev_priv = dev->dev_private; 6960 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -9189,10 +6968,14 @@ void intel_modeset_init(struct drm_device *dev)
9189 dev->mode_config.preferred_depth = 24; 6968 dev->mode_config.preferred_depth = 24;
9190 dev->mode_config.prefer_shadow = 1; 6969 dev->mode_config.prefer_shadow = 1;
9191 6970
9192 dev->mode_config.funcs = (void *)&intel_mode_funcs; 6971 dev->mode_config.funcs = &intel_mode_funcs;
9193 6972
9194 intel_init_quirks(dev); 6973 intel_init_quirks(dev);
9195 6974
6975 intel_init_pm(dev);
6976
6977 intel_prepare_ddi(dev);
6978
9196 intel_init_display(dev); 6979 intel_init_display(dev);
9197 6980
9198 if (IS_GEN2(dev)) { 6981 if (IS_GEN2(dev)) {
@@ -9217,22 +7000,12 @@ void intel_modeset_init(struct drm_device *dev)
9217 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); 7000 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9218 } 7001 }
9219 7002
7003 intel_pch_pll_init(dev);
7004
9220 /* Just disable it once at startup */ 7005 /* Just disable it once at startup */
9221 i915_disable_vga(dev); 7006 i915_disable_vga(dev);
9222 intel_setup_outputs(dev); 7007 intel_setup_outputs(dev);
9223 7008
9224 intel_init_clock_gating(dev);
9225
9226 if (IS_IRONLAKE_M(dev)) {
9227 ironlake_enable_drps(dev);
9228 intel_init_emon(dev);
9229 }
9230
9231 if (IS_GEN6(dev) || IS_GEN7(dev)) {
9232 gen6_enable_rps(dev_priv);
9233 gen6_update_ring_freq(dev_priv);
9234 }
9235
9236 INIT_WORK(&dev_priv->idle_work, intel_idle_update); 7009 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9237 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, 7010 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9238 (unsigned long)dev); 7011 (unsigned long)dev);
@@ -9240,8 +7013,7 @@ void intel_modeset_init(struct drm_device *dev)
9240 7013
9241void intel_modeset_gem_init(struct drm_device *dev) 7014void intel_modeset_gem_init(struct drm_device *dev)
9242{ 7015{
9243 if (IS_IRONLAKE_M(dev)) 7016 intel_modeset_init_hw(dev);
9244 ironlake_enable_rc6(dev);
9245 7017
9246 intel_setup_overlay(dev); 7018 intel_setup_overlay(dev);
9247} 7019}
@@ -9271,12 +7043,15 @@ void intel_modeset_cleanup(struct drm_device *dev)
9271 7043
9272 if (IS_IRONLAKE_M(dev)) 7044 if (IS_IRONLAKE_M(dev))
9273 ironlake_disable_drps(dev); 7045 ironlake_disable_drps(dev);
9274 if (IS_GEN6(dev) || IS_GEN7(dev)) 7046 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
9275 gen6_disable_rps(dev); 7047 gen6_disable_rps(dev);
9276 7048
9277 if (IS_IRONLAKE_M(dev)) 7049 if (IS_IRONLAKE_M(dev))
9278 ironlake_disable_rc6(dev); 7050 ironlake_disable_rc6(dev);
9279 7051
7052 if (IS_VALLEYVIEW(dev))
7053 vlv_init_dpio(dev);
7054
9280 mutex_unlock(&dev->struct_mutex); 7055 mutex_unlock(&dev->struct_mutex);
9281 7056
9282 /* Disable the irq before mode object teardown, for the irq might 7057 /* Disable the irq before mode object teardown, for the irq might
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 15:07:27 -0500