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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1029
1 files changed, 681 insertions, 348 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 897230832c8c..5146b8094ae0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -102,32 +102,32 @@ struct intel_limit {
102#define I9XX_DOT_MAX 400000 102#define I9XX_DOT_MAX 400000
103#define I9XX_VCO_MIN 1400000 103#define I9XX_VCO_MIN 1400000
104#define I9XX_VCO_MAX 2800000 104#define I9XX_VCO_MAX 2800000
105#define IGD_VCO_MIN 1700000 105#define PINEVIEW_VCO_MIN 1700000
106#define IGD_VCO_MAX 3500000 106#define PINEVIEW_VCO_MAX 3500000
107#define I9XX_N_MIN 1 107#define I9XX_N_MIN 1
108#define I9XX_N_MAX 6 108#define I9XX_N_MAX 6
109/* IGD's Ncounter is a ring counter */ 109/* Pineview's Ncounter is a ring counter */
110#define IGD_N_MIN 3 110#define PINEVIEW_N_MIN 3
111#define IGD_N_MAX 6 111#define PINEVIEW_N_MAX 6
112#define I9XX_M_MIN 70 112#define I9XX_M_MIN 70
113#define I9XX_M_MAX 120 113#define I9XX_M_MAX 120
114#define IGD_M_MIN 2 114#define PINEVIEW_M_MIN 2
115#define IGD_M_MAX 256 115#define PINEVIEW_M_MAX 256
116#define I9XX_M1_MIN 10 116#define I9XX_M1_MIN 10
117#define I9XX_M1_MAX 22 117#define I9XX_M1_MAX 22
118#define I9XX_M2_MIN 5 118#define I9XX_M2_MIN 5
119#define I9XX_M2_MAX 9 119#define I9XX_M2_MAX 9
120/* IGD M1 is reserved, and must be 0 */ 120/* Pineview M1 is reserved, and must be 0 */
121#define IGD_M1_MIN 0 121#define PINEVIEW_M1_MIN 0
122#define IGD_M1_MAX 0 122#define PINEVIEW_M1_MAX 0
123#define IGD_M2_MIN 0 123#define PINEVIEW_M2_MIN 0
124#define IGD_M2_MAX 254 124#define PINEVIEW_M2_MAX 254
125#define I9XX_P_SDVO_DAC_MIN 5 125#define I9XX_P_SDVO_DAC_MIN 5
126#define I9XX_P_SDVO_DAC_MAX 80 126#define I9XX_P_SDVO_DAC_MAX 80
127#define I9XX_P_LVDS_MIN 7 127#define I9XX_P_LVDS_MIN 7
128#define I9XX_P_LVDS_MAX 98 128#define I9XX_P_LVDS_MAX 98
129#define IGD_P_LVDS_MIN 7 129#define PINEVIEW_P_LVDS_MIN 7
130#define IGD_P_LVDS_MAX 112 130#define PINEVIEW_P_LVDS_MAX 112
131#define I9XX_P1_MIN 1 131#define I9XX_P1_MIN 1
132#define I9XX_P1_MAX 8 132#define I9XX_P1_MAX 8
133#define I9XX_P2_SDVO_DAC_SLOW 10 133#define I9XX_P2_SDVO_DAC_SLOW 10
@@ -234,33 +234,33 @@ struct intel_limit {
234#define G4X_P2_DISPLAY_PORT_FAST 10 234#define G4X_P2_DISPLAY_PORT_FAST 10
235#define G4X_P2_DISPLAY_PORT_LIMIT 0 235#define G4X_P2_DISPLAY_PORT_LIMIT 0
236 236
237/* IGDNG */ 237/* Ironlake */
238/* as we calculate clock using (register_value + 2) for 238/* as we calculate clock using (register_value + 2) for
239 N/M1/M2, so here the range value for them is (actual_value-2). 239 N/M1/M2, so here the range value for them is (actual_value-2).
240 */ 240 */
241#define IGDNG_DOT_MIN 25000 241#define IRONLAKE_DOT_MIN 25000
242#define IGDNG_DOT_MAX 350000 242#define IRONLAKE_DOT_MAX 350000
243#define IGDNG_VCO_MIN 1760000 243#define IRONLAKE_VCO_MIN 1760000
244#define IGDNG_VCO_MAX 3510000 244#define IRONLAKE_VCO_MAX 3510000
245#define IGDNG_N_MIN 1 245#define IRONLAKE_N_MIN 1
246#define IGDNG_N_MAX 5 246#define IRONLAKE_N_MAX 5
247#define IGDNG_M_MIN 79 247#define IRONLAKE_M_MIN 79
248#define IGDNG_M_MAX 118 248#define IRONLAKE_M_MAX 118
249#define IGDNG_M1_MIN 12 249#define IRONLAKE_M1_MIN 12
250#define IGDNG_M1_MAX 23 250#define IRONLAKE_M1_MAX 23
251#define IGDNG_M2_MIN 5 251#define IRONLAKE_M2_MIN 5
252#define IGDNG_M2_MAX 9 252#define IRONLAKE_M2_MAX 9
253#define IGDNG_P_SDVO_DAC_MIN 5 253#define IRONLAKE_P_SDVO_DAC_MIN 5
254#define IGDNG_P_SDVO_DAC_MAX 80 254#define IRONLAKE_P_SDVO_DAC_MAX 80
255#define IGDNG_P_LVDS_MIN 28 255#define IRONLAKE_P_LVDS_MIN 28
256#define IGDNG_P_LVDS_MAX 112 256#define IRONLAKE_P_LVDS_MAX 112
257#define IGDNG_P1_MIN 1 257#define IRONLAKE_P1_MIN 1
258#define IGDNG_P1_MAX 8 258#define IRONLAKE_P1_MAX 8
259#define IGDNG_P2_SDVO_DAC_SLOW 10 259#define IRONLAKE_P2_SDVO_DAC_SLOW 10
260#define IGDNG_P2_SDVO_DAC_FAST 5 260#define IRONLAKE_P2_SDVO_DAC_FAST 5
261#define IGDNG_P2_LVDS_SLOW 14 /* single channel */ 261#define IRONLAKE_P2_LVDS_SLOW 14 /* single channel */
262#define IGDNG_P2_LVDS_FAST 7 /* double channel */ 262#define IRONLAKE_P2_LVDS_FAST 7 /* double channel */
263#define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */ 263#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
264 264
265static bool 265static bool
266intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 266intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
@@ -272,15 +272,15 @@ static bool
272intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 272intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock); 273 int target, int refclk, intel_clock_t *best_clock);
274static bool 274static bool
275intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 275intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock); 276 int target, int refclk, intel_clock_t *best_clock);
277 277
278static bool 278static bool
279intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 279intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
280 int target, int refclk, intel_clock_t *best_clock); 280 int target, int refclk, intel_clock_t *best_clock);
281static bool 281static bool
282intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc, 282intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
283 int target, int refclk, intel_clock_t *best_clock); 283 int target, int refclk, intel_clock_t *best_clock);
284 284
285static const intel_limit_t intel_limits_i8xx_dvo = { 285static const intel_limit_t intel_limits_i8xx_dvo = {
286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, 286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
@@ -453,13 +453,13 @@ static const intel_limit_t intel_limits_g4x_display_port = {
453 .find_pll = intel_find_pll_g4x_dp, 453 .find_pll = intel_find_pll_g4x_dp,
454}; 454};
455 455
456static const intel_limit_t intel_limits_igd_sdvo = { 456static const intel_limit_t intel_limits_pineview_sdvo = {
457 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, 457 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
458 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, 458 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
459 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, 459 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
460 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, 460 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
461 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, 461 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
462 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, 462 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
463 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, 463 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
464 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 464 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
@@ -468,59 +468,59 @@ static const intel_limit_t intel_limits_igd_sdvo = {
468 .find_reduced_pll = intel_find_best_reduced_PLL, 468 .find_reduced_pll = intel_find_best_reduced_PLL,
469}; 469};
470 470
471static const intel_limit_t intel_limits_igd_lvds = { 471static const intel_limit_t intel_limits_pineview_lvds = {
472 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, 472 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
473 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, 473 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
474 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, 474 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
475 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, 475 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
476 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, 476 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
477 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, 477 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
478 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX }, 478 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
479 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 479 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
480 /* IGD only supports single-channel mode. */ 480 /* Pineview only supports single-channel mode. */
481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, 482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
483 .find_pll = intel_find_best_PLL, 483 .find_pll = intel_find_best_PLL,
484 .find_reduced_pll = intel_find_best_reduced_PLL, 484 .find_reduced_pll = intel_find_best_reduced_PLL,
485}; 485};
486 486
487static const intel_limit_t intel_limits_igdng_sdvo = { 487static const intel_limit_t intel_limits_ironlake_sdvo = {
488 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, 488 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
489 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, 489 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
490 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, 490 .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX },
491 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, 491 .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX },
492 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, 492 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
493 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, 493 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
494 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX }, 494 .p = { .min = IRONLAKE_P_SDVO_DAC_MIN, .max = IRONLAKE_P_SDVO_DAC_MAX },
495 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, 495 .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX },
496 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, 496 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
497 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW, 497 .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW,
498 .p2_fast = IGDNG_P2_SDVO_DAC_FAST }, 498 .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST },
499 .find_pll = intel_igdng_find_best_PLL, 499 .find_pll = intel_ironlake_find_best_PLL,
500}; 500};
501 501
502static const intel_limit_t intel_limits_igdng_lvds = { 502static const intel_limit_t intel_limits_ironlake_lvds = {
503 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, 503 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
504 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, 504 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
505 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, 505 .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX },
506 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, 506 .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX },
507 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, 507 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
508 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, 508 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
509 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX }, 509 .p = { .min = IRONLAKE_P_LVDS_MIN, .max = IRONLAKE_P_LVDS_MAX },
510 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, 510 .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX },
511 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, 511 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
512 .p2_slow = IGDNG_P2_LVDS_SLOW, 512 .p2_slow = IRONLAKE_P2_LVDS_SLOW,
513 .p2_fast = IGDNG_P2_LVDS_FAST }, 513 .p2_fast = IRONLAKE_P2_LVDS_FAST },
514 .find_pll = intel_igdng_find_best_PLL, 514 .find_pll = intel_ironlake_find_best_PLL,
515}; 515};
516 516
517static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc) 517static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
518{ 518{
519 const intel_limit_t *limit; 519 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
521 limit = &intel_limits_igdng_lvds; 521 limit = &intel_limits_ironlake_lvds;
522 else 522 else
523 limit = &intel_limits_igdng_sdvo; 523 limit = &intel_limits_ironlake_sdvo;
524 524
525 return limit; 525 return limit;
526} 526}
@@ -557,20 +557,20 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
557 struct drm_device *dev = crtc->dev; 557 struct drm_device *dev = crtc->dev;
558 const intel_limit_t *limit; 558 const intel_limit_t *limit;
559 559
560 if (IS_IGDNG(dev)) 560 if (IS_IRONLAKE(dev))
561 limit = intel_igdng_limit(crtc); 561 limit = intel_ironlake_limit(crtc);
562 else if (IS_G4X(dev)) { 562 else if (IS_G4X(dev)) {
563 limit = intel_g4x_limit(crtc); 563 limit = intel_g4x_limit(crtc);
564 } else if (IS_I9XX(dev) && !IS_IGD(dev)) { 564 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
566 limit = &intel_limits_i9xx_lvds; 566 limit = &intel_limits_i9xx_lvds;
567 else 567 else
568 limit = &intel_limits_i9xx_sdvo; 568 limit = &intel_limits_i9xx_sdvo;
569 } else if (IS_IGD(dev)) { 569 } else if (IS_PINEVIEW(dev)) {
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
571 limit = &intel_limits_igd_lvds; 571 limit = &intel_limits_pineview_lvds;
572 else 572 else
573 limit = &intel_limits_igd_sdvo; 573 limit = &intel_limits_pineview_sdvo;
574 } else { 574 } else {
575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
576 limit = &intel_limits_i8xx_lvds; 576 limit = &intel_limits_i8xx_lvds;
@@ -580,8 +580,8 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
580 return limit; 580 return limit;
581} 581}
582 582
583/* m1 is reserved as 0 in IGD, n is a ring counter */ 583/* m1 is reserved as 0 in Pineview, n is a ring counter */
584static void igd_clock(int refclk, intel_clock_t *clock) 584static void pineview_clock(int refclk, intel_clock_t *clock)
585{ 585{
586 clock->m = clock->m2 + 2; 586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2; 587 clock->p = clock->p1 * clock->p2;
@@ -591,8 +591,8 @@ static void igd_clock(int refclk, intel_clock_t *clock)
591 591
592static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) 592static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
593{ 593{
594 if (IS_IGD(dev)) { 594 if (IS_PINEVIEW(dev)) {
595 igd_clock(refclk, clock); 595 pineview_clock(refclk, clock);
596 return; 596 return;
597 } 597 }
598 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 598 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
@@ -657,7 +657,7 @@ static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
657 INTELPllInvalid ("m2 out of range\n"); 657 INTELPllInvalid ("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid ("m1 out of range\n"); 659 INTELPllInvalid ("m1 out of range\n");
660 if (clock->m1 <= clock->m2 && !IS_IGD(dev)) 660 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
661 INTELPllInvalid ("m1 <= m2\n"); 661 INTELPllInvalid ("m1 <= m2\n");
662 if (clock->m < limit->m.min || limit->m.max < clock->m) 662 if (clock->m < limit->m.min || limit->m.max < clock->m)
663 INTELPllInvalid ("m out of range\n"); 663 INTELPllInvalid ("m out of range\n");
@@ -706,16 +706,17 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
706 706
707 memset (best_clock, 0, sizeof (*best_clock)); 707 memset (best_clock, 0, sizeof (*best_clock));
708 708
709 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 709 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
710 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 710 clock.m1++) {
711 clock.m1++) { 711 for (clock.m2 = limit->m2.min;
712 for (clock.m2 = limit->m2.min; 712 clock.m2 <= limit->m2.max; clock.m2++) {
713 clock.m2 <= limit->m2.max; clock.m2++) { 713 /* m1 is always 0 in Pineview */
714 /* m1 is always 0 in IGD */ 714 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
715 if (clock.m2 >= clock.m1 && !IS_IGD(dev)) 715 break;
716 break; 716 for (clock.n = limit->n.min;
717 for (clock.n = limit->n.min; 717 clock.n <= limit->n.max; clock.n++) {
718 clock.n <= limit->n.max; clock.n++) { 718 for (clock.p1 = limit->p1.min;
719 clock.p1 <= limit->p1.max; clock.p1++) {
719 int this_err; 720 int this_err;
720 721
721 intel_clock(dev, refclk, &clock); 722 intel_clock(dev, refclk, &clock);
@@ -751,8 +752,8 @@ intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
751 752
752 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 753 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
753 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { 754 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
754 /* m1 is always 0 in IGD */ 755 /* m1 is always 0 in Pineview */
755 if (clock.m2 >= clock.m1 && !IS_IGD(dev)) 756 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
756 break; 757 break;
757 for (clock.n = limit->n.min; clock.n <= limit->n.max; 758 for (clock.n = limit->n.min; clock.n <= limit->n.max;
758 clock.n++) { 759 clock.n++) {
@@ -833,8 +834,8 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
833} 834}
834 835
835static bool 836static bool
836intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 837intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *best_clock) 838 int target, int refclk, intel_clock_t *best_clock)
838{ 839{
839 struct drm_device *dev = crtc->dev; 840 struct drm_device *dev = crtc->dev;
840 intel_clock_t clock; 841 intel_clock_t clock;
@@ -857,8 +858,8 @@ intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
857} 858}
858 859
859static bool 860static bool
860intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 861intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
861 int target, int refclk, intel_clock_t *best_clock) 862 int target, int refclk, intel_clock_t *best_clock)
862{ 863{
863 struct drm_device *dev = crtc->dev; 864 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private; 865 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -871,7 +872,7 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
871 return true; 872 return true;
872 873
873 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 874 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
874 return intel_find_pll_igdng_dp(limit, crtc, target, 875 return intel_find_pll_ironlake_dp(limit, crtc, target,
875 refclk, best_clock); 876 refclk, best_clock);
876 877
877 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
@@ -949,7 +950,7 @@ void
949intel_wait_for_vblank(struct drm_device *dev) 950intel_wait_for_vblank(struct drm_device *dev)
950{ 951{
951 /* Wait for 20ms, i.e. one cycle at 50hz. */ 952 /* Wait for 20ms, i.e. one cycle at 50hz. */
952 mdelay(20); 953 msleep(20);
953} 954}
954 955
955/* Parameters have changed, update FBC info */ 956/* Parameters have changed, update FBC info */
@@ -994,7 +995,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
994 fbc_ctl |= dev_priv->cfb_fence; 995 fbc_ctl |= dev_priv->cfb_fence;
995 I915_WRITE(FBC_CONTROL, fbc_ctl); 996 I915_WRITE(FBC_CONTROL, fbc_ctl);
996 997
997 DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ", 998 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
998 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); 999 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
999} 1000}
1000 1001
@@ -1017,7 +1018,7 @@ void i8xx_disable_fbc(struct drm_device *dev)
1017 1018
1018 intel_wait_for_vblank(dev); 1019 intel_wait_for_vblank(dev);
1019 1020
1020 DRM_DEBUG("disabled FBC\n"); 1021 DRM_DEBUG_KMS("disabled FBC\n");
1021} 1022}
1022 1023
1023static bool i8xx_fbc_enabled(struct drm_crtc *crtc) 1024static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
@@ -1062,7 +1063,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1062 /* enable it... */ 1063 /* enable it... */
1063 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); 1064 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1064 1065
1065 DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane); 1066 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1066} 1067}
1067 1068
1068void g4x_disable_fbc(struct drm_device *dev) 1069void g4x_disable_fbc(struct drm_device *dev)
@@ -1076,7 +1077,7 @@ void g4x_disable_fbc(struct drm_device *dev)
1076 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 1077 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1077 intel_wait_for_vblank(dev); 1078 intel_wait_for_vblank(dev);
1078 1079
1079 DRM_DEBUG("disabled FBC\n"); 1080 DRM_DEBUG_KMS("disabled FBC\n");
1080} 1081}
1081 1082
1082static bool g4x_fbc_enabled(struct drm_crtc *crtc) 1083static bool g4x_fbc_enabled(struct drm_crtc *crtc)
@@ -1141,25 +1142,27 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1141 * - going to an unsupported config (interlace, pixel multiply, etc.) 1142 * - going to an unsupported config (interlace, pixel multiply, etc.)
1142 */ 1143 */
1143 if (intel_fb->obj->size > dev_priv->cfb_size) { 1144 if (intel_fb->obj->size > dev_priv->cfb_size) {
1144 DRM_DEBUG("framebuffer too large, disabling compression\n"); 1145 DRM_DEBUG_KMS("framebuffer too large, disabling "
1146 "compression\n");
1145 goto out_disable; 1147 goto out_disable;
1146 } 1148 }
1147 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 1149 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1148 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) { 1150 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1149 DRM_DEBUG("mode incompatible with compression, disabling\n"); 1151 DRM_DEBUG_KMS("mode incompatible with compression, "
1152 "disabling\n");
1150 goto out_disable; 1153 goto out_disable;
1151 } 1154 }
1152 if ((mode->hdisplay > 2048) || 1155 if ((mode->hdisplay > 2048) ||
1153 (mode->vdisplay > 1536)) { 1156 (mode->vdisplay > 1536)) {
1154 DRM_DEBUG("mode too large for compression, disabling\n"); 1157 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1155 goto out_disable; 1158 goto out_disable;
1156 } 1159 }
1157 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) { 1160 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1158 DRM_DEBUG("plane not 0, disabling compression\n"); 1161 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1159 goto out_disable; 1162 goto out_disable;
1160 } 1163 }
1161 if (obj_priv->tiling_mode != I915_TILING_X) { 1164 if (obj_priv->tiling_mode != I915_TILING_X) {
1162 DRM_DEBUG("framebuffer not tiled, disabling compression\n"); 1165 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1163 goto out_disable; 1166 goto out_disable;
1164 } 1167 }
1165 1168
@@ -1181,13 +1184,57 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1181 return; 1184 return;
1182 1185
1183out_disable: 1186out_disable:
1184 DRM_DEBUG("unsupported config, disabling FBC\n"); 1187 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1185 /* Multiple disables should be harmless */ 1188 /* Multiple disables should be harmless */
1186 if (dev_priv->display.fbc_enabled(crtc)) 1189 if (dev_priv->display.fbc_enabled(crtc))
1187 dev_priv->display.disable_fbc(dev); 1190 dev_priv->display.disable_fbc(dev);
1188} 1191}
1189 1192
1190static int 1193static int
1194intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1195{
1196 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1197 u32 alignment;
1198 int ret;
1199
1200 switch (obj_priv->tiling_mode) {
1201 case I915_TILING_NONE:
1202 alignment = 64 * 1024;
1203 break;
1204 case I915_TILING_X:
1205 /* pin() will align the object as required by fence */
1206 alignment = 0;
1207 break;
1208 case I915_TILING_Y:
1209 /* FIXME: Is this true? */
1210 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1211 return -EINVAL;
1212 default:
1213 BUG();
1214 }
1215
1216 ret = i915_gem_object_pin(obj, alignment);
1217 if (ret != 0)
1218 return ret;
1219
1220 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1221 * fence, whereas 965+ only requires a fence if using
1222 * framebuffer compression. For simplicity, we always install
1223 * a fence as the cost is not that onerous.
1224 */
1225 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1226 obj_priv->tiling_mode != I915_TILING_NONE) {
1227 ret = i915_gem_object_get_fence_reg(obj);
1228 if (ret != 0) {
1229 i915_gem_object_unpin(obj);
1230 return ret;
1231 }
1232 }
1233
1234 return 0;
1235}
1236
1237static int
1191intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, 1238intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1192 struct drm_framebuffer *old_fb) 1239 struct drm_framebuffer *old_fb)
1193{ 1240{
@@ -1206,12 +1253,12 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1206 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE; 1253 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1207 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF); 1254 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1208 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; 1255 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1209 u32 dspcntr, alignment; 1256 u32 dspcntr;
1210 int ret; 1257 int ret;
1211 1258
1212 /* no fb bound */ 1259 /* no fb bound */
1213 if (!crtc->fb) { 1260 if (!crtc->fb) {
1214 DRM_DEBUG("No FB bound\n"); 1261 DRM_DEBUG_KMS("No FB bound\n");
1215 return 0; 1262 return 0;
1216 } 1263 }
1217 1264
@@ -1228,24 +1275,8 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1228 obj = intel_fb->obj; 1275 obj = intel_fb->obj;
1229 obj_priv = obj->driver_private; 1276 obj_priv = obj->driver_private;
1230 1277
1231 switch (obj_priv->tiling_mode) {
1232 case I915_TILING_NONE:
1233 alignment = 64 * 1024;
1234 break;
1235 case I915_TILING_X:
1236 /* pin() will align the object as required by fence */
1237 alignment = 0;
1238 break;
1239 case I915_TILING_Y:
1240 /* FIXME: Is this true? */
1241 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1242 return -EINVAL;
1243 default:
1244 BUG();
1245 }
1246
1247 mutex_lock(&dev->struct_mutex); 1278 mutex_lock(&dev->struct_mutex);
1248 ret = i915_gem_object_pin(obj, alignment); 1279 ret = intel_pin_and_fence_fb_obj(dev, obj);
1249 if (ret != 0) { 1280 if (ret != 0) {
1250 mutex_unlock(&dev->struct_mutex); 1281 mutex_unlock(&dev->struct_mutex);
1251 return ret; 1282 return ret;
@@ -1258,20 +1289,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1258 return ret; 1289 return ret;
1259 } 1290 }
1260 1291
1261 /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1262 * whereas 965+ only requires a fence if using framebuffer compression.
1263 * For simplicity, we always install a fence as the cost is not that onerous.
1264 */
1265 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1266 obj_priv->tiling_mode != I915_TILING_NONE) {
1267 ret = i915_gem_object_get_fence_reg(obj);
1268 if (ret != 0) {
1269 i915_gem_object_unpin(obj);
1270 mutex_unlock(&dev->struct_mutex);
1271 return ret;
1272 }
1273 }
1274
1275 dspcntr = I915_READ(dspcntr_reg); 1292 dspcntr = I915_READ(dspcntr_reg);
1276 /* Mask out pixel format bits in case we change it */ 1293 /* Mask out pixel format bits in case we change it */
1277 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 1294 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
@@ -1287,7 +1304,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1287 break; 1304 break;
1288 case 24: 1305 case 24:
1289 case 32: 1306 case 32:
1290 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 1307 if (crtc->fb->depth == 30)
1308 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1309 else
1310 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1291 break; 1311 break;
1292 default: 1312 default:
1293 DRM_ERROR("Unknown color depth\n"); 1313 DRM_ERROR("Unknown color depth\n");
@@ -1302,7 +1322,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1302 dspcntr &= ~DISPPLANE_TILED; 1322 dspcntr &= ~DISPPLANE_TILED;
1303 } 1323 }
1304 1324
1305 if (IS_IGDNG(dev)) 1325 if (IS_IRONLAKE(dev))
1306 /* must disable */ 1326 /* must disable */
1307 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 1327 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1308 1328
@@ -1311,7 +1331,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1311 Start = obj_priv->gtt_offset; 1331 Start = obj_priv->gtt_offset;
1312 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); 1332 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1313 1333
1314 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); 1334 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1315 I915_WRITE(dspstride, crtc->fb->pitch); 1335 I915_WRITE(dspstride, crtc->fb->pitch);
1316 if (IS_I965G(dev)) { 1336 if (IS_I965G(dev)) {
1317 I915_WRITE(dspbase, Offset); 1337 I915_WRITE(dspbase, Offset);
@@ -1363,7 +1383,7 @@ static void i915_disable_vga (struct drm_device *dev)
1363 u8 sr1; 1383 u8 sr1;
1364 u32 vga_reg; 1384 u32 vga_reg;
1365 1385
1366 if (IS_IGDNG(dev)) 1386 if (IS_IRONLAKE(dev))
1367 vga_reg = CPU_VGACNTRL; 1387 vga_reg = CPU_VGACNTRL;
1368 else 1388 else
1369 vga_reg = VGACNTRL; 1389 vga_reg = VGACNTRL;
@@ -1379,19 +1399,19 @@ static void i915_disable_vga (struct drm_device *dev)
1379 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 1399 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1380} 1400}
1381 1401
1382static void igdng_disable_pll_edp (struct drm_crtc *crtc) 1402static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1383{ 1403{
1384 struct drm_device *dev = crtc->dev; 1404 struct drm_device *dev = crtc->dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private; 1405 struct drm_i915_private *dev_priv = dev->dev_private;
1386 u32 dpa_ctl; 1406 u32 dpa_ctl;
1387 1407
1388 DRM_DEBUG("\n"); 1408 DRM_DEBUG_KMS("\n");
1389 dpa_ctl = I915_READ(DP_A); 1409 dpa_ctl = I915_READ(DP_A);
1390 dpa_ctl &= ~DP_PLL_ENABLE; 1410 dpa_ctl &= ~DP_PLL_ENABLE;
1391 I915_WRITE(DP_A, dpa_ctl); 1411 I915_WRITE(DP_A, dpa_ctl);
1392} 1412}
1393 1413
1394static void igdng_enable_pll_edp (struct drm_crtc *crtc) 1414static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1395{ 1415{
1396 struct drm_device *dev = crtc->dev; 1416 struct drm_device *dev = crtc->dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private; 1417 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1404,13 +1424,13 @@ static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1404} 1424}
1405 1425
1406 1426
1407static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock) 1427static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1408{ 1428{
1409 struct drm_device *dev = crtc->dev; 1429 struct drm_device *dev = crtc->dev;
1410 struct drm_i915_private *dev_priv = dev->dev_private; 1430 struct drm_i915_private *dev_priv = dev->dev_private;
1411 u32 dpa_ctl; 1431 u32 dpa_ctl;
1412 1432
1413 DRM_DEBUG("eDP PLL enable for clock %d\n", clock); 1433 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1414 dpa_ctl = I915_READ(DP_A); 1434 dpa_ctl = I915_READ(DP_A);
1415 dpa_ctl &= ~DP_PLL_FREQ_MASK; 1435 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1416 1436
@@ -1440,7 +1460,7 @@ static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1440 udelay(500); 1460 udelay(500);
1441} 1461}
1442 1462
1443static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) 1463static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1444{ 1464{
1445 struct drm_device *dev = crtc->dev; 1465 struct drm_device *dev = crtc->dev;
1446 struct drm_i915_private *dev_priv = dev->dev_private; 1466 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1481,10 +1501,19 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1481 case DRM_MODE_DPMS_ON: 1501 case DRM_MODE_DPMS_ON:
1482 case DRM_MODE_DPMS_STANDBY: 1502 case DRM_MODE_DPMS_STANDBY:
1483 case DRM_MODE_DPMS_SUSPEND: 1503 case DRM_MODE_DPMS_SUSPEND:
1484 DRM_DEBUG("crtc %d dpms on\n", pipe); 1504 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1505
1506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1507 temp = I915_READ(PCH_LVDS);
1508 if ((temp & LVDS_PORT_EN) == 0) {
1509 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1510 POSTING_READ(PCH_LVDS);
1511 }
1512 }
1513
1485 if (HAS_eDP) { 1514 if (HAS_eDP) {
1486 /* enable eDP PLL */ 1515 /* enable eDP PLL */
1487 igdng_enable_pll_edp(crtc); 1516 ironlake_enable_pll_edp(crtc);
1488 } else { 1517 } else {
1489 /* enable PCH DPLL */ 1518 /* enable PCH DPLL */
1490 temp = I915_READ(pch_dpll_reg); 1519 temp = I915_READ(pch_dpll_reg);
@@ -1501,7 +1530,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1501 I915_READ(fdi_rx_reg); 1530 I915_READ(fdi_rx_reg);
1502 udelay(200); 1531 udelay(200);
1503 1532
1504 /* Enable CPU FDI TX PLL, always on for IGDNG */ 1533 /* Enable CPU FDI TX PLL, always on for Ironlake */
1505 temp = I915_READ(fdi_tx_reg); 1534 temp = I915_READ(fdi_tx_reg);
1506 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 1535 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1507 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); 1536 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
@@ -1568,12 +1597,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1568 udelay(150); 1597 udelay(150);
1569 1598
1570 temp = I915_READ(fdi_rx_iir_reg); 1599 temp = I915_READ(fdi_rx_iir_reg);
1571 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1600 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1572 1601
1573 if ((temp & FDI_RX_BIT_LOCK) == 0) { 1602 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1574 for (j = 0; j < tries; j++) { 1603 for (j = 0; j < tries; j++) {
1575 temp = I915_READ(fdi_rx_iir_reg); 1604 temp = I915_READ(fdi_rx_iir_reg);
1576 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1605 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1606 temp);
1577 if (temp & FDI_RX_BIT_LOCK) 1607 if (temp & FDI_RX_BIT_LOCK)
1578 break; 1608 break;
1579 udelay(200); 1609 udelay(200);
@@ -1582,11 +1612,11 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1582 I915_WRITE(fdi_rx_iir_reg, 1612 I915_WRITE(fdi_rx_iir_reg,
1583 temp | FDI_RX_BIT_LOCK); 1613 temp | FDI_RX_BIT_LOCK);
1584 else 1614 else
1585 DRM_DEBUG("train 1 fail\n"); 1615 DRM_DEBUG_KMS("train 1 fail\n");
1586 } else { 1616 } else {
1587 I915_WRITE(fdi_rx_iir_reg, 1617 I915_WRITE(fdi_rx_iir_reg,
1588 temp | FDI_RX_BIT_LOCK); 1618 temp | FDI_RX_BIT_LOCK);
1589 DRM_DEBUG("train 1 ok 2!\n"); 1619 DRM_DEBUG_KMS("train 1 ok 2!\n");
1590 } 1620 }
1591 temp = I915_READ(fdi_tx_reg); 1621 temp = I915_READ(fdi_tx_reg);
1592 temp &= ~FDI_LINK_TRAIN_NONE; 1622 temp &= ~FDI_LINK_TRAIN_NONE;
@@ -1601,12 +1631,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1601 udelay(150); 1631 udelay(150);
1602 1632
1603 temp = I915_READ(fdi_rx_iir_reg); 1633 temp = I915_READ(fdi_rx_iir_reg);
1604 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1634 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1605 1635
1606 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { 1636 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1607 for (j = 0; j < tries; j++) { 1637 for (j = 0; j < tries; j++) {
1608 temp = I915_READ(fdi_rx_iir_reg); 1638 temp = I915_READ(fdi_rx_iir_reg);
1609 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1639 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1640 temp);
1610 if (temp & FDI_RX_SYMBOL_LOCK) 1641 if (temp & FDI_RX_SYMBOL_LOCK)
1611 break; 1642 break;
1612 udelay(200); 1643 udelay(200);
@@ -1614,15 +1645,15 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1614 if (j != tries) { 1645 if (j != tries) {
1615 I915_WRITE(fdi_rx_iir_reg, 1646 I915_WRITE(fdi_rx_iir_reg,
1616 temp | FDI_RX_SYMBOL_LOCK); 1647 temp | FDI_RX_SYMBOL_LOCK);
1617 DRM_DEBUG("train 2 ok 1!\n"); 1648 DRM_DEBUG_KMS("train 2 ok 1!\n");
1618 } else 1649 } else
1619 DRM_DEBUG("train 2 fail\n"); 1650 DRM_DEBUG_KMS("train 2 fail\n");
1620 } else { 1651 } else {
1621 I915_WRITE(fdi_rx_iir_reg, 1652 I915_WRITE(fdi_rx_iir_reg,
1622 temp | FDI_RX_SYMBOL_LOCK); 1653 temp | FDI_RX_SYMBOL_LOCK);
1623 DRM_DEBUG("train 2 ok 2!\n"); 1654 DRM_DEBUG_KMS("train 2 ok 2!\n");
1624 } 1655 }
1625 DRM_DEBUG("train done\n"); 1656 DRM_DEBUG_KMS("train done\n");
1626 1657
1627 /* set transcoder timing */ 1658 /* set transcoder timing */
1628 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); 1659 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
@@ -1664,9 +1695,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1664 1695
1665 break; 1696 break;
1666 case DRM_MODE_DPMS_OFF: 1697 case DRM_MODE_DPMS_OFF:
1667 DRM_DEBUG("crtc %d dpms off\n", pipe); 1698 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1668
1669 i915_disable_vga(dev);
1670 1699
1671 /* Disable display plane */ 1700 /* Disable display plane */
1672 temp = I915_READ(dspcntr_reg); 1701 temp = I915_READ(dspcntr_reg);
@@ -1677,6 +1706,8 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1677 I915_READ(dspbase_reg); 1706 I915_READ(dspbase_reg);
1678 } 1707 }
1679 1708
1709 i915_disable_vga(dev);
1710
1680 /* disable cpu pipe, disable after all planes disabled */ 1711 /* disable cpu pipe, disable after all planes disabled */
1681 temp = I915_READ(pipeconf_reg); 1712 temp = I915_READ(pipeconf_reg);
1682 if ((temp & PIPEACONF_ENABLE) != 0) { 1713 if ((temp & PIPEACONF_ENABLE) != 0) {
@@ -1690,16 +1721,23 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1690 udelay(500); 1721 udelay(500);
1691 continue; 1722 continue;
1692 } else { 1723 } else {
1693 DRM_DEBUG("pipe %d off delay\n", pipe); 1724 DRM_DEBUG_KMS("pipe %d off delay\n",
1725 pipe);
1694 break; 1726 break;
1695 } 1727 }
1696 } 1728 }
1697 } else 1729 } else
1698 DRM_DEBUG("crtc %d is disabled\n", pipe); 1730 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1699 1731
1700 if (HAS_eDP) { 1732 udelay(100);
1701 igdng_disable_pll_edp(crtc); 1733
1734 /* Disable PF */
1735 temp = I915_READ(pf_ctl_reg);
1736 if ((temp & PF_ENABLE) != 0) {
1737 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1738 I915_READ(pf_ctl_reg);
1702 } 1739 }
1740 I915_WRITE(pf_win_size, 0);
1703 1741
1704 /* disable CPU FDI tx and PCH FDI rx */ 1742 /* disable CPU FDI tx and PCH FDI rx */
1705 temp = I915_READ(fdi_tx_reg); 1743 temp = I915_READ(fdi_tx_reg);
@@ -1725,6 +1763,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1725 1763
1726 udelay(100); 1764 udelay(100);
1727 1765
1766 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1767 temp = I915_READ(PCH_LVDS);
1768 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1769 I915_READ(PCH_LVDS);
1770 udelay(100);
1771 }
1772
1728 /* disable PCH transcoder */ 1773 /* disable PCH transcoder */
1729 temp = I915_READ(transconf_reg); 1774 temp = I915_READ(transconf_reg);
1730 if ((temp & TRANS_ENABLE) != 0) { 1775 if ((temp & TRANS_ENABLE) != 0) {
@@ -1738,12 +1783,15 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1738 udelay(500); 1783 udelay(500);
1739 continue; 1784 continue;
1740 } else { 1785 } else {
1741 DRM_DEBUG("transcoder %d off delay\n", pipe); 1786 DRM_DEBUG_KMS("transcoder %d off "
1787 "delay\n", pipe);
1742 break; 1788 break;
1743 } 1789 }
1744 } 1790 }
1745 } 1791 }
1746 1792
1793 udelay(100);
1794
1747 /* disable PCH DPLL */ 1795 /* disable PCH DPLL */
1748 temp = I915_READ(pch_dpll_reg); 1796 temp = I915_READ(pch_dpll_reg);
1749 if ((temp & DPLL_VCO_ENABLE) != 0) { 1797 if ((temp & DPLL_VCO_ENABLE) != 0) {
@@ -1751,14 +1799,20 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1751 I915_READ(pch_dpll_reg); 1799 I915_READ(pch_dpll_reg);
1752 } 1800 }
1753 1801
1754 temp = I915_READ(fdi_rx_reg); 1802 if (HAS_eDP) {
1755 if ((temp & FDI_RX_PLL_ENABLE) != 0) { 1803 ironlake_disable_pll_edp(crtc);
1756 temp &= ~FDI_SEL_PCDCLK;
1757 temp &= ~FDI_RX_PLL_ENABLE;
1758 I915_WRITE(fdi_rx_reg, temp);
1759 I915_READ(fdi_rx_reg);
1760 } 1804 }
1761 1805
1806 temp = I915_READ(fdi_rx_reg);
1807 temp &= ~FDI_SEL_PCDCLK;
1808 I915_WRITE(fdi_rx_reg, temp);
1809 I915_READ(fdi_rx_reg);
1810
1811 temp = I915_READ(fdi_rx_reg);
1812 temp &= ~FDI_RX_PLL_ENABLE;
1813 I915_WRITE(fdi_rx_reg, temp);
1814 I915_READ(fdi_rx_reg);
1815
1762 /* Disable CPU FDI TX PLL */ 1816 /* Disable CPU FDI TX PLL */
1763 temp = I915_READ(fdi_tx_reg); 1817 temp = I915_READ(fdi_tx_reg);
1764 if ((temp & FDI_TX_PLL_ENABLE) != 0) { 1818 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
@@ -1767,20 +1821,43 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1767 udelay(100); 1821 udelay(100);
1768 } 1822 }
1769 1823
1770 /* Disable PF */
1771 temp = I915_READ(pf_ctl_reg);
1772 if ((temp & PF_ENABLE) != 0) {
1773 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1774 I915_READ(pf_ctl_reg);
1775 }
1776 I915_WRITE(pf_win_size, 0);
1777
1778 /* Wait for the clocks to turn off. */ 1824 /* Wait for the clocks to turn off. */
1779 udelay(150); 1825 udelay(100);
1780 break; 1826 break;
1781 } 1827 }
1782} 1828}
1783 1829
1830static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1831{
1832 struct intel_overlay *overlay;
1833 int ret;
1834
1835 if (!enable && intel_crtc->overlay) {
1836 overlay = intel_crtc->overlay;
1837 mutex_lock(&overlay->dev->struct_mutex);
1838 for (;;) {
1839 ret = intel_overlay_switch_off(overlay);
1840 if (ret == 0)
1841 break;
1842
1843 ret = intel_overlay_recover_from_interrupt(overlay, 0);
1844 if (ret != 0) {
1845 /* overlay doesn't react anymore. Usually
1846 * results in a black screen and an unkillable
1847 * X server. */
1848 BUG();
1849 overlay->hw_wedged = HW_WEDGED;
1850 break;
1851 }
1852 }
1853 mutex_unlock(&overlay->dev->struct_mutex);
1854 }
1855 /* Let userspace switch the overlay on again. In most cases userspace
1856 * has to recompute where to put it anyway. */
1857
1858 return;
1859}
1860
1784static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) 1861static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1785{ 1862{
1786 struct drm_device *dev = crtc->dev; 1863 struct drm_device *dev = crtc->dev;
@@ -1839,12 +1916,14 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1839 intel_update_fbc(crtc, &crtc->mode); 1916 intel_update_fbc(crtc, &crtc->mode);
1840 1917
1841 /* Give the overlay scaler a chance to enable if it's on this pipe */ 1918 /* Give the overlay scaler a chance to enable if it's on this pipe */
1842 //intel_crtc_dpms_video(crtc, true); TODO 1919 intel_crtc_dpms_overlay(intel_crtc, true);
1843 break; 1920 break;
1844 case DRM_MODE_DPMS_OFF: 1921 case DRM_MODE_DPMS_OFF:
1845 intel_update_watermarks(dev); 1922 intel_update_watermarks(dev);
1923
1846 /* Give the overlay scaler a chance to disable if it's on this pipe */ 1924 /* Give the overlay scaler a chance to disable if it's on this pipe */
1847 //intel_crtc_dpms_video(crtc, FALSE); TODO 1925 intel_crtc_dpms_overlay(intel_crtc, false);
1926 drm_vblank_off(dev, pipe);
1848 1927
1849 if (dev_priv->cfb_plane == plane && 1928 if (dev_priv->cfb_plane == plane &&
1850 dev_priv->display.disable_fbc) 1929 dev_priv->display.disable_fbc)
@@ -1963,7 +2042,7 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1963 struct drm_display_mode *adjusted_mode) 2042 struct drm_display_mode *adjusted_mode)
1964{ 2043{
1965 struct drm_device *dev = crtc->dev; 2044 struct drm_device *dev = crtc->dev;
1966 if (IS_IGDNG(dev)) { 2045 if (IS_IRONLAKE(dev)) {
1967 /* FDI link clock is fixed at 2.7G */ 2046 /* FDI link clock is fixed at 2.7G */
1968 if (mode->clock * 3 > 27000 * 4) 2047 if (mode->clock * 3 > 27000 * 4)
1969 return MODE_CLOCK_HIGH; 2048 return MODE_CLOCK_HIGH;
@@ -2039,7 +2118,7 @@ static int i830_get_display_clock_speed(struct drm_device *dev)
2039 * Return the pipe currently connected to the panel fitter, 2118 * Return the pipe currently connected to the panel fitter,
2040 * or -1 if the panel fitter is not present or not in use 2119 * or -1 if the panel fitter is not present or not in use
2041 */ 2120 */
2042static int intel_panel_fitter_pipe (struct drm_device *dev) 2121int intel_panel_fitter_pipe (struct drm_device *dev)
2043{ 2122{
2044 struct drm_i915_private *dev_priv = dev->dev_private; 2123 struct drm_i915_private *dev_priv = dev->dev_private;
2045 u32 pfit_control; 2124 u32 pfit_control;
@@ -2083,9 +2162,8 @@ fdi_reduce_ratio(u32 *num, u32 *den)
2083#define LINK_N 0x80000 2162#define LINK_N 0x80000
2084 2163
2085static void 2164static void
2086igdng_compute_m_n(int bits_per_pixel, int nlanes, 2165ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2087 int pixel_clock, int link_clock, 2166 int link_clock, struct fdi_m_n *m_n)
2088 struct fdi_m_n *m_n)
2089{ 2167{
2090 u64 temp; 2168 u64 temp;
2091 2169
@@ -2113,34 +2191,34 @@ struct intel_watermark_params {
2113 unsigned long cacheline_size; 2191 unsigned long cacheline_size;
2114}; 2192};
2115 2193
2116/* IGD has different values for various configs */ 2194/* Pineview has different values for various configs */
2117static struct intel_watermark_params igd_display_wm = { 2195static struct intel_watermark_params pineview_display_wm = {
2118 IGD_DISPLAY_FIFO, 2196 PINEVIEW_DISPLAY_FIFO,
2119 IGD_MAX_WM, 2197 PINEVIEW_MAX_WM,
2120 IGD_DFT_WM, 2198 PINEVIEW_DFT_WM,
2121 IGD_GUARD_WM, 2199 PINEVIEW_GUARD_WM,
2122 IGD_FIFO_LINE_SIZE 2200 PINEVIEW_FIFO_LINE_SIZE
2123}; 2201};
2124static struct intel_watermark_params igd_display_hplloff_wm = { 2202static struct intel_watermark_params pineview_display_hplloff_wm = {
2125 IGD_DISPLAY_FIFO, 2203 PINEVIEW_DISPLAY_FIFO,
2126 IGD_MAX_WM, 2204 PINEVIEW_MAX_WM,
2127 IGD_DFT_HPLLOFF_WM, 2205 PINEVIEW_DFT_HPLLOFF_WM,
2128 IGD_GUARD_WM, 2206 PINEVIEW_GUARD_WM,
2129 IGD_FIFO_LINE_SIZE 2207 PINEVIEW_FIFO_LINE_SIZE
2130}; 2208};
2131static struct intel_watermark_params igd_cursor_wm = { 2209static struct intel_watermark_params pineview_cursor_wm = {
2132 IGD_CURSOR_FIFO, 2210 PINEVIEW_CURSOR_FIFO,
2133 IGD_CURSOR_MAX_WM, 2211 PINEVIEW_CURSOR_MAX_WM,
2134 IGD_CURSOR_DFT_WM, 2212 PINEVIEW_CURSOR_DFT_WM,
2135 IGD_CURSOR_GUARD_WM, 2213 PINEVIEW_CURSOR_GUARD_WM,
2136 IGD_FIFO_LINE_SIZE, 2214 PINEVIEW_FIFO_LINE_SIZE,
2137}; 2215};
2138static struct intel_watermark_params igd_cursor_hplloff_wm = { 2216static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2139 IGD_CURSOR_FIFO, 2217 PINEVIEW_CURSOR_FIFO,
2140 IGD_CURSOR_MAX_WM, 2218 PINEVIEW_CURSOR_MAX_WM,
2141 IGD_CURSOR_DFT_WM, 2219 PINEVIEW_CURSOR_DFT_WM,
2142 IGD_CURSOR_GUARD_WM, 2220 PINEVIEW_CURSOR_GUARD_WM,
2143 IGD_FIFO_LINE_SIZE 2221 PINEVIEW_FIFO_LINE_SIZE
2144}; 2222};
2145static struct intel_watermark_params g4x_wm_info = { 2223static struct intel_watermark_params g4x_wm_info = {
2146 G4X_FIFO_SIZE, 2224 G4X_FIFO_SIZE,
@@ -2213,11 +2291,11 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2213 1000; 2291 1000;
2214 entries_required /= wm->cacheline_size; 2292 entries_required /= wm->cacheline_size;
2215 2293
2216 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required); 2294 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2217 2295
2218 wm_size = wm->fifo_size - (entries_required + wm->guard_size); 2296 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2219 2297
2220 DRM_DEBUG("FIFO watermark level: %d\n", wm_size); 2298 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2221 2299
2222 /* Don't promote wm_size to unsigned... */ 2300 /* Don't promote wm_size to unsigned... */
2223 if (wm_size > (long)wm->max_wm) 2301 if (wm_size > (long)wm->max_wm)
@@ -2279,50 +2357,50 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2279 return latency; 2357 return latency;
2280 } 2358 }
2281 2359
2282 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n"); 2360 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2283 2361
2284 return NULL; 2362 return NULL;
2285} 2363}
2286 2364
2287static void igd_disable_cxsr(struct drm_device *dev) 2365static void pineview_disable_cxsr(struct drm_device *dev)
2288{ 2366{
2289 struct drm_i915_private *dev_priv = dev->dev_private; 2367 struct drm_i915_private *dev_priv = dev->dev_private;
2290 u32 reg; 2368 u32 reg;
2291 2369
2292 /* deactivate cxsr */ 2370 /* deactivate cxsr */
2293 reg = I915_READ(DSPFW3); 2371 reg = I915_READ(DSPFW3);
2294 reg &= ~(IGD_SELF_REFRESH_EN); 2372 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2295 I915_WRITE(DSPFW3, reg); 2373 I915_WRITE(DSPFW3, reg);
2296 DRM_INFO("Big FIFO is disabled\n"); 2374 DRM_INFO("Big FIFO is disabled\n");
2297} 2375}
2298 2376
2299static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock, 2377static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2300 int pixel_size) 2378 int pixel_size)
2301{ 2379{
2302 struct drm_i915_private *dev_priv = dev->dev_private; 2380 struct drm_i915_private *dev_priv = dev->dev_private;
2303 u32 reg; 2381 u32 reg;
2304 unsigned long wm; 2382 unsigned long wm;
2305 struct cxsr_latency *latency; 2383 struct cxsr_latency *latency;
2306 2384
2307 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq, 2385 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2308 dev_priv->mem_freq); 2386 dev_priv->mem_freq);
2309 if (!latency) { 2387 if (!latency) {
2310 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n"); 2388 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2311 igd_disable_cxsr(dev); 2389 pineview_disable_cxsr(dev);
2312 return; 2390 return;
2313 } 2391 }
2314 2392
2315 /* Display SR */ 2393 /* Display SR */
2316 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size, 2394 wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2317 latency->display_sr); 2395 latency->display_sr);
2318 reg = I915_READ(DSPFW1); 2396 reg = I915_READ(DSPFW1);
2319 reg &= 0x7fffff; 2397 reg &= 0x7fffff;
2320 reg |= wm << 23; 2398 reg |= wm << 23;
2321 I915_WRITE(DSPFW1, reg); 2399 I915_WRITE(DSPFW1, reg);
2322 DRM_DEBUG("DSPFW1 register is %x\n", reg); 2400 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2323 2401
2324 /* cursor SR */ 2402 /* cursor SR */
2325 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size, 2403 wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2326 latency->cursor_sr); 2404 latency->cursor_sr);
2327 reg = I915_READ(DSPFW3); 2405 reg = I915_READ(DSPFW3);
2328 reg &= ~(0x3f << 24); 2406 reg &= ~(0x3f << 24);
@@ -2330,7 +2408,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2330 I915_WRITE(DSPFW3, reg); 2408 I915_WRITE(DSPFW3, reg);
2331 2409
2332 /* Display HPLL off SR */ 2410 /* Display HPLL off SR */
2333 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm, 2411 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2334 latency->display_hpll_disable, I915_FIFO_LINE_SIZE); 2412 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2335 reg = I915_READ(DSPFW3); 2413 reg = I915_READ(DSPFW3);
2336 reg &= 0xfffffe00; 2414 reg &= 0xfffffe00;
@@ -2338,17 +2416,17 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2338 I915_WRITE(DSPFW3, reg); 2416 I915_WRITE(DSPFW3, reg);
2339 2417
2340 /* cursor HPLL off SR */ 2418 /* cursor HPLL off SR */
2341 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size, 2419 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2342 latency->cursor_hpll_disable); 2420 latency->cursor_hpll_disable);
2343 reg = I915_READ(DSPFW3); 2421 reg = I915_READ(DSPFW3);
2344 reg &= ~(0x3f << 16); 2422 reg &= ~(0x3f << 16);
2345 reg |= (wm & 0x3f) << 16; 2423 reg |= (wm & 0x3f) << 16;
2346 I915_WRITE(DSPFW3, reg); 2424 I915_WRITE(DSPFW3, reg);
2347 DRM_DEBUG("DSPFW3 register is %x\n", reg); 2425 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2348 2426
2349 /* activate cxsr */ 2427 /* activate cxsr */
2350 reg = I915_READ(DSPFW3); 2428 reg = I915_READ(DSPFW3);
2351 reg |= IGD_SELF_REFRESH_EN; 2429 reg |= PINEVIEW_SELF_REFRESH_EN;
2352 I915_WRITE(DSPFW3, reg); 2430 I915_WRITE(DSPFW3, reg);
2353 2431
2354 DRM_INFO("Big FIFO is enabled\n"); 2432 DRM_INFO("Big FIFO is enabled\n");
@@ -2384,8 +2462,8 @@ static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2384 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - 2462 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2385 (dsparb & 0x7f); 2463 (dsparb & 0x7f);
2386 2464
2387 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2465 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2388 size); 2466 plane ? "B" : "A", size);
2389 2467
2390 return size; 2468 return size;
2391} 2469}
@@ -2403,8 +2481,8 @@ static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2403 (dsparb & 0x1ff); 2481 (dsparb & 0x1ff);
2404 size >>= 1; /* Convert to cachelines */ 2482 size >>= 1; /* Convert to cachelines */
2405 2483
2406 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2484 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2407 size); 2485 plane ? "B" : "A", size);
2408 2486
2409 return size; 2487 return size;
2410} 2488}
@@ -2418,7 +2496,8 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
2418 size = dsparb & 0x7f; 2496 size = dsparb & 0x7f;
2419 size >>= 2; /* Convert to cachelines */ 2497 size >>= 2; /* Convert to cachelines */
2420 2498
2421 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2499 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2500 plane ? "B" : "A",
2422 size); 2501 size);
2423 2502
2424 return size; 2503 return size;
@@ -2433,8 +2512,8 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
2433 size = dsparb & 0x7f; 2512 size = dsparb & 0x7f;
2434 size >>= 1; /* Convert to cachelines */ 2513 size >>= 1; /* Convert to cachelines */
2435 2514
2436 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2515 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2437 size); 2516 plane ? "B" : "A", size);
2438 2517
2439 return size; 2518 return size;
2440} 2519}
@@ -2509,15 +2588,39 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2509 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 2588 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2510} 2589}
2511 2590
2512static void i965_update_wm(struct drm_device *dev, int unused, int unused2, 2591static void i965_update_wm(struct drm_device *dev, int planea_clock,
2513 int unused3, int unused4) 2592 int planeb_clock, int sr_hdisplay, int pixel_size)
2514{ 2593{
2515 struct drm_i915_private *dev_priv = dev->dev_private; 2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 unsigned long line_time_us;
2596 int sr_clock, sr_entries, srwm = 1;
2597
2598 /* Calc sr entries for one plane configs */
2599 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2600 /* self-refresh has much higher latency */
2601 const static int sr_latency_ns = 12000;
2602
2603 sr_clock = planea_clock ? planea_clock : planeb_clock;
2604 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2605
2606 /* Use ns/us then divide to preserve precision */
2607 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2608 pixel_size * sr_hdisplay) / 1000;
2609 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2610 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2611 srwm = I945_FIFO_SIZE - sr_entries;
2612 if (srwm < 0)
2613 srwm = 1;
2614 srwm &= 0x3f;
2615 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2616 }
2516 2617
2517 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n"); 2618 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2619 srwm);
2518 2620
2519 /* 965 has limitations... */ 2621 /* 965 has limitations... */
2520 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0)); 2622 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2623 (8 << 0));
2521 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 2624 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2522} 2625}
2523 2626
@@ -2553,7 +2656,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2553 pixel_size, latency_ns); 2656 pixel_size, latency_ns);
2554 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, 2657 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2555 pixel_size, latency_ns); 2658 pixel_size, latency_ns);
2556 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 2659 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2557 2660
2558 /* 2661 /*
2559 * Overlay gets an aggressive default since video jitter is bad. 2662 * Overlay gets an aggressive default since video jitter is bad.
@@ -2573,14 +2676,14 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2573 sr_entries = (((sr_latency_ns / line_time_us) + 1) * 2676 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2574 pixel_size * sr_hdisplay) / 1000; 2677 pixel_size * sr_hdisplay) / 1000;
2575 sr_entries = roundup(sr_entries / cacheline_size, 1); 2678 sr_entries = roundup(sr_entries / cacheline_size, 1);
2576 DRM_DEBUG("self-refresh entries: %d\n", sr_entries); 2679 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2577 srwm = total_size - sr_entries; 2680 srwm = total_size - sr_entries;
2578 if (srwm < 0) 2681 if (srwm < 0)
2579 srwm = 1; 2682 srwm = 1;
2580 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); 2683 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2581 } 2684 }
2582 2685
2583 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 2686 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2584 planea_wm, planeb_wm, cwm, srwm); 2687 planea_wm, planeb_wm, cwm, srwm);
2585 2688
2586 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 2689 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
@@ -2607,7 +2710,7 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2607 pixel_size, latency_ns); 2710 pixel_size, latency_ns);
2608 fwater_lo |= (3<<8) | planea_wm; 2711 fwater_lo |= (3<<8) | planea_wm;
2609 2712
2610 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm); 2713 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2611 2714
2612 I915_WRITE(FW_BLC, fwater_lo); 2715 I915_WRITE(FW_BLC, fwater_lo);
2613} 2716}
@@ -2661,11 +2764,11 @@ static void intel_update_watermarks(struct drm_device *dev)
2661 if (crtc->enabled) { 2764 if (crtc->enabled) {
2662 enabled++; 2765 enabled++;
2663 if (intel_crtc->plane == 0) { 2766 if (intel_crtc->plane == 0) {
2664 DRM_DEBUG("plane A (pipe %d) clock: %d\n", 2767 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2665 intel_crtc->pipe, crtc->mode.clock); 2768 intel_crtc->pipe, crtc->mode.clock);
2666 planea_clock = crtc->mode.clock; 2769 planea_clock = crtc->mode.clock;
2667 } else { 2770 } else {
2668 DRM_DEBUG("plane B (pipe %d) clock: %d\n", 2771 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2669 intel_crtc->pipe, crtc->mode.clock); 2772 intel_crtc->pipe, crtc->mode.clock);
2670 planeb_clock = crtc->mode.clock; 2773 planeb_clock = crtc->mode.clock;
2671 } 2774 }
@@ -2682,10 +2785,10 @@ static void intel_update_watermarks(struct drm_device *dev)
2682 return; 2785 return;
2683 2786
2684 /* Single plane configs can enable self refresh */ 2787 /* Single plane configs can enable self refresh */
2685 if (enabled == 1 && IS_IGD(dev)) 2788 if (enabled == 1 && IS_PINEVIEW(dev))
2686 igd_enable_cxsr(dev, sr_clock, pixel_size); 2789 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2687 else if (IS_IGD(dev)) 2790 else if (IS_PINEVIEW(dev))
2688 igd_disable_cxsr(dev); 2791 pineview_disable_cxsr(dev);
2689 2792
2690 dev_priv->display.update_wm(dev, planea_clock, planeb_clock, 2793 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2691 sr_hdisplay, pixel_size); 2794 sr_hdisplay, pixel_size);
@@ -2779,10 +2882,11 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2779 2882
2780 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) { 2883 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2781 refclk = dev_priv->lvds_ssc_freq * 1000; 2884 refclk = dev_priv->lvds_ssc_freq * 1000;
2782 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000); 2885 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2886 refclk / 1000);
2783 } else if (IS_I9XX(dev)) { 2887 } else if (IS_I9XX(dev)) {
2784 refclk = 96000; 2888 refclk = 96000;
2785 if (IS_IGDNG(dev)) 2889 if (IS_IRONLAKE(dev))
2786 refclk = 120000; /* 120Mhz refclk */ 2890 refclk = 120000; /* 120Mhz refclk */
2787 } else { 2891 } else {
2788 refclk = 48000; 2892 refclk = 48000;
@@ -2802,14 +2906,25 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2802 return -EINVAL; 2906 return -EINVAL;
2803 } 2907 }
2804 2908
2805 if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) { 2909 if (is_lvds && limit->find_reduced_pll &&
2910 dev_priv->lvds_downclock_avail) {
2806 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t)); 2911 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2807 has_reduced_clock = limit->find_reduced_pll(limit, crtc, 2912 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2808 (adjusted_mode->clock*3/4), 2913 dev_priv->lvds_downclock,
2809 refclk, 2914 refclk,
2810 &reduced_clock); 2915 &reduced_clock);
2916 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2917 /*
2918 * If the different P is found, it means that we can't
2919 * switch the display clock by using the FP0/FP1.
2920 * In such case we will disable the LVDS downclock
2921 * feature.
2922 */
2923 DRM_DEBUG_KMS("Different P is found for "
2924 "LVDS clock/downclock\n");
2925 has_reduced_clock = 0;
2926 }
2811 } 2927 }
2812
2813 /* SDVO TV has fixed PLL values depend on its clock range, 2928 /* SDVO TV has fixed PLL values depend on its clock range,
2814 this mirrors vbios setting. */ 2929 this mirrors vbios setting. */
2815 if (is_sdvo && is_tv) { 2930 if (is_sdvo && is_tv) {
@@ -2831,7 +2946,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2831 } 2946 }
2832 2947
2833 /* FDI link */ 2948 /* FDI link */
2834 if (IS_IGDNG(dev)) { 2949 if (IS_IRONLAKE(dev)) {
2835 int lane, link_bw, bpp; 2950 int lane, link_bw, bpp;
2836 /* eDP doesn't require FDI link, so just set DP M/N 2951 /* eDP doesn't require FDI link, so just set DP M/N
2837 according to current link config */ 2952 according to current link config */
@@ -2873,8 +2988,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2873 bpp = 24; 2988 bpp = 24;
2874 } 2989 }
2875 2990
2876 igdng_compute_m_n(bpp, lane, target_clock, 2991 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
2877 link_bw, &m_n);
2878 } 2992 }
2879 2993
2880 /* Ironlake: try to setup display ref clock before DPLL 2994 /* Ironlake: try to setup display ref clock before DPLL
@@ -2882,7 +2996,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2882 * PCH B stepping, previous chipset stepping should be 2996 * PCH B stepping, previous chipset stepping should be
2883 * ignoring this setting. 2997 * ignoring this setting.
2884 */ 2998 */
2885 if (IS_IGDNG(dev)) { 2999 if (IS_IRONLAKE(dev)) {
2886 temp = I915_READ(PCH_DREF_CONTROL); 3000 temp = I915_READ(PCH_DREF_CONTROL);
2887 /* Always enable nonspread source */ 3001 /* Always enable nonspread source */
2888 temp &= ~DREF_NONSPREAD_SOURCE_MASK; 3002 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
@@ -2917,7 +3031,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2917 } 3031 }
2918 } 3032 }
2919 3033
2920 if (IS_IGD(dev)) { 3034 if (IS_PINEVIEW(dev)) {
2921 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; 3035 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2922 if (has_reduced_clock) 3036 if (has_reduced_clock)
2923 fp2 = (1 << reduced_clock.n) << 16 | 3037 fp2 = (1 << reduced_clock.n) << 16 |
@@ -2929,7 +3043,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2929 reduced_clock.m2; 3043 reduced_clock.m2;
2930 } 3044 }
2931 3045
2932 if (!IS_IGDNG(dev)) 3046 if (!IS_IRONLAKE(dev))
2933 dpll = DPLL_VGA_MODE_DIS; 3047 dpll = DPLL_VGA_MODE_DIS;
2934 3048
2935 if (IS_I9XX(dev)) { 3049 if (IS_I9XX(dev)) {
@@ -2942,19 +3056,19 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2942 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 3056 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2943 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 3057 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2944 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 3058 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2945 else if (IS_IGDNG(dev)) 3059 else if (IS_IRONLAKE(dev))
2946 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 3060 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2947 } 3061 }
2948 if (is_dp) 3062 if (is_dp)
2949 dpll |= DPLL_DVO_HIGH_SPEED; 3063 dpll |= DPLL_DVO_HIGH_SPEED;
2950 3064
2951 /* compute bitmask from p1 value */ 3065 /* compute bitmask from p1 value */
2952 if (IS_IGD(dev)) 3066 if (IS_PINEVIEW(dev))
2953 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD; 3067 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2954 else { 3068 else {
2955 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3069 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2956 /* also FPA1 */ 3070 /* also FPA1 */
2957 if (IS_IGDNG(dev)) 3071 if (IS_IRONLAKE(dev))
2958 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 3072 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2959 if (IS_G4X(dev) && has_reduced_clock) 3073 if (IS_G4X(dev) && has_reduced_clock)
2960 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 3074 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
@@ -2973,7 +3087,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2973 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 3087 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2974 break; 3088 break;
2975 } 3089 }
2976 if (IS_I965G(dev) && !IS_IGDNG(dev)) 3090 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
2977 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 3091 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2978 } else { 3092 } else {
2979 if (is_lvds) { 3093 if (is_lvds) {
@@ -3005,9 +3119,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3005 /* Set up the display plane register */ 3119 /* Set up the display plane register */
3006 dspcntr = DISPPLANE_GAMMA_ENABLE; 3120 dspcntr = DISPPLANE_GAMMA_ENABLE;
3007 3121
3008 /* IGDNG's plane is forced to pipe, bit 24 is to 3122 /* Ironlake's plane is forced to pipe, bit 24 is to
3009 enable color space conversion */ 3123 enable color space conversion */
3010 if (!IS_IGDNG(dev)) { 3124 if (!IS_IRONLAKE(dev)) {
3011 if (pipe == 0) 3125 if (pipe == 0)
3012 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; 3126 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3013 else 3127 else
@@ -3034,20 +3148,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3034 3148
3035 3149
3036 /* Disable the panel fitter if it was on our pipe */ 3150 /* Disable the panel fitter if it was on our pipe */
3037 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe) 3151 if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
3038 I915_WRITE(PFIT_CONTROL, 0); 3152 I915_WRITE(PFIT_CONTROL, 0);
3039 3153
3040 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 3154 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3041 drm_mode_debug_printmodeline(mode); 3155 drm_mode_debug_printmodeline(mode);
3042 3156
3043 /* assign to IGDNG registers */ 3157 /* assign to Ironlake registers */
3044 if (IS_IGDNG(dev)) { 3158 if (IS_IRONLAKE(dev)) {
3045 fp_reg = pch_fp_reg; 3159 fp_reg = pch_fp_reg;
3046 dpll_reg = pch_dpll_reg; 3160 dpll_reg = pch_dpll_reg;
3047 } 3161 }
3048 3162
3049 if (is_edp) { 3163 if (is_edp) {
3050 igdng_disable_pll_edp(crtc); 3164 ironlake_disable_pll_edp(crtc);
3051 } else if ((dpll & DPLL_VCO_ENABLE)) { 3165 } else if ((dpll & DPLL_VCO_ENABLE)) {
3052 I915_WRITE(fp_reg, fp); 3166 I915_WRITE(fp_reg, fp);
3053 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 3167 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
@@ -3062,7 +3176,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3062 if (is_lvds) { 3176 if (is_lvds) {
3063 u32 lvds; 3177 u32 lvds;
3064 3178
3065 if (IS_IGDNG(dev)) 3179 if (IS_IRONLAKE(dev))
3066 lvds_reg = PCH_LVDS; 3180 lvds_reg = PCH_LVDS;
3067 3181
3068 lvds = I915_READ(lvds_reg); 3182 lvds = I915_READ(lvds_reg);
@@ -3095,7 +3209,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3095 /* Wait for the clocks to stabilize. */ 3209 /* Wait for the clocks to stabilize. */
3096 udelay(150); 3210 udelay(150);
3097 3211
3098 if (IS_I965G(dev) && !IS_IGDNG(dev)) { 3212 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
3099 if (is_sdvo) { 3213 if (is_sdvo) {
3100 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 3214 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3101 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | 3215 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
@@ -3115,14 +3229,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3115 I915_WRITE(fp_reg + 4, fp2); 3229 I915_WRITE(fp_reg + 4, fp2);
3116 intel_crtc->lowfreq_avail = true; 3230 intel_crtc->lowfreq_avail = true;
3117 if (HAS_PIPE_CXSR(dev)) { 3231 if (HAS_PIPE_CXSR(dev)) {
3118 DRM_DEBUG("enabling CxSR downclocking\n"); 3232 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3119 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 3233 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3120 } 3234 }
3121 } else { 3235 } else {
3122 I915_WRITE(fp_reg + 4, fp); 3236 I915_WRITE(fp_reg + 4, fp);
3123 intel_crtc->lowfreq_avail = false; 3237 intel_crtc->lowfreq_avail = false;
3124 if (HAS_PIPE_CXSR(dev)) { 3238 if (HAS_PIPE_CXSR(dev)) {
3125 DRM_DEBUG("disabling CxSR downclocking\n"); 3239 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3126 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 3240 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3127 } 3241 }
3128 } 3242 }
@@ -3142,21 +3256,21 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3142 /* pipesrc and dspsize control the size that is scaled from, which should 3256 /* pipesrc and dspsize control the size that is scaled from, which should
3143 * always be the user's requested size. 3257 * always be the user's requested size.
3144 */ 3258 */
3145 if (!IS_IGDNG(dev)) { 3259 if (!IS_IRONLAKE(dev)) {
3146 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | 3260 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3147 (mode->hdisplay - 1)); 3261 (mode->hdisplay - 1));
3148 I915_WRITE(dsppos_reg, 0); 3262 I915_WRITE(dsppos_reg, 0);
3149 } 3263 }
3150 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 3264 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3151 3265
3152 if (IS_IGDNG(dev)) { 3266 if (IS_IRONLAKE(dev)) {
3153 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m); 3267 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3154 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n); 3268 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3155 I915_WRITE(link_m1_reg, m_n.link_m); 3269 I915_WRITE(link_m1_reg, m_n.link_m);
3156 I915_WRITE(link_n1_reg, m_n.link_n); 3270 I915_WRITE(link_n1_reg, m_n.link_n);
3157 3271
3158 if (is_edp) { 3272 if (is_edp) {
3159 igdng_set_pll_edp(crtc, adjusted_mode->clock); 3273 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3160 } else { 3274 } else {
3161 /* enable FDI RX PLL too */ 3275 /* enable FDI RX PLL too */
3162 temp = I915_READ(fdi_rx_reg); 3276 temp = I915_READ(fdi_rx_reg);
@@ -3170,7 +3284,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3170 3284
3171 intel_wait_for_vblank(dev); 3285 intel_wait_for_vblank(dev);
3172 3286
3173 if (IS_IGDNG(dev)) { 3287 if (IS_IRONLAKE(dev)) {
3174 /* enable address swizzle for tiling buffer */ 3288 /* enable address swizzle for tiling buffer */
3175 temp = I915_READ(DISP_ARB_CTL); 3289 temp = I915_READ(DISP_ARB_CTL);
3176 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); 3290 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
@@ -3204,8 +3318,8 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
3204 if (!crtc->enabled) 3318 if (!crtc->enabled)
3205 return; 3319 return;
3206 3320
3207 /* use legacy palette for IGDNG */ 3321 /* use legacy palette for Ironlake */
3208 if (IS_IGDNG(dev)) 3322 if (IS_IRONLAKE(dev))
3209 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : 3323 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3210 LGC_PALETTE_B; 3324 LGC_PALETTE_B;
3211 3325
@@ -3234,11 +3348,11 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3234 size_t addr; 3348 size_t addr;
3235 int ret; 3349 int ret;
3236 3350
3237 DRM_DEBUG("\n"); 3351 DRM_DEBUG_KMS("\n");
3238 3352
3239 /* if we want to turn off the cursor ignore width and height */ 3353 /* if we want to turn off the cursor ignore width and height */
3240 if (!handle) { 3354 if (!handle) {
3241 DRM_DEBUG("cursor off\n"); 3355 DRM_DEBUG_KMS("cursor off\n");
3242 if (IS_MOBILE(dev) || IS_I9XX(dev)) { 3356 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3243 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 3357 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3244 temp |= CURSOR_MODE_DISABLE; 3358 temp |= CURSOR_MODE_DISABLE;
@@ -3546,18 +3660,18 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3546 fp = I915_READ((pipe == 0) ? FPA1 : FPB1); 3660 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3547 3661
3548 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 3662 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3549 if (IS_IGD(dev)) { 3663 if (IS_PINEVIEW(dev)) {
3550 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 3664 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3551 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT; 3665 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3552 } else { 3666 } else {
3553 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 3667 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3554 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 3668 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3555 } 3669 }
3556 3670
3557 if (IS_I9XX(dev)) { 3671 if (IS_I9XX(dev)) {
3558 if (IS_IGD(dev)) 3672 if (IS_PINEVIEW(dev))
3559 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> 3673 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3560 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); 3674 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3561 else 3675 else
3562 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 3676 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3563 DPLL_FPA01_P1_POST_DIV_SHIFT); 3677 DPLL_FPA01_P1_POST_DIV_SHIFT);
@@ -3572,7 +3686,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3572 7 : 14; 3686 7 : 14;
3573 break; 3687 break;
3574 default: 3688 default:
3575 DRM_DEBUG("Unknown DPLL mode %08x in programmed " 3689 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3576 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 3690 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3577 return 0; 3691 return 0;
3578 } 3692 }
@@ -3658,7 +3772,7 @@ static void intel_gpu_idle_timer(unsigned long arg)
3658 struct drm_device *dev = (struct drm_device *)arg; 3772 struct drm_device *dev = (struct drm_device *)arg;
3659 drm_i915_private_t *dev_priv = dev->dev_private; 3773 drm_i915_private_t *dev_priv = dev->dev_private;
3660 3774
3661 DRM_DEBUG("idle timer fired, downclocking\n"); 3775 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3662 3776
3663 dev_priv->busy = false; 3777 dev_priv->busy = false;
3664 3778
@@ -3669,11 +3783,11 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3669{ 3783{
3670 drm_i915_private_t *dev_priv = dev->dev_private; 3784 drm_i915_private_t *dev_priv = dev->dev_private;
3671 3785
3672 if (IS_IGDNG(dev)) 3786 if (IS_IRONLAKE(dev))
3673 return; 3787 return;
3674 3788
3675 if (!dev_priv->render_reclock_avail) { 3789 if (!dev_priv->render_reclock_avail) {
3676 DRM_DEBUG("not reclocking render clock\n"); 3790 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3677 return; 3791 return;
3678 } 3792 }
3679 3793
@@ -3682,7 +3796,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3682 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock); 3796 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3683 else if (IS_I85X(dev)) 3797 else if (IS_I85X(dev))
3684 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock); 3798 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3685 DRM_DEBUG("increasing render clock frequency\n"); 3799 DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3686 3800
3687 /* Schedule downclock */ 3801 /* Schedule downclock */
3688 if (schedule) 3802 if (schedule)
@@ -3694,11 +3808,11 @@ void intel_decrease_renderclock(struct drm_device *dev)
3694{ 3808{
3695 drm_i915_private_t *dev_priv = dev->dev_private; 3809 drm_i915_private_t *dev_priv = dev->dev_private;
3696 3810
3697 if (IS_IGDNG(dev)) 3811 if (IS_IRONLAKE(dev))
3698 return; 3812 return;
3699 3813
3700 if (!dev_priv->render_reclock_avail) { 3814 if (!dev_priv->render_reclock_avail) {
3701 DRM_DEBUG("not reclocking render clock\n"); 3815 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3702 return; 3816 return;
3703 } 3817 }
3704 3818
@@ -3758,7 +3872,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
3758 3872
3759 pci_write_config_word(dev->pdev, HPLLCC, hpllcc); 3873 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3760 } 3874 }
3761 DRM_DEBUG("decreasing render clock frequency\n"); 3875 DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3762} 3876}
3763 3877
3764/* Note that no increase function is needed for this - increase_renderclock() 3878/* Note that no increase function is needed for this - increase_renderclock()
@@ -3766,7 +3880,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
3766 */ 3880 */
3767void intel_decrease_displayclock(struct drm_device *dev) 3881void intel_decrease_displayclock(struct drm_device *dev)
3768{ 3882{
3769 if (IS_IGDNG(dev)) 3883 if (IS_IRONLAKE(dev))
3770 return; 3884 return;
3771 3885
3772 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) || 3886 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
@@ -3792,7 +3906,7 @@ static void intel_crtc_idle_timer(unsigned long arg)
3792 struct drm_crtc *crtc = &intel_crtc->base; 3906 struct drm_crtc *crtc = &intel_crtc->base;
3793 drm_i915_private_t *dev_priv = crtc->dev->dev_private; 3907 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3794 3908
3795 DRM_DEBUG("idle timer fired, downclocking\n"); 3909 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3796 3910
3797 intel_crtc->busy = false; 3911 intel_crtc->busy = false;
3798 3912
@@ -3808,14 +3922,14 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3808 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 3922 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3809 int dpll = I915_READ(dpll_reg); 3923 int dpll = I915_READ(dpll_reg);
3810 3924
3811 if (IS_IGDNG(dev)) 3925 if (IS_IRONLAKE(dev))
3812 return; 3926 return;
3813 3927
3814 if (!dev_priv->lvds_downclock_avail) 3928 if (!dev_priv->lvds_downclock_avail)
3815 return; 3929 return;
3816 3930
3817 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { 3931 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3818 DRM_DEBUG("upclocking LVDS\n"); 3932 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3819 3933
3820 /* Unlock panel regs */ 3934 /* Unlock panel regs */
3821 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); 3935 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
@@ -3826,7 +3940,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3826 intel_wait_for_vblank(dev); 3940 intel_wait_for_vblank(dev);
3827 dpll = I915_READ(dpll_reg); 3941 dpll = I915_READ(dpll_reg);
3828 if (dpll & DISPLAY_RATE_SELECT_FPA1) 3942 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3829 DRM_DEBUG("failed to upclock LVDS!\n"); 3943 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3830 3944
3831 /* ...and lock them again */ 3945 /* ...and lock them again */
3832 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); 3946 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
@@ -3847,7 +3961,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3847 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 3961 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3848 int dpll = I915_READ(dpll_reg); 3962 int dpll = I915_READ(dpll_reg);
3849 3963
3850 if (IS_IGDNG(dev)) 3964 if (IS_IRONLAKE(dev))
3851 return; 3965 return;
3852 3966
3853 if (!dev_priv->lvds_downclock_avail) 3967 if (!dev_priv->lvds_downclock_avail)
@@ -3858,7 +3972,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3858 * the manual case. 3972 * the manual case.
3859 */ 3973 */
3860 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 3974 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3861 DRM_DEBUG("downclocking LVDS\n"); 3975 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3862 3976
3863 /* Unlock panel regs */ 3977 /* Unlock panel regs */
3864 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); 3978 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
@@ -3869,7 +3983,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3869 intel_wait_for_vblank(dev); 3983 intel_wait_for_vblank(dev);
3870 dpll = I915_READ(dpll_reg); 3984 dpll = I915_READ(dpll_reg);
3871 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 3985 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3872 DRM_DEBUG("failed to downclock LVDS!\n"); 3986 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3873 3987
3874 /* ...and lock them again */ 3988 /* ...and lock them again */
3875 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); 3989 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
@@ -3936,8 +4050,13 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3936 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 4050 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3937 return; 4051 return;
3938 4052
3939 dev_priv->busy = true; 4053 if (!dev_priv->busy) {
3940 intel_increase_renderclock(dev, true); 4054 dev_priv->busy = true;
4055 intel_increase_renderclock(dev, true);
4056 } else {
4057 mod_timer(&dev_priv->idle_timer, jiffies +
4058 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4059 }
3941 4060
3942 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 4061 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3943 if (!crtc->fb) 4062 if (!crtc->fb)
@@ -3967,6 +4086,158 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
3967 kfree(intel_crtc); 4086 kfree(intel_crtc);
3968} 4087}
3969 4088
4089struct intel_unpin_work {
4090 struct work_struct work;
4091 struct drm_device *dev;
4092 struct drm_gem_object *obj;
4093 struct drm_pending_vblank_event *event;
4094 int pending;
4095};
4096
4097static void intel_unpin_work_fn(struct work_struct *__work)
4098{
4099 struct intel_unpin_work *work =
4100 container_of(__work, struct intel_unpin_work, work);
4101
4102 mutex_lock(&work->dev->struct_mutex);
4103 i915_gem_object_unpin(work->obj);
4104 drm_gem_object_unreference(work->obj);
4105 mutex_unlock(&work->dev->struct_mutex);
4106 kfree(work);
4107}
4108
4109void intel_finish_page_flip(struct drm_device *dev, int pipe)
4110{
4111 drm_i915_private_t *dev_priv = dev->dev_private;
4112 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4114 struct intel_unpin_work *work;
4115 struct drm_i915_gem_object *obj_priv;
4116 struct drm_pending_vblank_event *e;
4117 struct timeval now;
4118 unsigned long flags;
4119
4120 /* Ignore early vblank irqs */
4121 if (intel_crtc == NULL)
4122 return;
4123
4124 spin_lock_irqsave(&dev->event_lock, flags);
4125 work = intel_crtc->unpin_work;
4126 if (work == NULL || !work->pending) {
4127 spin_unlock_irqrestore(&dev->event_lock, flags);
4128 return;
4129 }
4130
4131 intel_crtc->unpin_work = NULL;
4132 drm_vblank_put(dev, intel_crtc->pipe);
4133
4134 if (work->event) {
4135 e = work->event;
4136 do_gettimeofday(&now);
4137 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4138 e->event.tv_sec = now.tv_sec;
4139 e->event.tv_usec = now.tv_usec;
4140 list_add_tail(&e->base.link,
4141 &e->base.file_priv->event_list);
4142 wake_up_interruptible(&e->base.file_priv->event_wait);
4143 }
4144
4145 spin_unlock_irqrestore(&dev->event_lock, flags);
4146
4147 obj_priv = work->obj->driver_private;
4148 if (atomic_dec_and_test(&obj_priv->pending_flip))
4149 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4150 schedule_work(&work->work);
4151}
4152
4153void intel_prepare_page_flip(struct drm_device *dev, int plane)
4154{
4155 drm_i915_private_t *dev_priv = dev->dev_private;
4156 struct intel_crtc *intel_crtc =
4157 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4158 unsigned long flags;
4159
4160 spin_lock_irqsave(&dev->event_lock, flags);
4161 if (intel_crtc->unpin_work)
4162 intel_crtc->unpin_work->pending = 1;
4163 spin_unlock_irqrestore(&dev->event_lock, flags);
4164}
4165
4166static int intel_crtc_page_flip(struct drm_crtc *crtc,
4167 struct drm_framebuffer *fb,
4168 struct drm_pending_vblank_event *event)
4169{
4170 struct drm_device *dev = crtc->dev;
4171 struct drm_i915_private *dev_priv = dev->dev_private;
4172 struct intel_framebuffer *intel_fb;
4173 struct drm_i915_gem_object *obj_priv;
4174 struct drm_gem_object *obj;
4175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176 struct intel_unpin_work *work;
4177 unsigned long flags;
4178 int ret;
4179 RING_LOCALS;
4180
4181 work = kzalloc(sizeof *work, GFP_KERNEL);
4182 if (work == NULL)
4183 return -ENOMEM;
4184
4185 mutex_lock(&dev->struct_mutex);
4186
4187 work->event = event;
4188 work->dev = crtc->dev;
4189 intel_fb = to_intel_framebuffer(crtc->fb);
4190 work->obj = intel_fb->obj;
4191 INIT_WORK(&work->work, intel_unpin_work_fn);
4192
4193 /* We borrow the event spin lock for protecting unpin_work */
4194 spin_lock_irqsave(&dev->event_lock, flags);
4195 if (intel_crtc->unpin_work) {
4196 spin_unlock_irqrestore(&dev->event_lock, flags);
4197 kfree(work);
4198 mutex_unlock(&dev->struct_mutex);
4199 return -EBUSY;
4200 }
4201 intel_crtc->unpin_work = work;
4202 spin_unlock_irqrestore(&dev->event_lock, flags);
4203
4204 intel_fb = to_intel_framebuffer(fb);
4205 obj = intel_fb->obj;
4206
4207 ret = intel_pin_and_fence_fb_obj(dev, obj);
4208 if (ret != 0) {
4209 kfree(work);
4210 mutex_unlock(&dev->struct_mutex);
4211 return ret;
4212 }
4213
4214 /* Reference the old fb object for the scheduled work. */
4215 drm_gem_object_reference(work->obj);
4216
4217 crtc->fb = fb;
4218 i915_gem_object_flush_write_domain(obj);
4219 drm_vblank_get(dev, intel_crtc->pipe);
4220 obj_priv = obj->driver_private;
4221 atomic_inc(&obj_priv->pending_flip);
4222
4223 BEGIN_LP_RING(4);
4224 OUT_RING(MI_DISPLAY_FLIP |
4225 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4226 OUT_RING(fb->pitch);
4227 if (IS_I965G(dev)) {
4228 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4229 OUT_RING((fb->width << 16) | fb->height);
4230 } else {
4231 OUT_RING(obj_priv->gtt_offset);
4232 OUT_RING(MI_NOOP);
4233 }
4234 ADVANCE_LP_RING();
4235
4236 mutex_unlock(&dev->struct_mutex);
4237
4238 return 0;
4239}
4240
3970static const struct drm_crtc_helper_funcs intel_helper_funcs = { 4241static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3971 .dpms = intel_crtc_dpms, 4242 .dpms = intel_crtc_dpms,
3972 .mode_fixup = intel_crtc_mode_fixup, 4243 .mode_fixup = intel_crtc_mode_fixup,
@@ -3983,11 +4254,13 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
3983 .gamma_set = intel_crtc_gamma_set, 4254 .gamma_set = intel_crtc_gamma_set,
3984 .set_config = drm_crtc_helper_set_config, 4255 .set_config = drm_crtc_helper_set_config,
3985 .destroy = intel_crtc_destroy, 4256 .destroy = intel_crtc_destroy,
4257 .page_flip = intel_crtc_page_flip,
3986}; 4258};
3987 4259
3988 4260
3989static void intel_crtc_init(struct drm_device *dev, int pipe) 4261static void intel_crtc_init(struct drm_device *dev, int pipe)
3990{ 4262{
4263 drm_i915_private_t *dev_priv = dev->dev_private;
3991 struct intel_crtc *intel_crtc; 4264 struct intel_crtc *intel_crtc;
3992 int i; 4265 int i;
3993 4266
@@ -4010,10 +4283,15 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
4010 intel_crtc->pipe = pipe; 4283 intel_crtc->pipe = pipe;
4011 intel_crtc->plane = pipe; 4284 intel_crtc->plane = pipe;
4012 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) { 4285 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4013 DRM_DEBUG("swapping pipes & planes for FBC\n"); 4286 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4014 intel_crtc->plane = ((pipe == 0) ? 1 : 0); 4287 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4015 } 4288 }
4016 4289
4290 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4291 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4292 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4293 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4294
4017 intel_crtc->cursor_addr = 0; 4295 intel_crtc->cursor_addr = 0;
4018 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; 4296 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4019 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 4297 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
@@ -4090,7 +4368,7 @@ static void intel_setup_outputs(struct drm_device *dev)
4090 if (IS_MOBILE(dev) && !IS_I830(dev)) 4368 if (IS_MOBILE(dev) && !IS_I830(dev))
4091 intel_lvds_init(dev); 4369 intel_lvds_init(dev);
4092 4370
4093 if (IS_IGDNG(dev)) { 4371 if (IS_IRONLAKE(dev)) {
4094 int found; 4372 int found;
4095 4373
4096 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) 4374 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
@@ -4118,7 +4396,7 @@ static void intel_setup_outputs(struct drm_device *dev)
4118 if (I915_READ(PCH_DP_D) & DP_DETECTED) 4396 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4119 intel_dp_init(dev, PCH_DP_D); 4397 intel_dp_init(dev, PCH_DP_D);
4120 4398
4121 } else if (IS_I9XX(dev)) { 4399 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4122 bool found = false; 4400 bool found = false;
4123 4401
4124 if (I915_READ(SDVOB) & SDVO_DETECTED) { 4402 if (I915_READ(SDVOB) & SDVO_DETECTED) {
@@ -4145,10 +4423,10 @@ static void intel_setup_outputs(struct drm_device *dev)
4145 4423
4146 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED)) 4424 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4147 intel_dp_init(dev, DP_D); 4425 intel_dp_init(dev, DP_D);
4148 } else 4426 } else if (IS_I8XX(dev))
4149 intel_dvo_init(dev); 4427 intel_dvo_init(dev);
4150 4428
4151 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev)) 4429 if (SUPPORTS_TV(dev))
4152 intel_tv_init(dev); 4430 intel_tv_init(dev);
4153 4431
4154 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 4432 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
@@ -4257,7 +4535,7 @@ void intel_init_clock_gating(struct drm_device *dev)
4257 * Disable clock gating reported to work incorrectly according to the 4535 * Disable clock gating reported to work incorrectly according to the
4258 * specs, but enable as much else as we can. 4536 * specs, but enable as much else as we can.
4259 */ 4537 */
4260 if (IS_IGDNG(dev)) { 4538 if (IS_IRONLAKE(dev)) {
4261 return; 4539 return;
4262 } else if (IS_G4X(dev)) { 4540 } else if (IS_G4X(dev)) {
4263 uint32_t dspclk_gate; 4541 uint32_t dspclk_gate;
@@ -4291,11 +4569,47 @@ void intel_init_clock_gating(struct drm_device *dev)
4291 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 4569 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4292 DSTATE_DOT_CLOCK_GATING; 4570 DSTATE_DOT_CLOCK_GATING;
4293 I915_WRITE(D_STATE, dstate); 4571 I915_WRITE(D_STATE, dstate);
4294 } else if (IS_I855(dev) || IS_I865G(dev)) { 4572 } else if (IS_I85X(dev) || IS_I865G(dev)) {
4295 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 4573 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4296 } else if (IS_I830(dev)) { 4574 } else if (IS_I830(dev)) {
4297 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 4575 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4298 } 4576 }
4577
4578 /*
4579 * GPU can automatically power down the render unit if given a page
4580 * to save state.
4581 */
4582 if (I915_HAS_RC6(dev)) {
4583 struct drm_gem_object *pwrctx;
4584 struct drm_i915_gem_object *obj_priv;
4585 int ret;
4586
4587 pwrctx = drm_gem_object_alloc(dev, 4096);
4588 if (!pwrctx) {
4589 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4590 goto out;
4591 }
4592
4593 ret = i915_gem_object_pin(pwrctx, 4096);
4594 if (ret) {
4595 DRM_ERROR("failed to pin power context: %d\n", ret);
4596 drm_gem_object_unreference(pwrctx);
4597 goto out;
4598 }
4599
4600 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4601
4602 obj_priv = pwrctx->driver_private;
4603
4604 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4605 I915_WRITE(MCHBAR_RENDER_STANDBY,
4606 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4607
4608 dev_priv->pwrctx = pwrctx;
4609 }
4610
4611out:
4612 return;
4299} 4613}
4300 4614
4301/* Set up chip specific display functions */ 4615/* Set up chip specific display functions */
@@ -4304,8 +4618,8 @@ static void intel_init_display(struct drm_device *dev)
4304 struct drm_i915_private *dev_priv = dev->dev_private; 4618 struct drm_i915_private *dev_priv = dev->dev_private;
4305 4619
4306 /* We always want a DPMS function */ 4620 /* We always want a DPMS function */
4307 if (IS_IGDNG(dev)) 4621 if (IS_IRONLAKE(dev))
4308 dev_priv->display.dpms = igdng_crtc_dpms; 4622 dev_priv->display.dpms = ironlake_crtc_dpms;
4309 else 4623 else
4310 dev_priv->display.dpms = i9xx_crtc_dpms; 4624 dev_priv->display.dpms = i9xx_crtc_dpms;
4311 4625
@@ -4324,13 +4638,13 @@ static void intel_init_display(struct drm_device *dev)
4324 } 4638 }
4325 4639
4326 /* Returns the core display clock speed */ 4640 /* Returns the core display clock speed */
4327 if (IS_I945G(dev)) 4641 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4328 dev_priv->display.get_display_clock_speed = 4642 dev_priv->display.get_display_clock_speed =
4329 i945_get_display_clock_speed; 4643 i945_get_display_clock_speed;
4330 else if (IS_I915G(dev)) 4644 else if (IS_I915G(dev))
4331 dev_priv->display.get_display_clock_speed = 4645 dev_priv->display.get_display_clock_speed =
4332 i915_get_display_clock_speed; 4646 i915_get_display_clock_speed;
4333 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev)) 4647 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4334 dev_priv->display.get_display_clock_speed = 4648 dev_priv->display.get_display_clock_speed =
4335 i9xx_misc_get_display_clock_speed; 4649 i9xx_misc_get_display_clock_speed;
4336 else if (IS_I915GM(dev)) 4650 else if (IS_I915GM(dev))
@@ -4339,7 +4653,7 @@ static void intel_init_display(struct drm_device *dev)
4339 else if (IS_I865G(dev)) 4653 else if (IS_I865G(dev))
4340 dev_priv->display.get_display_clock_speed = 4654 dev_priv->display.get_display_clock_speed =
4341 i865_get_display_clock_speed; 4655 i865_get_display_clock_speed;
4342 else if (IS_I855(dev)) 4656 else if (IS_I85X(dev))
4343 dev_priv->display.get_display_clock_speed = 4657 dev_priv->display.get_display_clock_speed =
4344 i855_get_display_clock_speed; 4658 i855_get_display_clock_speed;
4345 else /* 852, 830 */ 4659 else /* 852, 830 */
@@ -4347,7 +4661,7 @@ static void intel_init_display(struct drm_device *dev)
4347 i830_get_display_clock_speed; 4661 i830_get_display_clock_speed;
4348 4662
4349 /* For FIFO watermark updates */ 4663 /* For FIFO watermark updates */
4350 if (IS_IGDNG(dev)) 4664 if (IS_IRONLAKE(dev))
4351 dev_priv->display.update_wm = NULL; 4665 dev_priv->display.update_wm = NULL;
4352 else if (IS_G4X(dev)) 4666 else if (IS_G4X(dev))
4353 dev_priv->display.update_wm = g4x_update_wm; 4667 dev_priv->display.update_wm = g4x_update_wm;
@@ -4403,7 +4717,7 @@ void intel_modeset_init(struct drm_device *dev)
4403 num_pipe = 2; 4717 num_pipe = 2;
4404 else 4718 else
4405 num_pipe = 1; 4719 num_pipe = 1;
4406 DRM_DEBUG("%d display pipe%s available.\n", 4720 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4407 num_pipe, num_pipe > 1 ? "s" : ""); 4721 num_pipe, num_pipe > 1 ? "s" : "");
4408 4722
4409 if (IS_I85X(dev)) 4723 if (IS_I85X(dev))
@@ -4422,6 +4736,15 @@ void intel_modeset_init(struct drm_device *dev)
4422 INIT_WORK(&dev_priv->idle_work, intel_idle_update); 4736 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4423 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, 4737 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4424 (unsigned long)dev); 4738 (unsigned long)dev);
4739
4740 intel_setup_overlay(dev);
4741
4742 if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4743 dev_priv->fsb_freq,
4744 dev_priv->mem_freq))
4745 DRM_INFO("failed to find known CxSR latency "
4746 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4747 dev_priv->fsb_freq, dev_priv->mem_freq);
4425} 4748}
4426 4749
4427void intel_modeset_cleanup(struct drm_device *dev) 4750void intel_modeset_cleanup(struct drm_device *dev)
@@ -4445,11 +4768,21 @@ void intel_modeset_cleanup(struct drm_device *dev)
4445 intel_increase_renderclock(dev, false); 4768 intel_increase_renderclock(dev, false);
4446 del_timer_sync(&dev_priv->idle_timer); 4769 del_timer_sync(&dev_priv->idle_timer);
4447 4770
4448 mutex_unlock(&dev->struct_mutex);
4449
4450 if (dev_priv->display.disable_fbc) 4771 if (dev_priv->display.disable_fbc)
4451 dev_priv->display.disable_fbc(dev); 4772 dev_priv->display.disable_fbc(dev);
4452 4773
4774 if (dev_priv->pwrctx) {
4775 struct drm_i915_gem_object *obj_priv;
4776
4777 obj_priv = dev_priv->pwrctx->driver_private;
4778 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4779 I915_READ(PWRCTXA);
4780 i915_gem_object_unpin(dev_priv->pwrctx);
4781 drm_gem_object_unreference(dev_priv->pwrctx);
4782 }
4783
4784 mutex_unlock(&dev->struct_mutex);
4785
4453 drm_mode_config_cleanup(dev); 4786 drm_mode_config_cleanup(dev);
4454} 4787}
4455 4788
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 17:42:16 -0500