aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_display.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1312
1 files changed, 855 insertions, 457 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d8324c69fa86..507370513f3d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -91,15 +91,16 @@ static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb, 91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd, 92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj); 93 struct drm_i915_gem_object *obj);
94static void intel_dp_set_m_n(struct intel_crtc *crtc);
95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); 95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n); 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99static void ironlake_set_pipeconf(struct drm_crtc *crtc); 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100static void haswell_set_pipeconf(struct drm_crtc *crtc); 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc); 101static void intel_set_pipe_csc(struct drm_crtc *crtc);
102static void vlv_prepare_pll(struct intel_crtc *crtc); 102static void vlv_prepare_pll(struct intel_crtc *crtc);
103static void chv_prepare_pll(struct intel_crtc *crtc);
103 104
104static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) 105static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
105{ 106{
@@ -899,7 +900,8 @@ static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
899 frame = I915_READ(frame_reg); 900 frame = I915_READ(frame_reg);
900 901
901 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) 902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
902 WARN(1, "vblank wait timed out\n"); 903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
903} 905}
904 906
905/** 907/**
@@ -940,7 +942,8 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
940 if (wait_for(I915_READ(pipestat_reg) & 942 if (wait_for(I915_READ(pipestat_reg) &
941 PIPE_VBLANK_INTERRUPT_STATUS, 943 PIPE_VBLANK_INTERRUPT_STATUS,
942 50)) 944 50))
943 DRM_DEBUG_KMS("vblank wait timed out\n"); 945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
944} 947}
945 948
946static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) 949static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
@@ -964,8 +967,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
964 967
965/* 968/*
966 * intel_wait_for_pipe_off - wait for pipe to turn off 969 * intel_wait_for_pipe_off - wait for pipe to turn off
967 * @dev: drm device 970 * @crtc: crtc whose pipe to wait for
968 * @pipe: pipe to wait for
969 * 971 *
970 * After disabling a pipe, we can't wait for vblank in the usual way, 972 * After disabling a pipe, we can't wait for vblank in the usual way,
971 * spinning on the vblank interrupt status bit, since we won't actually 973 * spinning on the vblank interrupt status bit, since we won't actually
@@ -979,11 +981,12 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
979 * ends up stopping at the start of the next frame). 981 * ends up stopping at the start of the next frame).
980 * 982 *
981 */ 983 */
982void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) 984static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
983{ 985{
986 struct drm_device *dev = crtc->base.dev;
984 struct drm_i915_private *dev_priv = dev->dev_private; 987 struct drm_i915_private *dev_priv = dev->dev_private;
985 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 988 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
986 pipe); 989 enum pipe pipe = crtc->pipe;
987 990
988 if (INTEL_INFO(dev)->gen >= 4) { 991 if (INTEL_INFO(dev)->gen >= 4) {
989 int reg = PIPECONF(cpu_transcoder); 992 int reg = PIPECONF(cpu_transcoder);
@@ -1192,27 +1195,40 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1192static void assert_panel_unlocked(struct drm_i915_private *dev_priv, 1195static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 enum pipe pipe) 1196 enum pipe pipe)
1194{ 1197{
1195 int pp_reg, lvds_reg; 1198 struct drm_device *dev = dev_priv->dev;
1199 int pp_reg;
1196 u32 val; 1200 u32 val;
1197 enum pipe panel_pipe = PIPE_A; 1201 enum pipe panel_pipe = PIPE_A;
1198 bool locked = true; 1202 bool locked = true;
1199 1203
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) { 1204 if (WARN_ON(HAS_DDI(dev)))
1205 return;
1206
1207 if (HAS_PCH_SPLIT(dev)) {
1208 u32 port_sel;
1209
1201 pp_reg = PCH_PP_CONTROL; 1210 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS; 1211 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220 panel_pipe = pipe;
1203 } else { 1221 } else {
1204 pp_reg = PP_CONTROL; 1222 pp_reg = PP_CONTROL;
1205 lvds_reg = LVDS; 1223 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
1206 } 1225 }
1207 1226
1208 val = I915_READ(pp_reg); 1227 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) || 1228 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) 1229 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1211 locked = false; 1230 locked = false;
1212 1231
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1215
1216 WARN(panel_pipe == pipe && locked, 1232 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n", 1233 "panel assertion failure, pipe %c regs locked\n",
1218 pipe_name(pipe)); 1234 pipe_name(pipe));
@@ -1245,8 +1261,9 @@ void assert_pipe(struct drm_i915_private *dev_priv,
1245 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1261 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1246 pipe); 1262 pipe);
1247 1263
1248 /* if we need the pipe A quirk it must be always on */ 1264 /* if we need the pipe quirk it must be always on */
1249 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 1265 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1266 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1250 state = true; 1267 state = true;
1251 1268
1252 if (!intel_display_power_enabled(dev_priv, 1269 if (!intel_display_power_enabled(dev_priv,
@@ -1300,7 +1317,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1300 } 1317 }
1301 1318
1302 /* Need to check both planes against the pipe */ 1319 /* Need to check both planes against the pipe */
1303 for_each_pipe(i) { 1320 for_each_pipe(dev_priv, i) {
1304 reg = DSPCNTR(i); 1321 reg = DSPCNTR(i);
1305 val = I915_READ(reg); 1322 val = I915_READ(reg);
1306 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1323 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
@@ -1341,6 +1358,12 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1341 } 1358 }
1342} 1359}
1343 1360
1361static void assert_vblank_disabled(struct drm_crtc *crtc)
1362{
1363 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1364 drm_crtc_vblank_put(crtc);
1365}
1366
1344static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 1367static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1345{ 1368{
1346 u32 val; 1369 u32 val;
@@ -1513,34 +1536,6 @@ static void intel_init_dpio(struct drm_device *dev)
1513 } 1536 }
1514} 1537}
1515 1538
1516static void intel_reset_dpio(struct drm_device *dev)
1517{
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520 if (IS_CHERRYVIEW(dev)) {
1521 enum dpio_phy phy;
1522 u32 val;
1523
1524 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1525 /* Poll for phypwrgood signal */
1526 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1527 PHY_POWERGOOD(phy), 1))
1528 DRM_ERROR("Display PHY %d is not power up\n", phy);
1529
1530 /*
1531 * Deassert common lane reset for PHY.
1532 *
1533 * This should only be done on init and resume from S3
1534 * with both PLLs disabled, or we risk losing DPIO and
1535 * PLL synchronization.
1536 */
1537 val = I915_READ(DISPLAY_PHY_CONTROL);
1538 I915_WRITE(DISPLAY_PHY_CONTROL,
1539 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1540 }
1541 }
1542}
1543
1544static void vlv_enable_pll(struct intel_crtc *crtc) 1539static void vlv_enable_pll(struct intel_crtc *crtc)
1545{ 1540{
1546 struct drm_device *dev = crtc->base.dev; 1541 struct drm_device *dev = crtc->base.dev;
@@ -1554,7 +1549,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc)
1554 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); 1549 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1555 1550
1556 /* PLL is protected by panel, make sure we can write it */ 1551 /* PLL is protected by panel, make sure we can write it */
1557 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) 1552 if (IS_MOBILE(dev_priv->dev))
1558 assert_panel_unlocked(dev_priv, crtc->pipe); 1553 assert_panel_unlocked(dev_priv, crtc->pipe);
1559 1554
1560 I915_WRITE(reg, dpll); 1555 I915_WRITE(reg, dpll);
@@ -1617,6 +1612,18 @@ static void chv_enable_pll(struct intel_crtc *crtc)
1617 mutex_unlock(&dev_priv->dpio_lock); 1612 mutex_unlock(&dev_priv->dpio_lock);
1618} 1613}
1619 1614
1615static int intel_num_dvo_pipes(struct drm_device *dev)
1616{
1617 struct intel_crtc *crtc;
1618 int count = 0;
1619
1620 for_each_intel_crtc(dev, crtc)
1621 count += crtc->active &&
1622 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO);
1623
1624 return count;
1625}
1626
1620static void i9xx_enable_pll(struct intel_crtc *crtc) 1627static void i9xx_enable_pll(struct intel_crtc *crtc)
1621{ 1628{
1622 struct drm_device *dev = crtc->base.dev; 1629 struct drm_device *dev = crtc->base.dev;
@@ -1633,7 +1640,18 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
1633 if (IS_MOBILE(dev) && !IS_I830(dev)) 1640 if (IS_MOBILE(dev) && !IS_I830(dev))
1634 assert_panel_unlocked(dev_priv, crtc->pipe); 1641 assert_panel_unlocked(dev_priv, crtc->pipe);
1635 1642
1636 I915_WRITE(reg, dpll); 1643 /* Enable DVO 2x clock on both PLLs if necessary */
1644 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1645 /*
1646 * It appears to be important that we don't enable this
1647 * for the current pipe before otherwise configuring the
1648 * PLL. No idea how this should be handled if multiple
1649 * DVO outputs are enabled simultaneosly.
1650 */
1651 dpll |= DPLL_DVO_2X_MODE;
1652 I915_WRITE(DPLL(!crtc->pipe),
1653 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1654 }
1637 1655
1638 /* Wait for the clocks to stabilize. */ 1656 /* Wait for the clocks to stabilize. */
1639 POSTING_READ(reg); 1657 POSTING_READ(reg);
@@ -1672,10 +1690,25 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
1672 * 1690 *
1673 * Note! This is for pre-ILK only. 1691 * Note! This is for pre-ILK only.
1674 */ 1692 */
1675static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1693static void i9xx_disable_pll(struct intel_crtc *crtc)
1676{ 1694{
1677 /* Don't disable pipe A or pipe A PLLs if needed */ 1695 struct drm_device *dev = crtc->base.dev;
1678 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697 enum pipe pipe = crtc->pipe;
1698
1699 /* Disable DVO 2x clock on both PLLs if necessary */
1700 if (IS_I830(dev) &&
1701 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) &&
1702 intel_num_dvo_pipes(dev) == 1) {
1703 I915_WRITE(DPLL(PIPE_B),
1704 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1705 I915_WRITE(DPLL(PIPE_A),
1706 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1707 }
1708
1709 /* Don't disable pipe or pipe PLLs if needed */
1710 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1711 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1679 return; 1712 return;
1680 1713
1681 /* Make sure the pipe isn't still relying on us */ 1714 /* Make sure the pipe isn't still relying on us */
@@ -1712,7 +1745,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1712 assert_pipe_disabled(dev_priv, pipe); 1745 assert_pipe_disabled(dev_priv, pipe);
1713 1746
1714 /* Set PLL en = 0 */ 1747 /* Set PLL en = 0 */
1715 val = DPLL_SSC_REF_CLOCK_CHV; 1748 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1716 if (pipe != PIPE_A) 1749 if (pipe != PIPE_A)
1717 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1750 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1718 I915_WRITE(DPLL(pipe), val); 1751 I915_WRITE(DPLL(pipe), val);
@@ -1806,7 +1839,7 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1806 if (WARN_ON(pll->refcount == 0)) 1839 if (WARN_ON(pll->refcount == 0))
1807 return; 1840 return;
1808 1841
1809 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", 1842 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1810 pll->name, pll->active, pll->on, 1843 pll->name, pll->active, pll->on,
1811 crtc->base.base.id); 1844 crtc->base.base.id);
1812 1845
@@ -1824,7 +1857,7 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1824 pll->on = true; 1857 pll->on = true;
1825} 1858}
1826 1859
1827void intel_disable_shared_dpll(struct intel_crtc *crtc) 1860static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1828{ 1861{
1829 struct drm_device *dev = crtc->base.dev; 1862 struct drm_device *dev = crtc->base.dev;
1830 struct drm_i915_private *dev_priv = dev->dev_private; 1863 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1868,7 +1901,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1868 uint32_t reg, val, pipeconf_val; 1901 uint32_t reg, val, pipeconf_val;
1869 1902
1870 /* PCH only available on ILK+ */ 1903 /* PCH only available on ILK+ */
1871 BUG_ON(INTEL_INFO(dev)->gen < 5); 1904 BUG_ON(!HAS_PCH_SPLIT(dev));
1872 1905
1873 /* Make sure PCH DPLL is enabled */ 1906 /* Make sure PCH DPLL is enabled */
1874 assert_shared_dpll_enabled(dev_priv, 1907 assert_shared_dpll_enabled(dev_priv,
@@ -1921,7 +1954,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1921 u32 val, pipeconf_val; 1954 u32 val, pipeconf_val;
1922 1955
1923 /* PCH only available on ILK+ */ 1956 /* PCH only available on ILK+ */
1924 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); 1957 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1925 1958
1926 /* FDI must be feeding us bits for PCH ports */ 1959 /* FDI must be feeding us bits for PCH ports */
1927 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); 1960 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
@@ -2043,8 +2076,8 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
2043 reg = PIPECONF(cpu_transcoder); 2076 reg = PIPECONF(cpu_transcoder);
2044 val = I915_READ(reg); 2077 val = I915_READ(reg);
2045 if (val & PIPECONF_ENABLE) { 2078 if (val & PIPECONF_ENABLE) {
2046 WARN_ON(!(pipe == PIPE_A && 2079 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2047 dev_priv->quirks & QUIRK_PIPEA_FORCE)); 2080 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2048 return; 2081 return;
2049 } 2082 }
2050 2083
@@ -2054,21 +2087,19 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
2054 2087
2055/** 2088/**
2056 * intel_disable_pipe - disable a pipe, asserting requirements 2089 * intel_disable_pipe - disable a pipe, asserting requirements
2057 * @dev_priv: i915 private structure 2090 * @crtc: crtc whose pipes is to be disabled
2058 * @pipe: pipe to disable
2059 * 2091 *
2060 * Disable @pipe, making sure that various hardware specific requirements 2092 * Disable the pipe of @crtc, making sure that various hardware
2061 * are met, if applicable, e.g. plane disabled, panel fitter off, etc. 2093 * specific requirements are met, if applicable, e.g. plane
2062 * 2094 * disabled, panel fitter off, etc.
2063 * @pipe should be %PIPE_A or %PIPE_B.
2064 * 2095 *
2065 * Will wait until the pipe has shut down before returning. 2096 * Will wait until the pipe has shut down before returning.
2066 */ 2097 */
2067static void intel_disable_pipe(struct drm_i915_private *dev_priv, 2098static void intel_disable_pipe(struct intel_crtc *crtc)
2068 enum pipe pipe)
2069{ 2099{
2070 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 2100 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 pipe); 2101 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2102 enum pipe pipe = crtc->pipe;
2072 int reg; 2103 int reg;
2073 u32 val; 2104 u32 val;
2074 2105
@@ -2080,17 +2111,26 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2080 assert_cursor_disabled(dev_priv, pipe); 2111 assert_cursor_disabled(dev_priv, pipe);
2081 assert_sprites_disabled(dev_priv, pipe); 2112 assert_sprites_disabled(dev_priv, pipe);
2082 2113
2083 /* Don't disable pipe A or pipe A PLLs if needed */
2084 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2085 return;
2086
2087 reg = PIPECONF(cpu_transcoder); 2114 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg); 2115 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0) 2116 if ((val & PIPECONF_ENABLE) == 0)
2090 return; 2117 return;
2091 2118
2092 I915_WRITE(reg, val & ~PIPECONF_ENABLE); 2119 /*
2093 intel_wait_for_pipe_off(dev_priv->dev, pipe); 2120 * Double wide has implications for planes
2121 * so best keep it disabled when not needed.
2122 */
2123 if (crtc->config.double_wide)
2124 val &= ~PIPECONF_DOUBLE_WIDE;
2125
2126 /* Don't disable pipe or pipe PLLs if needed */
2127 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2128 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2129 val &= ~PIPECONF_ENABLE;
2130
2131 I915_WRITE(reg, val);
2132 if ((val & PIPECONF_ENABLE) == 0)
2133 intel_wait_for_pipe_off(crtc);
2094} 2134}
2095 2135
2096/* 2136/*
@@ -2109,35 +2149,28 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2109 2149
2110/** 2150/**
2111 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe 2151 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2112 * @dev_priv: i915 private structure 2152 * @plane: plane to be enabled
2113 * @plane: plane to enable 2153 * @crtc: crtc for the plane
2114 * @pipe: pipe being fed
2115 * 2154 *
2116 * Enable @plane on @pipe, making sure that @pipe is running first. 2155 * Enable @plane on @crtc, making sure that the pipe is running first.
2117 */ 2156 */
2118static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, 2157static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2119 enum plane plane, enum pipe pipe) 2158 struct drm_crtc *crtc)
2120{ 2159{
2121 struct drm_device *dev = dev_priv->dev; 2160 struct drm_device *dev = plane->dev;
2122 struct intel_crtc *intel_crtc = 2161 struct drm_i915_private *dev_priv = dev->dev_private;
2123 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 2162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2124 int reg;
2125 u32 val;
2126 2163
2127 /* If the pipe isn't enabled, we can't pump pixels and may hang */ 2164 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2128 assert_pipe_enabled(dev_priv, pipe); 2165 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2129 2166
2130 if (intel_crtc->primary_enabled) 2167 if (intel_crtc->primary_enabled)
2131 return; 2168 return;
2132 2169
2133 intel_crtc->primary_enabled = true; 2170 intel_crtc->primary_enabled = true;
2134 2171
2135 reg = DSPCNTR(plane); 2172 dev_priv->display.update_primary_plane(crtc, plane->fb,
2136 val = I915_READ(reg); 2173 crtc->x, crtc->y);
2137 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2138
2139 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2140 intel_flush_primary_plane(dev_priv, plane);
2141 2174
2142 /* 2175 /*
2143 * BDW signals flip done immediately if the plane 2176 * BDW signals flip done immediately if the plane
@@ -2150,31 +2183,27 @@ static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2150 2183
2151/** 2184/**
2152 * intel_disable_primary_hw_plane - disable the primary hardware plane 2185 * intel_disable_primary_hw_plane - disable the primary hardware plane
2153 * @dev_priv: i915 private structure 2186 * @plane: plane to be disabled
2154 * @plane: plane to disable 2187 * @crtc: crtc for the plane
2155 * @pipe: pipe consuming the data
2156 * 2188 *
2157 * Disable @plane; should be an independent operation. 2189 * Disable @plane on @crtc, making sure that the pipe is running first.
2158 */ 2190 */
2159static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, 2191static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2160 enum plane plane, enum pipe pipe) 2192 struct drm_crtc *crtc)
2161{ 2193{
2162 struct intel_crtc *intel_crtc = 2194 struct drm_device *dev = plane->dev;
2163 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 2195 struct drm_i915_private *dev_priv = dev->dev_private;
2164 int reg; 2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2165 u32 val; 2197
2198 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2166 2199
2167 if (!intel_crtc->primary_enabled) 2200 if (!intel_crtc->primary_enabled)
2168 return; 2201 return;
2169 2202
2170 intel_crtc->primary_enabled = false; 2203 intel_crtc->primary_enabled = false;
2171 2204
2172 reg = DSPCNTR(plane); 2205 dev_priv->display.update_primary_plane(crtc, plane->fb,
2173 val = I915_READ(reg); 2206 crtc->x, crtc->y);
2174 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2175
2176 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2177 intel_flush_primary_plane(dev_priv, plane);
2178} 2207}
2179 2208
2180static bool need_vtd_wa(struct drm_device *dev) 2209static bool need_vtd_wa(struct drm_device *dev)
@@ -2422,16 +2451,46 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2422 struct drm_device *dev = crtc->dev; 2451 struct drm_device *dev = crtc->dev;
2423 struct drm_i915_private *dev_priv = dev->dev_private; 2452 struct drm_i915_private *dev_priv = dev->dev_private;
2424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2425 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2454 struct drm_i915_gem_object *obj;
2426 int plane = intel_crtc->plane; 2455 int plane = intel_crtc->plane;
2427 unsigned long linear_offset; 2456 unsigned long linear_offset;
2428 u32 dspcntr; 2457 u32 dspcntr;
2429 u32 reg; 2458 u32 reg = DSPCNTR(plane);
2459 int pixel_size;
2460
2461 if (!intel_crtc->primary_enabled) {
2462 I915_WRITE(reg, 0);
2463 if (INTEL_INFO(dev)->gen >= 4)
2464 I915_WRITE(DSPSURF(plane), 0);
2465 else
2466 I915_WRITE(DSPADDR(plane), 0);
2467 POSTING_READ(reg);
2468 return;
2469 }
2470
2471 obj = intel_fb_obj(fb);
2472 if (WARN_ON(obj == NULL))
2473 return;
2474
2475 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2476
2477 dspcntr = DISPPLANE_GAMMA_ENABLE;
2478
2479 dspcntr |= DISPLAY_PLANE_ENABLE;
2480
2481 if (INTEL_INFO(dev)->gen < 4) {
2482 if (intel_crtc->pipe == PIPE_B)
2483 dspcntr |= DISPPLANE_SEL_PIPE_B;
2484
2485 /* pipesrc and dspsize control the size that is scaled from,
2486 * which should always be the user's requested size.
2487 */
2488 I915_WRITE(DSPSIZE(plane),
2489 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2490 (intel_crtc->config.pipe_src_w - 1));
2491 I915_WRITE(DSPPOS(plane), 0);
2492 }
2430 2493
2431 reg = DSPCNTR(plane);
2432 dspcntr = I915_READ(reg);
2433 /* Mask out pixel format bits in case we change it */
2434 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2435 switch (fb->pixel_format) { 2494 switch (fb->pixel_format) {
2436 case DRM_FORMAT_C8: 2495 case DRM_FORMAT_C8:
2437 dspcntr |= DISPPLANE_8BPP; 2496 dspcntr |= DISPPLANE_8BPP;
@@ -2463,30 +2522,40 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2463 BUG(); 2522 BUG();
2464 } 2523 }
2465 2524
2466 if (INTEL_INFO(dev)->gen >= 4) { 2525 if (INTEL_INFO(dev)->gen >= 4 &&
2467 if (obj->tiling_mode != I915_TILING_NONE) 2526 obj->tiling_mode != I915_TILING_NONE)
2468 dspcntr |= DISPPLANE_TILED; 2527 dspcntr |= DISPPLANE_TILED;
2469 else
2470 dspcntr &= ~DISPPLANE_TILED;
2471 }
2472 2528
2473 if (IS_G4X(dev)) 2529 if (IS_G4X(dev))
2474 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 2530 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2475 2531
2476 I915_WRITE(reg, dspcntr); 2532 linear_offset = y * fb->pitches[0] + x * pixel_size;
2477
2478 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2479 2533
2480 if (INTEL_INFO(dev)->gen >= 4) { 2534 if (INTEL_INFO(dev)->gen >= 4) {
2481 intel_crtc->dspaddr_offset = 2535 intel_crtc->dspaddr_offset =
2482 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, 2536 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2483 fb->bits_per_pixel / 8, 2537 pixel_size,
2484 fb->pitches[0]); 2538 fb->pitches[0]);
2485 linear_offset -= intel_crtc->dspaddr_offset; 2539 linear_offset -= intel_crtc->dspaddr_offset;
2486 } else { 2540 } else {
2487 intel_crtc->dspaddr_offset = linear_offset; 2541 intel_crtc->dspaddr_offset = linear_offset;
2488 } 2542 }
2489 2543
2544 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2545 dspcntr |= DISPPLANE_ROTATE_180;
2546
2547 x += (intel_crtc->config.pipe_src_w - 1);
2548 y += (intel_crtc->config.pipe_src_h - 1);
2549
2550 /* Finding the last pixel of the last line of the display
2551 data and adding to linear_offset*/
2552 linear_offset +=
2553 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2554 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2555 }
2556
2557 I915_WRITE(reg, dspcntr);
2558
2490 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 2559 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2491 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, 2560 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2492 fb->pitches[0]); 2561 fb->pitches[0]);
@@ -2508,16 +2577,33 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2508 struct drm_device *dev = crtc->dev; 2577 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private; 2578 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2580 struct drm_i915_gem_object *obj;
2512 int plane = intel_crtc->plane; 2581 int plane = intel_crtc->plane;
2513 unsigned long linear_offset; 2582 unsigned long linear_offset;
2514 u32 dspcntr; 2583 u32 dspcntr;
2515 u32 reg; 2584 u32 reg = DSPCNTR(plane);
2585 int pixel_size;
2586
2587 if (!intel_crtc->primary_enabled) {
2588 I915_WRITE(reg, 0);
2589 I915_WRITE(DSPSURF(plane), 0);
2590 POSTING_READ(reg);
2591 return;
2592 }
2593
2594 obj = intel_fb_obj(fb);
2595 if (WARN_ON(obj == NULL))
2596 return;
2597
2598 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2599
2600 dspcntr = DISPPLANE_GAMMA_ENABLE;
2601
2602 dspcntr |= DISPLAY_PLANE_ENABLE;
2603
2604 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2605 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2516 2606
2517 reg = DSPCNTR(plane);
2518 dspcntr = I915_READ(reg);
2519 /* Mask out pixel format bits in case we change it */
2520 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2521 switch (fb->pixel_format) { 2607 switch (fb->pixel_format) {
2522 case DRM_FORMAT_C8: 2608 case DRM_FORMAT_C8:
2523 dspcntr |= DISPPLANE_8BPP; 2609 dspcntr |= DISPPLANE_8BPP;
@@ -2547,22 +2633,32 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2547 2633
2548 if (obj->tiling_mode != I915_TILING_NONE) 2634 if (obj->tiling_mode != I915_TILING_NONE)
2549 dspcntr |= DISPPLANE_TILED; 2635 dspcntr |= DISPPLANE_TILED;
2550 else
2551 dspcntr &= ~DISPPLANE_TILED;
2552 2636
2553 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2637 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2554 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2555 else
2556 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 2638 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2557 2639
2558 I915_WRITE(reg, dspcntr); 2640 linear_offset = y * fb->pitches[0] + x * pixel_size;
2559
2560 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2561 intel_crtc->dspaddr_offset = 2641 intel_crtc->dspaddr_offset =
2562 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, 2642 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2563 fb->bits_per_pixel / 8, 2643 pixel_size,
2564 fb->pitches[0]); 2644 fb->pitches[0]);
2565 linear_offset -= intel_crtc->dspaddr_offset; 2645 linear_offset -= intel_crtc->dspaddr_offset;
2646 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2647 dspcntr |= DISPPLANE_ROTATE_180;
2648
2649 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2650 x += (intel_crtc->config.pipe_src_w - 1);
2651 y += (intel_crtc->config.pipe_src_h - 1);
2652
2653 /* Finding the last pixel of the last line of the display
2654 data and adding to linear_offset*/
2655 linear_offset +=
2656 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2657 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2658 }
2659 }
2660
2661 I915_WRITE(reg, dspcntr);
2566 2662
2567 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 2663 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2568 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, 2664 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
@@ -3346,23 +3442,54 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev)
3346 return false; 3442 return false;
3347} 3443}
3348 3444
3445static void page_flip_completed(struct intel_crtc *intel_crtc)
3446{
3447 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3448 struct intel_unpin_work *work = intel_crtc->unpin_work;
3449
3450 /* ensure that the unpin work is consistent wrt ->pending. */
3451 smp_rmb();
3452 intel_crtc->unpin_work = NULL;
3453
3454 if (work->event)
3455 drm_send_vblank_event(intel_crtc->base.dev,
3456 intel_crtc->pipe,
3457 work->event);
3458
3459 drm_crtc_vblank_put(&intel_crtc->base);
3460
3461 wake_up_all(&dev_priv->pending_flip_queue);
3462 queue_work(dev_priv->wq, &work->work);
3463
3464 trace_i915_flip_complete(intel_crtc->plane,
3465 work->pending_flip_obj);
3466}
3467
3349void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 3468void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3350{ 3469{
3351 struct drm_device *dev = crtc->dev; 3470 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private; 3471 struct drm_i915_private *dev_priv = dev->dev_private;
3353 3472
3354 if (crtc->primary->fb == NULL)
3355 return;
3356
3357 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); 3473 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3474 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3475 !intel_crtc_has_pending_flip(crtc),
3476 60*HZ) == 0)) {
3477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3478 unsigned long flags;
3358 3479
3359 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, 3480 spin_lock_irqsave(&dev->event_lock, flags);
3360 !intel_crtc_has_pending_flip(crtc), 3481 if (intel_crtc->unpin_work) {
3361 60*HZ) == 0); 3482 WARN_ONCE(1, "Removing stuck page flip\n");
3483 page_flip_completed(intel_crtc);
3484 }
3485 spin_unlock_irqrestore(&dev->event_lock, flags);
3486 }
3362 3487
3363 mutex_lock(&dev->struct_mutex); 3488 if (crtc->primary->fb) {
3364 intel_finish_fb(crtc->primary->fb); 3489 mutex_lock(&dev->struct_mutex);
3365 mutex_unlock(&dev->struct_mutex); 3490 intel_finish_fb(crtc->primary->fb);
3491 mutex_unlock(&dev->struct_mutex);
3492 }
3366} 3493}
3367 3494
3368/* Program iCLKIP clock to the desired frequency */ 3495/* Program iCLKIP clock to the desired frequency */
@@ -3911,14 +4038,14 @@ static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3911static void intel_crtc_enable_planes(struct drm_crtc *crtc) 4038static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3912{ 4039{
3913 struct drm_device *dev = crtc->dev; 4040 struct drm_device *dev = crtc->dev;
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3916 int pipe = intel_crtc->pipe; 4042 int pipe = intel_crtc->pipe;
3917 int plane = intel_crtc->plane; 4043
4044 assert_vblank_disabled(crtc);
3918 4045
3919 drm_vblank_on(dev, pipe); 4046 drm_vblank_on(dev, pipe);
3920 4047
3921 intel_enable_primary_hw_plane(dev_priv, plane, pipe); 4048 intel_enable_primary_hw_plane(crtc->primary, crtc);
3922 intel_enable_planes(crtc); 4049 intel_enable_planes(crtc);
3923 intel_crtc_update_cursor(crtc, true); 4050 intel_crtc_update_cursor(crtc, true);
3924 intel_crtc_dpms_overlay(intel_crtc, true); 4051 intel_crtc_dpms_overlay(intel_crtc, true);
@@ -3955,7 +4082,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3955 intel_crtc_dpms_overlay(intel_crtc, false); 4082 intel_crtc_dpms_overlay(intel_crtc, false);
3956 intel_crtc_update_cursor(crtc, false); 4083 intel_crtc_update_cursor(crtc, false);
3957 intel_disable_planes(crtc); 4084 intel_disable_planes(crtc);
3958 intel_disable_primary_hw_plane(dev_priv, plane, pipe); 4085 intel_disable_primary_hw_plane(crtc->primary, crtc);
3959 4086
3960 /* 4087 /*
3961 * FIXME: Once we grow proper nuclear flip support out of this we need 4088 * FIXME: Once we grow proper nuclear flip support out of this we need
@@ -3965,6 +4092,8 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3965 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); 4092 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3966 4093
3967 drm_vblank_off(dev, pipe); 4094 drm_vblank_off(dev, pipe);
4095
4096 assert_vblank_disabled(crtc);
3968} 4097}
3969 4098
3970static void ironlake_crtc_enable(struct drm_crtc *crtc) 4099static void ironlake_crtc_enable(struct drm_crtc *crtc)
@@ -3974,7 +4103,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3975 struct intel_encoder *encoder; 4104 struct intel_encoder *encoder;
3976 int pipe = intel_crtc->pipe; 4105 int pipe = intel_crtc->pipe;
3977 enum plane plane = intel_crtc->plane;
3978 4106
3979 WARN_ON(!crtc->enabled); 4107 WARN_ON(!crtc->enabled);
3980 4108
@@ -3991,18 +4119,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3991 4119
3992 if (intel_crtc->config.has_pch_encoder) { 4120 if (intel_crtc->config.has_pch_encoder) {
3993 intel_cpu_transcoder_set_m_n(intel_crtc, 4121 intel_cpu_transcoder_set_m_n(intel_crtc,
3994 &intel_crtc->config.fdi_m_n); 4122 &intel_crtc->config.fdi_m_n, NULL);
3995 } 4123 }
3996 4124
3997 ironlake_set_pipeconf(crtc); 4125 ironlake_set_pipeconf(crtc);
3998 4126
3999 /* Set up the display plane register */
4000 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
4001 POSTING_READ(DSPCNTR(plane));
4002
4003 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4004 crtc->x, crtc->y);
4005
4006 intel_crtc->active = true; 4127 intel_crtc->active = true;
4007 4128
4008 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); 4129 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -4087,7 +4208,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088 struct intel_encoder *encoder; 4209 struct intel_encoder *encoder;
4089 int pipe = intel_crtc->pipe; 4210 int pipe = intel_crtc->pipe;
4090 enum plane plane = intel_crtc->plane;
4091 4211
4092 WARN_ON(!crtc->enabled); 4212 WARN_ON(!crtc->enabled);
4093 4213
@@ -4102,22 +4222,20 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4102 4222
4103 intel_set_pipe_timings(intel_crtc); 4223 intel_set_pipe_timings(intel_crtc);
4104 4224
4225 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4226 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4227 intel_crtc->config.pixel_multiplier - 1);
4228 }
4229
4105 if (intel_crtc->config.has_pch_encoder) { 4230 if (intel_crtc->config.has_pch_encoder) {
4106 intel_cpu_transcoder_set_m_n(intel_crtc, 4231 intel_cpu_transcoder_set_m_n(intel_crtc,
4107 &intel_crtc->config.fdi_m_n); 4232 &intel_crtc->config.fdi_m_n, NULL);
4108 } 4233 }
4109 4234
4110 haswell_set_pipeconf(crtc); 4235 haswell_set_pipeconf(crtc);
4111 4236
4112 intel_set_pipe_csc(crtc); 4237 intel_set_pipe_csc(crtc);
4113 4238
4114 /* Set up the display plane register */
4115 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4116 POSTING_READ(DSPCNTR(plane));
4117
4118 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4119 crtc->x, crtc->y);
4120
4121 intel_crtc->active = true; 4239 intel_crtc->active = true;
4122 4240
4123 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); 4241 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -4198,7 +4316,8 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
4198 if (intel_crtc->config.has_pch_encoder) 4316 if (intel_crtc->config.has_pch_encoder)
4199 intel_set_pch_fifo_underrun_reporting(dev, pipe, false); 4317 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4200 4318
4201 intel_disable_pipe(dev_priv, pipe); 4319 intel_disable_pipe(intel_crtc);
4320
4202 ironlake_pfit_disable(intel_crtc); 4321 ironlake_pfit_disable(intel_crtc);
4203 4322
4204 for_each_encoder_on_crtc(dev, crtc, encoder) 4323 for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -4246,7 +4365,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
4246 struct drm_i915_private *dev_priv = dev->dev_private; 4365 struct drm_i915_private *dev_priv = dev->dev_private;
4247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4248 struct intel_encoder *encoder; 4367 struct intel_encoder *encoder;
4249 int pipe = intel_crtc->pipe;
4250 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 4368 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4251 4369
4252 if (!intel_crtc->active) 4370 if (!intel_crtc->active)
@@ -4261,7 +4379,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
4261 4379
4262 if (intel_crtc->config.has_pch_encoder) 4380 if (intel_crtc->config.has_pch_encoder)
4263 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); 4381 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4264 intel_disable_pipe(dev_priv, pipe); 4382 intel_disable_pipe(intel_crtc);
4265 4383
4266 if (intel_crtc->config.dp_encoder_is_mst) 4384 if (intel_crtc->config.dp_encoder_is_mst)
4267 intel_ddi_set_vc_payload_alloc(crtc, false); 4385 intel_ddi_set_vc_payload_alloc(crtc, false);
@@ -4539,12 +4657,57 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4539 vlv_update_cdclk(dev); 4657 vlv_update_cdclk(dev);
4540} 4658}
4541 4659
4660static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4661{
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 u32 val, cmd;
4664
4665 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4666
4667 switch (cdclk) {
4668 case 400000:
4669 cmd = 3;
4670 break;
4671 case 333333:
4672 case 320000:
4673 cmd = 2;
4674 break;
4675 case 266667:
4676 cmd = 1;
4677 break;
4678 case 200000:
4679 cmd = 0;
4680 break;
4681 default:
4682 WARN_ON(1);
4683 return;
4684 }
4685
4686 mutex_lock(&dev_priv->rps.hw_lock);
4687 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4688 val &= ~DSPFREQGUAR_MASK_CHV;
4689 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4690 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4691 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4692 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4693 50)) {
4694 DRM_ERROR("timed out waiting for CDclk change\n");
4695 }
4696 mutex_unlock(&dev_priv->rps.hw_lock);
4697
4698 vlv_update_cdclk(dev);
4699}
4700
4542static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, 4701static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4543 int max_pixclk) 4702 int max_pixclk)
4544{ 4703{
4545 int vco = valleyview_get_vco(dev_priv); 4704 int vco = valleyview_get_vco(dev_priv);
4546 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000; 4705 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4547 4706
4707 /* FIXME: Punit isn't quite ready yet */
4708 if (IS_CHERRYVIEW(dev_priv->dev))
4709 return 400000;
4710
4548 /* 4711 /*
4549 * Really only a few cases to deal with, as only 4 CDclks are supported: 4712 * Really only a few cases to deal with, as only 4 CDclks are supported:
4550 * 200MHz 4713 * 200MHz
@@ -4607,21 +4770,23 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
4607 int max_pixclk = intel_mode_max_pixclk(dev_priv); 4770 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4608 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); 4771 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4609 4772
4610 if (req_cdclk != dev_priv->vlv_cdclk_freq) 4773 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4611 valleyview_set_cdclk(dev, req_cdclk); 4774 if (IS_CHERRYVIEW(dev))
4775 cherryview_set_cdclk(dev, req_cdclk);
4776 else
4777 valleyview_set_cdclk(dev, req_cdclk);
4778 }
4779
4612 modeset_update_crtc_power_domains(dev); 4780 modeset_update_crtc_power_domains(dev);
4613} 4781}
4614 4782
4615static void valleyview_crtc_enable(struct drm_crtc *crtc) 4783static void valleyview_crtc_enable(struct drm_crtc *crtc)
4616{ 4784{
4617 struct drm_device *dev = crtc->dev; 4785 struct drm_device *dev = crtc->dev;
4618 struct drm_i915_private *dev_priv = dev->dev_private;
4619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4620 struct intel_encoder *encoder; 4787 struct intel_encoder *encoder;
4621 int pipe = intel_crtc->pipe; 4788 int pipe = intel_crtc->pipe;
4622 int plane = intel_crtc->plane;
4623 bool is_dsi; 4789 bool is_dsi;
4624 u32 dspcntr;
4625 4790
4626 WARN_ON(!crtc->enabled); 4791 WARN_ON(!crtc->enabled);
4627 4792
@@ -4630,33 +4795,20 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
4630 4795
4631 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); 4796 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4632 4797
4633 if (!is_dsi && !IS_CHERRYVIEW(dev)) 4798 if (!is_dsi) {
4634 vlv_prepare_pll(intel_crtc); 4799 if (IS_CHERRYVIEW(dev))
4635 4800 chv_prepare_pll(intel_crtc);
4636 /* Set up the display plane register */ 4801 else
4637 dspcntr = DISPPLANE_GAMMA_ENABLE; 4802 vlv_prepare_pll(intel_crtc);
4803 }
4638 4804
4639 if (intel_crtc->config.has_dp_encoder) 4805 if (intel_crtc->config.has_dp_encoder)
4640 intel_dp_set_m_n(intel_crtc); 4806 intel_dp_set_m_n(intel_crtc);
4641 4807
4642 intel_set_pipe_timings(intel_crtc); 4808 intel_set_pipe_timings(intel_crtc);
4643 4809
4644 /* pipesrc and dspsize control the size that is scaled from,
4645 * which should always be the user's requested size.
4646 */
4647 I915_WRITE(DSPSIZE(plane),
4648 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4649 (intel_crtc->config.pipe_src_w - 1));
4650 I915_WRITE(DSPPOS(plane), 0);
4651
4652 i9xx_set_pipeconf(intel_crtc); 4810 i9xx_set_pipeconf(intel_crtc);
4653 4811
4654 I915_WRITE(DSPCNTR(plane), dspcntr);
4655 POSTING_READ(DSPCNTR(plane));
4656
4657 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4658 crtc->x, crtc->y);
4659
4660 intel_crtc->active = true; 4812 intel_crtc->active = true;
4661 4813
4662 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); 4814 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -4704,12 +4856,9 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4704static void i9xx_crtc_enable(struct drm_crtc *crtc) 4856static void i9xx_crtc_enable(struct drm_crtc *crtc)
4705{ 4857{
4706 struct drm_device *dev = crtc->dev; 4858 struct drm_device *dev = crtc->dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709 struct intel_encoder *encoder; 4860 struct intel_encoder *encoder;
4710 int pipe = intel_crtc->pipe; 4861 int pipe = intel_crtc->pipe;
4711 int plane = intel_crtc->plane;
4712 u32 dspcntr;
4713 4862
4714 WARN_ON(!crtc->enabled); 4863 WARN_ON(!crtc->enabled);
4715 4864
@@ -4718,35 +4867,13 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
4718 4867
4719 i9xx_set_pll_dividers(intel_crtc); 4868 i9xx_set_pll_dividers(intel_crtc);
4720 4869
4721 /* Set up the display plane register */
4722 dspcntr = DISPPLANE_GAMMA_ENABLE;
4723
4724 if (pipe == 0)
4725 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4726 else
4727 dspcntr |= DISPPLANE_SEL_PIPE_B;
4728
4729 if (intel_crtc->config.has_dp_encoder) 4870 if (intel_crtc->config.has_dp_encoder)
4730 intel_dp_set_m_n(intel_crtc); 4871 intel_dp_set_m_n(intel_crtc);
4731 4872
4732 intel_set_pipe_timings(intel_crtc); 4873 intel_set_pipe_timings(intel_crtc);
4733 4874
4734 /* pipesrc and dspsize control the size that is scaled from,
4735 * which should always be the user's requested size.
4736 */
4737 I915_WRITE(DSPSIZE(plane),
4738 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4739 (intel_crtc->config.pipe_src_w - 1));
4740 I915_WRITE(DSPPOS(plane), 0);
4741
4742 i9xx_set_pipeconf(intel_crtc); 4875 i9xx_set_pipeconf(intel_crtc);
4743 4876
4744 I915_WRITE(DSPCNTR(plane), dspcntr);
4745 POSTING_READ(DSPCNTR(plane));
4746
4747 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4748 crtc->x, crtc->y);
4749
4750 intel_crtc->active = true; 4877 intel_crtc->active = true;
4751 4878
4752 if (!IS_GEN2(dev)) 4879 if (!IS_GEN2(dev))
@@ -4842,7 +4969,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
4842 */ 4969 */
4843 intel_wait_for_vblank(dev, pipe); 4970 intel_wait_for_vblank(dev, pipe);
4844 4971
4845 intel_disable_pipe(dev_priv, pipe); 4972 intel_disable_pipe(intel_crtc);
4846 4973
4847 i9xx_pfit_disable(intel_crtc); 4974 i9xx_pfit_disable(intel_crtc);
4848 4975
@@ -4856,7 +4983,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
4856 else if (IS_VALLEYVIEW(dev)) 4983 else if (IS_VALLEYVIEW(dev))
4857 vlv_disable_pll(dev_priv, pipe); 4984 vlv_disable_pll(dev_priv, pipe);
4858 else 4985 else
4859 i9xx_disable_pll(dev_priv, pipe); 4986 i9xx_disable_pll(intel_crtc);
4860 } 4987 }
4861 4988
4862 if (!IS_GEN2(dev)) 4989 if (!IS_GEN2(dev))
@@ -5275,6 +5402,10 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
5275 u32 val; 5402 u32 val;
5276 int divider; 5403 int divider;
5277 5404
5405 /* FIXME: Punit isn't quite ready yet */
5406 if (IS_CHERRYVIEW(dev))
5407 return 400000;
5408
5278 mutex_lock(&dev_priv->dpio_lock); 5409 mutex_lock(&dev_priv->dpio_lock);
5279 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 5410 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5280 mutex_unlock(&dev_priv->dpio_lock); 5411 mutex_unlock(&dev_priv->dpio_lock);
@@ -5519,7 +5650,8 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5519} 5650}
5520 5651
5521static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 5652static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5522 struct intel_link_m_n *m_n) 5653 struct intel_link_m_n *m_n,
5654 struct intel_link_m_n *m2_n2)
5523{ 5655{
5524 struct drm_device *dev = crtc->base.dev; 5656 struct drm_device *dev = crtc->base.dev;
5525 struct drm_i915_private *dev_priv = dev->dev_private; 5657 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5531,6 +5663,18 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5531 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); 5663 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5532 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); 5664 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5533 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); 5665 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5666 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5667 * for gen < 8) and if DRRS is supported (to make sure the
5668 * registers are not unnecessarily accessed).
5669 */
5670 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5671 crtc->config.has_drrs) {
5672 I915_WRITE(PIPE_DATA_M2(transcoder),
5673 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5674 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5675 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5676 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5677 }
5534 } else { 5678 } else {
5535 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); 5679 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5536 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); 5680 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
@@ -5539,12 +5683,13 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5539 } 5683 }
5540} 5684}
5541 5685
5542static void intel_dp_set_m_n(struct intel_crtc *crtc) 5686void intel_dp_set_m_n(struct intel_crtc *crtc)
5543{ 5687{
5544 if (crtc->config.has_pch_encoder) 5688 if (crtc->config.has_pch_encoder)
5545 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); 5689 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5546 else 5690 else
5547 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); 5691 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5692 &crtc->config.dp_m2_n2);
5548} 5693}
5549 5694
5550static void vlv_update_pll(struct intel_crtc *crtc) 5695static void vlv_update_pll(struct intel_crtc *crtc)
@@ -5662,6 +5807,18 @@ static void vlv_prepare_pll(struct intel_crtc *crtc)
5662 5807
5663static void chv_update_pll(struct intel_crtc *crtc) 5808static void chv_update_pll(struct intel_crtc *crtc)
5664{ 5809{
5810 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5811 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5812 DPLL_VCO_ENABLE;
5813 if (crtc->pipe != PIPE_A)
5814 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5815
5816 crtc->config.dpll_hw_state.dpll_md =
5817 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5818}
5819
5820static void chv_prepare_pll(struct intel_crtc *crtc)
5821{
5665 struct drm_device *dev = crtc->base.dev; 5822 struct drm_device *dev = crtc->base.dev;
5666 struct drm_i915_private *dev_priv = dev->dev_private; 5823 struct drm_i915_private *dev_priv = dev->dev_private;
5667 int pipe = crtc->pipe; 5824 int pipe = crtc->pipe;
@@ -5671,15 +5828,6 @@ static void chv_update_pll(struct intel_crtc *crtc)
5671 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 5828 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5672 int refclk; 5829 int refclk;
5673 5830
5674 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5675 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5676 DPLL_VCO_ENABLE;
5677 if (pipe != PIPE_A)
5678 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5679
5680 crtc->config.dpll_hw_state.dpll_md =
5681 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5682
5683 bestn = crtc->config.dpll.n; 5831 bestn = crtc->config.dpll.n;
5684 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; 5832 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5685 bestm1 = crtc->config.dpll.m1; 5833 bestm1 = crtc->config.dpll.m1;
@@ -5839,7 +5987,7 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
5839 dpll |= PLL_P2_DIVIDE_BY_4; 5987 dpll |= PLL_P2_DIVIDE_BY_4;
5840 } 5988 }
5841 5989
5842 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) 5990 if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5843 dpll |= DPLL_DVO_2X_MODE; 5991 dpll |= DPLL_DVO_2X_MODE;
5844 5992
5845 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && 5993 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
@@ -5990,9 +6138,9 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5990 6138
5991 pipeconf = 0; 6139 pipeconf = 0;
5992 6140
5993 if (dev_priv->quirks & QUIRK_PIPEA_FORCE && 6141 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
5994 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) 6142 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
5995 pipeconf |= PIPECONF_ENABLE; 6143 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
5996 6144
5997 if (intel_crtc->config.double_wide) 6145 if (intel_crtc->config.double_wide)
5998 pipeconf |= PIPECONF_DOUBLE_WIDE; 6146 pipeconf |= PIPECONF_DOUBLE_WIDE;
@@ -6235,7 +6383,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
6235 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; 6383 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6236 6384
6237 val = I915_READ(DSPSTRIDE(pipe)); 6385 val = I915_READ(DSPSTRIDE(pipe));
6238 crtc->base.primary->fb->pitches[0] = val & 0xffffff80; 6386 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6239 6387
6240 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, 6388 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6241 plane_config->tiled); 6389 plane_config->tiled);
@@ -6345,6 +6493,14 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6345 } 6493 }
6346 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); 6494 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6347 if (!IS_VALLEYVIEW(dev)) { 6495 if (!IS_VALLEYVIEW(dev)) {
6496 /*
6497 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6498 * on 830. Filter it out here so that we don't
6499 * report errors due to that.
6500 */
6501 if (IS_I830(dev))
6502 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6503
6348 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); 6504 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6349 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); 6505 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6350 } else { 6506 } else {
@@ -6367,7 +6523,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6367static void ironlake_init_pch_refclk(struct drm_device *dev) 6523static void ironlake_init_pch_refclk(struct drm_device *dev)
6368{ 6524{
6369 struct drm_i915_private *dev_priv = dev->dev_private; 6525 struct drm_i915_private *dev_priv = dev->dev_private;
6370 struct drm_mode_config *mode_config = &dev->mode_config;
6371 struct intel_encoder *encoder; 6526 struct intel_encoder *encoder;
6372 u32 val, final; 6527 u32 val, final;
6373 bool has_lvds = false; 6528 bool has_lvds = false;
@@ -6377,8 +6532,7 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
6377 bool can_ssc = false; 6532 bool can_ssc = false;
6378 6533
6379 /* We need to take the global config into account */ 6534 /* We need to take the global config into account */
6380 list_for_each_entry(encoder, &mode_config->encoder_list, 6535 for_each_intel_encoder(dev, encoder) {
6381 base.head) {
6382 switch (encoder->type) { 6536 switch (encoder->type) {
6383 case INTEL_OUTPUT_LVDS: 6537 case INTEL_OUTPUT_LVDS:
6384 has_panel = true; 6538 has_panel = true;
@@ -6685,11 +6839,10 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
6685 6839
6686static void lpt_init_pch_refclk(struct drm_device *dev) 6840static void lpt_init_pch_refclk(struct drm_device *dev)
6687{ 6841{
6688 struct drm_mode_config *mode_config = &dev->mode_config;
6689 struct intel_encoder *encoder; 6842 struct intel_encoder *encoder;
6690 bool has_vga = false; 6843 bool has_vga = false;
6691 6844
6692 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 6845 for_each_intel_encoder(dev, encoder) {
6693 switch (encoder->type) { 6846 switch (encoder->type) {
6694 case INTEL_OUTPUT_ANALOG: 6847 case INTEL_OUTPUT_ANALOG:
6695 has_vga = true; 6848 has_vga = true;
@@ -7145,7 +7298,8 @@ static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7145 7298
7146static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, 7299static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7147 enum transcoder transcoder, 7300 enum transcoder transcoder,
7148 struct intel_link_m_n *m_n) 7301 struct intel_link_m_n *m_n,
7302 struct intel_link_m_n *m2_n2)
7149{ 7303{
7150 struct drm_device *dev = crtc->base.dev; 7304 struct drm_device *dev = crtc->base.dev;
7151 struct drm_i915_private *dev_priv = dev->dev_private; 7305 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7159,6 +7313,20 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7159 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); 7313 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7160 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) 7314 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7161 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 7315 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7316 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7317 * gen < 8) and if DRRS is supported (to make sure the
7318 * registers are not unnecessarily read).
7319 */
7320 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7321 crtc->config.has_drrs) {
7322 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7323 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7324 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7325 & ~TU_SIZE_MASK;
7326 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7327 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7328 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7329 }
7162 } else { 7330 } else {
7163 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); 7331 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7164 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); 7332 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
@@ -7177,14 +7345,15 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
7177 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); 7345 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7178 else 7346 else
7179 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, 7347 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7180 &pipe_config->dp_m_n); 7348 &pipe_config->dp_m_n,
7349 &pipe_config->dp_m2_n2);
7181} 7350}
7182 7351
7183static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, 7352static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7184 struct intel_crtc_config *pipe_config) 7353 struct intel_crtc_config *pipe_config)
7185{ 7354{
7186 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, 7355 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7187 &pipe_config->fdi_m_n); 7356 &pipe_config->fdi_m_n, NULL);
7188} 7357}
7189 7358
7190static void ironlake_get_pfit_config(struct intel_crtc *crtc, 7359static void ironlake_get_pfit_config(struct intel_crtc *crtc,
@@ -7255,7 +7424,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
7255 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; 7424 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7256 7425
7257 val = I915_READ(DSPSTRIDE(pipe)); 7426 val = I915_READ(DSPSTRIDE(pipe));
7258 crtc->base.primary->fb->pitches[0] = val & 0xffffff80; 7427 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7259 7428
7260 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, 7429 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7261 plane_config->tiled); 7430 plane_config->tiled);
@@ -7615,6 +7784,22 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7615 return 0; 7784 return 0;
7616} 7785}
7617 7786
7787static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7788 enum port port,
7789 struct intel_crtc_config *pipe_config)
7790{
7791 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7792
7793 switch (pipe_config->ddi_pll_sel) {
7794 case PORT_CLK_SEL_WRPLL1:
7795 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7796 break;
7797 case PORT_CLK_SEL_WRPLL2:
7798 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7799 break;
7800 }
7801}
7802
7618static void haswell_get_ddi_port_state(struct intel_crtc *crtc, 7803static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7619 struct intel_crtc_config *pipe_config) 7804 struct intel_crtc_config *pipe_config)
7620{ 7805{
@@ -7628,16 +7813,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7628 7813
7629 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 7814 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7630 7815
7631 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); 7816 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7632
7633 switch (pipe_config->ddi_pll_sel) {
7634 case PORT_CLK_SEL_WRPLL1:
7635 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7636 break;
7637 case PORT_CLK_SEL_WRPLL2:
7638 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7639 break;
7640 }
7641 7817
7642 if (pipe_config->shared_dpll >= 0) { 7818 if (pipe_config->shared_dpll >= 0) {
7643 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; 7819 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
@@ -7719,7 +7895,12 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7719 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && 7895 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7720 (I915_READ(IPS_CTL) & IPS_ENABLE); 7896 (I915_READ(IPS_CTL) & IPS_ENABLE);
7721 7897
7722 pipe_config->pixel_multiplier = 1; 7898 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
7899 pipe_config->pixel_multiplier =
7900 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
7901 } else {
7902 pipe_config->pixel_multiplier = 1;
7903 }
7723 7904
7724 return true; 7905 return true;
7725} 7906}
@@ -8037,74 +8218,62 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8037 struct drm_device *dev = crtc->dev; 8218 struct drm_device *dev = crtc->dev;
8038 struct drm_i915_private *dev_priv = dev->dev_private; 8219 struct drm_i915_private *dev_priv = dev->dev_private;
8039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8040 uint32_t cntl; 8221 uint32_t cntl = 0, size = 0;
8041 8222
8042 if (base != intel_crtc->cursor_base) { 8223 if (base) {
8043 /* On these chipsets we can only modify the base whilst 8224 unsigned int width = intel_crtc->cursor_width;
8044 * the cursor is disabled. 8225 unsigned int height = intel_crtc->cursor_height;
8045 */ 8226 unsigned int stride = roundup_pow_of_two(width) * 4;
8046 if (intel_crtc->cursor_cntl) { 8227
8047 I915_WRITE(_CURACNTR, 0); 8228 switch (stride) {
8048 POSTING_READ(_CURACNTR); 8229 default:
8049 intel_crtc->cursor_cntl = 0; 8230 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8231 width, stride);
8232 stride = 256;
8233 /* fallthrough */
8234 case 256:
8235 case 512:
8236 case 1024:
8237 case 2048:
8238 break;
8050 } 8239 }
8051 8240
8052 I915_WRITE(_CURABASE, base); 8241 cntl |= CURSOR_ENABLE |
8053 POSTING_READ(_CURABASE); 8242 CURSOR_GAMMA_ENABLE |
8243 CURSOR_FORMAT_ARGB |
8244 CURSOR_STRIDE(stride);
8245
8246 size = (height << 12) | width;
8054 } 8247 }
8055 8248
8056 /* XXX width must be 64, stride 256 => 0x00 << 28 */ 8249 if (intel_crtc->cursor_cntl != 0 &&
8057 cntl = 0; 8250 (intel_crtc->cursor_base != base ||
8058 if (base) 8251 intel_crtc->cursor_size != size ||
8059 cntl = (CURSOR_ENABLE | 8252 intel_crtc->cursor_cntl != cntl)) {
8060 CURSOR_GAMMA_ENABLE | 8253 /* On these chipsets we can only modify the base/size/stride
8061 CURSOR_FORMAT_ARGB); 8254 * whilst the cursor is disabled.
8062 if (intel_crtc->cursor_cntl != cntl) { 8255 */
8063 I915_WRITE(_CURACNTR, cntl); 8256 I915_WRITE(_CURACNTR, 0);
8064 POSTING_READ(_CURACNTR); 8257 POSTING_READ(_CURACNTR);
8065 intel_crtc->cursor_cntl = cntl; 8258 intel_crtc->cursor_cntl = 0;
8066 } 8259 }
8067}
8068 8260
8069static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) 8261 if (intel_crtc->cursor_base != base)
8070{ 8262 I915_WRITE(_CURABASE, base);
8071 struct drm_device *dev = crtc->dev;
8072 struct drm_i915_private *dev_priv = dev->dev_private;
8073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8074 int pipe = intel_crtc->pipe;
8075 uint32_t cntl;
8076 8263
8077 cntl = 0; 8264 if (intel_crtc->cursor_size != size) {
8078 if (base) { 8265 I915_WRITE(CURSIZE, size);
8079 cntl = MCURSOR_GAMMA_ENABLE; 8266 intel_crtc->cursor_size = size;
8080 switch (intel_crtc->cursor_width) {
8081 case 64:
8082 cntl |= CURSOR_MODE_64_ARGB_AX;
8083 break;
8084 case 128:
8085 cntl |= CURSOR_MODE_128_ARGB_AX;
8086 break;
8087 case 256:
8088 cntl |= CURSOR_MODE_256_ARGB_AX;
8089 break;
8090 default:
8091 WARN_ON(1);
8092 return;
8093 }
8094 cntl |= pipe << 28; /* Connect to correct pipe */
8095 } 8267 }
8268
8096 if (intel_crtc->cursor_cntl != cntl) { 8269 if (intel_crtc->cursor_cntl != cntl) {
8097 I915_WRITE(CURCNTR(pipe), cntl); 8270 I915_WRITE(_CURACNTR, cntl);
8098 POSTING_READ(CURCNTR(pipe)); 8271 POSTING_READ(_CURACNTR);
8099 intel_crtc->cursor_cntl = cntl; 8272 intel_crtc->cursor_cntl = cntl;
8100 } 8273 }
8101
8102 /* and commit changes on next vblank */
8103 I915_WRITE(CURBASE(pipe), base);
8104 POSTING_READ(CURBASE(pipe));
8105} 8274}
8106 8275
8107static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) 8276static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8108{ 8277{
8109 struct drm_device *dev = crtc->dev; 8278 struct drm_device *dev = crtc->dev;
8110 struct drm_i915_private *dev_priv = dev->dev_private; 8279 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8129,6 +8298,7 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8129 WARN_ON(1); 8298 WARN_ON(1);
8130 return; 8299 return;
8131 } 8300 }
8301 cntl |= pipe << 28; /* Connect to correct pipe */
8132 } 8302 }
8133 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 8303 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8134 cntl |= CURSOR_PIPE_CSC_ENABLE; 8304 cntl |= CURSOR_PIPE_CSC_ENABLE;
@@ -8188,15 +8358,50 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8188 8358
8189 I915_WRITE(CURPOS(pipe), pos); 8359 I915_WRITE(CURPOS(pipe), pos);
8190 8360
8191 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) 8361 if (IS_845G(dev) || IS_I865G(dev))
8192 ivb_update_cursor(crtc, base);
8193 else if (IS_845G(dev) || IS_I865G(dev))
8194 i845_update_cursor(crtc, base); 8362 i845_update_cursor(crtc, base);
8195 else 8363 else
8196 i9xx_update_cursor(crtc, base); 8364 i9xx_update_cursor(crtc, base);
8197 intel_crtc->cursor_base = base; 8365 intel_crtc->cursor_base = base;
8198} 8366}
8199 8367
8368static bool cursor_size_ok(struct drm_device *dev,
8369 uint32_t width, uint32_t height)
8370{
8371 if (width == 0 || height == 0)
8372 return false;
8373
8374 /*
8375 * 845g/865g are special in that they are only limited by
8376 * the width of their cursors, the height is arbitrary up to
8377 * the precision of the register. Everything else requires
8378 * square cursors, limited to a few power-of-two sizes.
8379 */
8380 if (IS_845G(dev) || IS_I865G(dev)) {
8381 if ((width & 63) != 0)
8382 return false;
8383
8384 if (width > (IS_845G(dev) ? 64 : 512))
8385 return false;
8386
8387 if (height > 1023)
8388 return false;
8389 } else {
8390 switch (width | height) {
8391 case 256:
8392 case 128:
8393 if (IS_GEN2(dev))
8394 return false;
8395 case 64:
8396 break;
8397 default:
8398 return false;
8399 }
8400 }
8401
8402 return true;
8403}
8404
8200/* 8405/*
8201 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object 8406 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8202 * 8407 *
@@ -8212,7 +8417,7 @@ static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8212 struct drm_i915_private *dev_priv = dev->dev_private; 8417 struct drm_i915_private *dev_priv = dev->dev_private;
8213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8214 enum pipe pipe = intel_crtc->pipe; 8419 enum pipe pipe = intel_crtc->pipe;
8215 unsigned old_width; 8420 unsigned old_width, stride;
8216 uint32_t addr; 8421 uint32_t addr;
8217 int ret; 8422 int ret;
8218 8423
@@ -8220,20 +8425,18 @@ static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8220 if (!obj) { 8425 if (!obj) {
8221 DRM_DEBUG_KMS("cursor off\n"); 8426 DRM_DEBUG_KMS("cursor off\n");
8222 addr = 0; 8427 addr = 0;
8223 obj = NULL;
8224 mutex_lock(&dev->struct_mutex); 8428 mutex_lock(&dev->struct_mutex);
8225 goto finish; 8429 goto finish;
8226 } 8430 }
8227 8431
8228 /* Check for which cursor types we support */ 8432 /* Check for which cursor types we support */
8229 if (!((width == 64 && height == 64) || 8433 if (!cursor_size_ok(dev, width, height)) {
8230 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8231 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8232 DRM_DEBUG("Cursor dimension not supported\n"); 8434 DRM_DEBUG("Cursor dimension not supported\n");
8233 return -EINVAL; 8435 return -EINVAL;
8234 } 8436 }
8235 8437
8236 if (obj->base.size < width * height * 4) { 8438 stride = roundup_pow_of_two(width) * 4;
8439 if (obj->base.size < stride * height) {
8237 DRM_DEBUG_KMS("buffer is too small\n"); 8440 DRM_DEBUG_KMS("buffer is too small\n");
8238 ret = -ENOMEM; 8441 ret = -ENOMEM;
8239 goto fail; 8442 goto fail;
@@ -8295,9 +8498,6 @@ static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8295 addr = obj->phys_handle->busaddr; 8498 addr = obj->phys_handle->busaddr;
8296 } 8499 }
8297 8500
8298 if (IS_GEN2(dev))
8299 I915_WRITE(CURSIZE, (height << 12) | width);
8300
8301 finish: 8501 finish:
8302 if (intel_crtc->cursor_bo) { 8502 if (intel_crtc->cursor_bo) {
8303 if (!INTEL_INFO(dev)->cursor_needs_physical) 8503 if (!INTEL_INFO(dev)->cursor_needs_physical)
@@ -8944,12 +9144,13 @@ static void intel_mark_fb_busy(struct drm_device *dev,
8944 unsigned frontbuffer_bits, 9144 unsigned frontbuffer_bits,
8945 struct intel_engine_cs *ring) 9145 struct intel_engine_cs *ring)
8946{ 9146{
9147 struct drm_i915_private *dev_priv = dev->dev_private;
8947 enum pipe pipe; 9148 enum pipe pipe;
8948 9149
8949 if (!i915.powersave) 9150 if (!i915.powersave)
8950 return; 9151 return;
8951 9152
8952 for_each_pipe(pipe) { 9153 for_each_pipe(dev_priv, pipe) {
8953 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) 9154 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8954 continue; 9155 continue;
8955 9156
@@ -9019,6 +9220,14 @@ void intel_frontbuffer_flush(struct drm_device *dev,
9019 intel_mark_fb_busy(dev, frontbuffer_bits, NULL); 9220 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9020 9221
9021 intel_edp_psr_flush(dev, frontbuffer_bits); 9222 intel_edp_psr_flush(dev, frontbuffer_bits);
9223
9224 /*
9225 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9226 * needs to be reworked into a proper frontbuffer tracking scheme like
9227 * psr employs.
9228 */
9229 if (IS_BROADWELL(dev))
9230 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9022} 9231}
9023 9232
9024/** 9233/**
@@ -9151,7 +9360,6 @@ static void intel_unpin_work_fn(struct work_struct *__work)
9151static void do_intel_finish_page_flip(struct drm_device *dev, 9360static void do_intel_finish_page_flip(struct drm_device *dev,
9152 struct drm_crtc *crtc) 9361 struct drm_crtc *crtc)
9153{ 9362{
9154 struct drm_i915_private *dev_priv = dev->dev_private;
9155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9156 struct intel_unpin_work *work; 9364 struct intel_unpin_work *work;
9157 unsigned long flags; 9365 unsigned long flags;
@@ -9171,23 +9379,9 @@ static void do_intel_finish_page_flip(struct drm_device *dev,
9171 return; 9379 return;
9172 } 9380 }
9173 9381
9174 /* and that the unpin work is consistent wrt ->pending. */ 9382 page_flip_completed(intel_crtc);
9175 smp_rmb();
9176
9177 intel_crtc->unpin_work = NULL;
9178
9179 if (work->event)
9180 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9181
9182 drm_crtc_vblank_put(crtc);
9183 9383
9184 spin_unlock_irqrestore(&dev->event_lock, flags); 9384 spin_unlock_irqrestore(&dev->event_lock, flags);
9185
9186 wake_up_all(&dev_priv->pending_flip_queue);
9187
9188 queue_work(dev_priv->wq, &work->work);
9189
9190 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9191} 9385}
9192 9386
9193void intel_finish_page_flip(struct drm_device *dev, int pipe) 9387void intel_finish_page_flip(struct drm_device *dev, int pipe)
@@ -9532,6 +9726,8 @@ static bool use_mmio_flip(struct intel_engine_cs *ring,
9532 return false; 9726 return false;
9533 else if (i915.use_mmio_flip > 0) 9727 else if (i915.use_mmio_flip > 0)
9534 return true; 9728 return true;
9729 else if (i915.enable_execlists)
9730 return true;
9535 else 9731 else
9536 return ring != obj->ring; 9732 return ring != obj->ring;
9537} 9733}
@@ -9665,6 +9861,65 @@ static int intel_default_queue_flip(struct drm_device *dev,
9665 return -ENODEV; 9861 return -ENODEV;
9666} 9862}
9667 9863
9864static bool __intel_pageflip_stall_check(struct drm_device *dev,
9865 struct drm_crtc *crtc)
9866{
9867 struct drm_i915_private *dev_priv = dev->dev_private;
9868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9869 struct intel_unpin_work *work = intel_crtc->unpin_work;
9870 u32 addr;
9871
9872 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9873 return true;
9874
9875 if (!work->enable_stall_check)
9876 return false;
9877
9878 if (work->flip_ready_vblank == 0) {
9879 if (work->flip_queued_ring &&
9880 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9881 work->flip_queued_seqno))
9882 return false;
9883
9884 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9885 }
9886
9887 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9888 return false;
9889
9890 /* Potential stall - if we see that the flip has happened,
9891 * assume a missed interrupt. */
9892 if (INTEL_INFO(dev)->gen >= 4)
9893 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9894 else
9895 addr = I915_READ(DSPADDR(intel_crtc->plane));
9896
9897 /* There is a potential issue here with a false positive after a flip
9898 * to the same address. We could address this by checking for a
9899 * non-incrementing frame counter.
9900 */
9901 return addr == work->gtt_offset;
9902}
9903
9904void intel_check_page_flip(struct drm_device *dev, int pipe)
9905{
9906 struct drm_i915_private *dev_priv = dev->dev_private;
9907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9909 unsigned long flags;
9910
9911 if (crtc == NULL)
9912 return;
9913
9914 spin_lock_irqsave(&dev->event_lock, flags);
9915 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9916 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9917 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9918 page_flip_completed(intel_crtc);
9919 }
9920 spin_unlock_irqrestore(&dev->event_lock, flags);
9921}
9922
9668static int intel_crtc_page_flip(struct drm_crtc *crtc, 9923static int intel_crtc_page_flip(struct drm_crtc *crtc,
9669 struct drm_framebuffer *fb, 9924 struct drm_framebuffer *fb,
9670 struct drm_pending_vblank_event *event, 9925 struct drm_pending_vblank_event *event,
@@ -9721,12 +9976,20 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
9721 /* We borrow the event spin lock for protecting unpin_work */ 9976 /* We borrow the event spin lock for protecting unpin_work */
9722 spin_lock_irqsave(&dev->event_lock, flags); 9977 spin_lock_irqsave(&dev->event_lock, flags);
9723 if (intel_crtc->unpin_work) { 9978 if (intel_crtc->unpin_work) {
9724 spin_unlock_irqrestore(&dev->event_lock, flags); 9979 /* Before declaring the flip queue wedged, check if
9725 kfree(work); 9980 * the hardware completed the operation behind our backs.
9726 drm_crtc_vblank_put(crtc); 9981 */
9982 if (__intel_pageflip_stall_check(dev, crtc)) {
9983 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9984 page_flip_completed(intel_crtc);
9985 } else {
9986 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9987 spin_unlock_irqrestore(&dev->event_lock, flags);
9727 9988
9728 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 9989 drm_crtc_vblank_put(crtc);
9729 return -EBUSY; 9990 kfree(work);
9991 return -EBUSY;
9992 }
9730 } 9993 }
9731 intel_crtc->unpin_work = work; 9994 intel_crtc->unpin_work = work;
9732 spin_unlock_irqrestore(&dev->event_lock, flags); 9995 spin_unlock_irqrestore(&dev->event_lock, flags);
@@ -9746,8 +10009,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
9746 10009
9747 work->pending_flip_obj = obj; 10010 work->pending_flip_obj = obj;
9748 10011
9749 work->enable_stall_check = true;
9750
9751 atomic_inc(&intel_crtc->unpin_work_count); 10012 atomic_inc(&intel_crtc->unpin_work_count);
9752 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); 10013 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9753 10014
@@ -9776,14 +10037,26 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
9776 work->gtt_offset = 10037 work->gtt_offset =
9777 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; 10038 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9778 10039
9779 if (use_mmio_flip(ring, obj)) 10040 if (use_mmio_flip(ring, obj)) {
9780 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, 10041 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9781 page_flip_flags); 10042 page_flip_flags);
9782 else 10043 if (ret)
10044 goto cleanup_unpin;
10045
10046 work->flip_queued_seqno = obj->last_write_seqno;
10047 work->flip_queued_ring = obj->ring;
10048 } else {
9783 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, 10049 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9784 page_flip_flags); 10050 page_flip_flags);
9785 if (ret) 10051 if (ret)
9786 goto cleanup_unpin; 10052 goto cleanup_unpin;
10053
10054 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10055 work->flip_queued_ring = ring;
10056 }
10057
10058 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10059 work->enable_stall_check = true;
9787 10060
9788 i915_gem_track_fb(work->old_fb_obj, obj, 10061 i915_gem_track_fb(work->old_fb_obj, obj,
9789 INTEL_FRONTBUFFER_PRIMARY(pipe)); 10062 INTEL_FRONTBUFFER_PRIMARY(pipe));
@@ -9818,8 +10091,11 @@ free_work:
9818out_hang: 10091out_hang:
9819 intel_crtc_wait_for_pending_flips(crtc); 10092 intel_crtc_wait_for_pending_flips(crtc);
9820 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); 10093 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9821 if (ret == 0 && event) 10094 if (ret == 0 && event) {
10095 spin_lock_irqsave(&dev->event_lock, flags);
9822 drm_send_vblank_event(dev, pipe, event); 10096 drm_send_vblank_event(dev, pipe, event);
10097 spin_unlock_irqrestore(&dev->event_lock, flags);
10098 }
9823 } 10099 }
9824 return ret; 10100 return ret;
9825} 10101}
@@ -9847,8 +10123,7 @@ static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9847 to_intel_encoder(connector->base.encoder); 10123 to_intel_encoder(connector->base.encoder);
9848 } 10124 }
9849 10125
9850 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10126 for_each_intel_encoder(dev, encoder) {
9851 base.head) {
9852 encoder->new_crtc = 10127 encoder->new_crtc =
9853 to_intel_crtc(encoder->base.crtc); 10128 to_intel_crtc(encoder->base.crtc);
9854 } 10129 }
@@ -9879,8 +10154,7 @@ static void intel_modeset_commit_output_state(struct drm_device *dev)
9879 connector->base.encoder = &connector->new_encoder->base; 10154 connector->base.encoder = &connector->new_encoder->base;
9880 } 10155 }
9881 10156
9882 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10157 for_each_intel_encoder(dev, encoder) {
9883 base.head) {
9884 encoder->base.crtc = &encoder->new_crtc->base; 10158 encoder->base.crtc = &encoder->new_crtc->base;
9885 } 10159 }
9886 10160
@@ -10007,6 +10281,15 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
10007 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, 10281 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10008 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, 10282 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10009 pipe_config->dp_m_n.tu); 10283 pipe_config->dp_m_n.tu);
10284
10285 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10286 pipe_config->has_dp_encoder,
10287 pipe_config->dp_m2_n2.gmch_m,
10288 pipe_config->dp_m2_n2.gmch_n,
10289 pipe_config->dp_m2_n2.link_m,
10290 pipe_config->dp_m2_n2.link_n,
10291 pipe_config->dp_m2_n2.tu);
10292
10010 DRM_DEBUG_KMS("requested mode:\n"); 10293 DRM_DEBUG_KMS("requested mode:\n");
10011 drm_mode_debug_printmodeline(&pipe_config->requested_mode); 10294 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10012 DRM_DEBUG_KMS("adjusted mode:\n"); 10295 DRM_DEBUG_KMS("adjusted mode:\n");
@@ -10041,8 +10324,7 @@ static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10041 struct drm_device *dev = crtc->base.dev; 10324 struct drm_device *dev = crtc->base.dev;
10042 struct intel_encoder *source_encoder; 10325 struct intel_encoder *source_encoder;
10043 10326
10044 list_for_each_entry(source_encoder, 10327 for_each_intel_encoder(dev, source_encoder) {
10045 &dev->mode_config.encoder_list, base.head) {
10046 if (source_encoder->new_crtc != crtc) 10328 if (source_encoder->new_crtc != crtc)
10047 continue; 10329 continue;
10048 10330
@@ -10058,8 +10340,7 @@ static bool check_encoder_cloning(struct intel_crtc *crtc)
10058 struct drm_device *dev = crtc->base.dev; 10340 struct drm_device *dev = crtc->base.dev;
10059 struct intel_encoder *encoder; 10341 struct intel_encoder *encoder;
10060 10342
10061 list_for_each_entry(encoder, 10343 for_each_intel_encoder(dev, encoder) {
10062 &dev->mode_config.encoder_list, base.head) {
10063 if (encoder->new_crtc != crtc) 10344 if (encoder->new_crtc != crtc)
10064 continue; 10345 continue;
10065 10346
@@ -10143,8 +10424,7 @@ encoder_retry:
10143 * adjust it according to limitations or connector properties, and also 10424 * adjust it according to limitations or connector properties, and also
10144 * a chance to reject the mode entirely. 10425 * a chance to reject the mode entirely.
10145 */ 10426 */
10146 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10427 for_each_intel_encoder(dev, encoder) {
10147 base.head) {
10148 10428
10149 if (&encoder->new_crtc->base != crtc) 10429 if (&encoder->new_crtc->base != crtc)
10150 continue; 10430 continue;
@@ -10222,8 +10502,7 @@ intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10222 1 << connector->new_encoder->new_crtc->pipe; 10502 1 << connector->new_encoder->new_crtc->pipe;
10223 } 10503 }
10224 10504
10225 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10505 for_each_intel_encoder(dev, encoder) {
10226 base.head) {
10227 if (encoder->base.crtc == &encoder->new_crtc->base) 10506 if (encoder->base.crtc == &encoder->new_crtc->base)
10228 continue; 10507 continue;
10229 10508
@@ -10297,8 +10576,7 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10297 struct intel_crtc *intel_crtc; 10576 struct intel_crtc *intel_crtc;
10298 struct drm_connector *connector; 10577 struct drm_connector *connector;
10299 10578
10300 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, 10579 for_each_intel_encoder(dev, intel_encoder) {
10301 base.head) {
10302 if (!intel_encoder->base.crtc) 10580 if (!intel_encoder->base.crtc)
10303 continue; 10581 continue;
10304 10582
@@ -10387,6 +10665,22 @@ intel_pipe_config_compare(struct drm_device *dev,
10387 return false; \ 10665 return false; \
10388 } 10666 }
10389 10667
10668/* This is required for BDW+ where there is only one set of registers for
10669 * switching between high and low RR.
10670 * This macro can be used whenever a comparison has to be made between one
10671 * hw state and multiple sw state variables.
10672 */
10673#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10674 if ((current_config->name != pipe_config->name) && \
10675 (current_config->alt_name != pipe_config->name)) { \
10676 DRM_ERROR("mismatch in " #name " " \
10677 "(expected %i or %i, found %i)\n", \
10678 current_config->name, \
10679 current_config->alt_name, \
10680 pipe_config->name); \
10681 return false; \
10682 }
10683
10390#define PIPE_CONF_CHECK_FLAGS(name, mask) \ 10684#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10391 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 10685 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10392 DRM_ERROR("mismatch in " #name "(" #mask ") " \ 10686 DRM_ERROR("mismatch in " #name "(" #mask ") " \
@@ -10419,11 +10713,28 @@ intel_pipe_config_compare(struct drm_device *dev,
10419 PIPE_CONF_CHECK_I(fdi_m_n.tu); 10713 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10420 10714
10421 PIPE_CONF_CHECK_I(has_dp_encoder); 10715 PIPE_CONF_CHECK_I(has_dp_encoder);
10422 PIPE_CONF_CHECK_I(dp_m_n.gmch_m); 10716
10423 PIPE_CONF_CHECK_I(dp_m_n.gmch_n); 10717 if (INTEL_INFO(dev)->gen < 8) {
10424 PIPE_CONF_CHECK_I(dp_m_n.link_m); 10718 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10425 PIPE_CONF_CHECK_I(dp_m_n.link_n); 10719 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10426 PIPE_CONF_CHECK_I(dp_m_n.tu); 10720 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10721 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10722 PIPE_CONF_CHECK_I(dp_m_n.tu);
10723
10724 if (current_config->has_drrs) {
10725 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10726 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10727 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10728 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10729 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10730 }
10731 } else {
10732 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10733 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10734 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10735 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10736 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10737 }
10427 10738
10428 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); 10739 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10429 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); 10740 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
@@ -10509,6 +10820,7 @@ intel_pipe_config_compare(struct drm_device *dev,
10509 10820
10510#undef PIPE_CONF_CHECK_X 10821#undef PIPE_CONF_CHECK_X
10511#undef PIPE_CONF_CHECK_I 10822#undef PIPE_CONF_CHECK_I
10823#undef PIPE_CONF_CHECK_I_ALT
10512#undef PIPE_CONF_CHECK_FLAGS 10824#undef PIPE_CONF_CHECK_FLAGS
10513#undef PIPE_CONF_CHECK_CLOCK_FUZZY 10825#undef PIPE_CONF_CHECK_CLOCK_FUZZY
10514#undef PIPE_CONF_QUIRK 10826#undef PIPE_CONF_QUIRK
@@ -10538,8 +10850,7 @@ check_encoder_state(struct drm_device *dev)
10538 struct intel_encoder *encoder; 10850 struct intel_encoder *encoder;
10539 struct intel_connector *connector; 10851 struct intel_connector *connector;
10540 10852
10541 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10853 for_each_intel_encoder(dev, encoder) {
10542 base.head) {
10543 bool enabled = false; 10854 bool enabled = false;
10544 bool active = false; 10855 bool active = false;
10545 enum pipe pipe, tracked_pipe; 10856 enum pipe pipe, tracked_pipe;
@@ -10618,8 +10929,7 @@ check_crtc_state(struct drm_device *dev)
10618 WARN(crtc->active && !crtc->base.enabled, 10929 WARN(crtc->active && !crtc->base.enabled,
10619 "active crtc, but not enabled in sw tracking\n"); 10930 "active crtc, but not enabled in sw tracking\n");
10620 10931
10621 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10932 for_each_intel_encoder(dev, encoder) {
10622 base.head) {
10623 if (encoder->base.crtc != &crtc->base) 10933 if (encoder->base.crtc != &crtc->base)
10624 continue; 10934 continue;
10625 enabled = true; 10935 enabled = true;
@@ -10637,12 +10947,12 @@ check_crtc_state(struct drm_device *dev)
10637 active = dev_priv->display.get_pipe_config(crtc, 10947 active = dev_priv->display.get_pipe_config(crtc,
10638 &pipe_config); 10948 &pipe_config);
10639 10949
10640 /* hw state is inconsistent with the pipe A quirk */ 10950 /* hw state is inconsistent with the pipe quirk */
10641 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 10951 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10952 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10642 active = crtc->active; 10953 active = crtc->active;
10643 10954
10644 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10955 for_each_intel_encoder(dev, encoder) {
10645 base.head) {
10646 enum pipe pipe; 10956 enum pipe pipe;
10647 if (encoder->base.crtc != &crtc->base) 10957 if (encoder->base.crtc != &crtc->base)
10648 continue; 10958 continue;
@@ -11010,7 +11320,7 @@ static void intel_set_config_restore_state(struct drm_device *dev,
11010 } 11320 }
11011 11321
11012 count = 0; 11322 count = 0;
11013 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 11323 for_each_intel_encoder(dev, encoder) {
11014 encoder->new_crtc = 11324 encoder->new_crtc =
11015 to_intel_crtc(config->save_encoder_crtcs[count++]); 11325 to_intel_crtc(config->save_encoder_crtcs[count++]);
11016 } 11326 }
@@ -11169,8 +11479,7 @@ intel_modeset_stage_output_state(struct drm_device *dev,
11169 } 11479 }
11170 11480
11171 /* Check for any encoders that needs to be disabled. */ 11481 /* Check for any encoders that needs to be disabled. */
11172 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 11482 for_each_intel_encoder(dev, encoder) {
11173 base.head) {
11174 int num_connectors = 0; 11483 int num_connectors = 0;
11175 list_for_each_entry(connector, 11484 list_for_each_entry(connector,
11176 &dev->mode_config.connector_list, 11485 &dev->mode_config.connector_list,
@@ -11203,9 +11512,7 @@ intel_modeset_stage_output_state(struct drm_device *dev,
11203 for_each_intel_crtc(dev, crtc) { 11512 for_each_intel_crtc(dev, crtc) {
11204 crtc->new_enabled = false; 11513 crtc->new_enabled = false;
11205 11514
11206 list_for_each_entry(encoder, 11515 for_each_intel_encoder(dev, encoder) {
11207 &dev->mode_config.encoder_list,
11208 base.head) {
11209 if (encoder->new_crtc == crtc) { 11516 if (encoder->new_crtc == crtc) {
11210 crtc->new_enabled = true; 11517 crtc->new_enabled = true;
11211 break; 11518 break;
@@ -11242,7 +11549,7 @@ static void disable_crtc_nofb(struct intel_crtc *crtc)
11242 connector->new_encoder = NULL; 11549 connector->new_encoder = NULL;
11243 } 11550 }
11244 11551
11245 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 11552 for_each_intel_encoder(dev, encoder) {
11246 if (encoder->new_crtc == crtc) 11553 if (encoder->new_crtc == crtc)
11247 encoder->new_crtc = NULL; 11554 encoder->new_crtc = NULL;
11248 } 11555 }
@@ -11305,7 +11612,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
11305 ret = intel_set_mode(set->crtc, set->mode, 11612 ret = intel_set_mode(set->crtc, set->mode,
11306 set->x, set->y, set->fb); 11613 set->x, set->y, set->fb);
11307 } else if (config->fb_changed) { 11614 } else if (config->fb_changed) {
11308 struct drm_i915_private *dev_priv = dev->dev_private;
11309 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); 11615 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11310 11616
11311 intel_crtc_wait_for_pending_flips(set->crtc); 11617 intel_crtc_wait_for_pending_flips(set->crtc);
@@ -11319,8 +11625,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
11319 */ 11625 */
11320 if (!intel_crtc->primary_enabled && ret == 0) { 11626 if (!intel_crtc->primary_enabled && ret == 0) {
11321 WARN_ON(!intel_crtc->active); 11627 WARN_ON(!intel_crtc->active);
11322 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, 11628 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11323 intel_crtc->pipe);
11324 } 11629 }
11325 11630
11326 /* 11631 /*
@@ -11473,8 +11778,6 @@ static int
11473intel_primary_plane_disable(struct drm_plane *plane) 11778intel_primary_plane_disable(struct drm_plane *plane)
11474{ 11779{
11475 struct drm_device *dev = plane->dev; 11780 struct drm_device *dev = plane->dev;
11476 struct drm_i915_private *dev_priv = dev->dev_private;
11477 struct intel_plane *intel_plane = to_intel_plane(plane);
11478 struct intel_crtc *intel_crtc; 11781 struct intel_crtc *intel_crtc;
11479 11782
11480 if (!plane->fb) 11783 if (!plane->fb)
@@ -11497,8 +11800,8 @@ intel_primary_plane_disable(struct drm_plane *plane)
11497 goto disable_unpin; 11800 goto disable_unpin;
11498 11801
11499 intel_crtc_wait_for_pending_flips(plane->crtc); 11802 intel_crtc_wait_for_pending_flips(plane->crtc);
11500 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane, 11803 intel_disable_primary_hw_plane(plane, plane->crtc);
11501 intel_plane->pipe); 11804
11502disable_unpin: 11805disable_unpin:
11503 mutex_lock(&dev->struct_mutex); 11806 mutex_lock(&dev->struct_mutex);
11504 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, 11807 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
@@ -11520,7 +11823,6 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11520 struct drm_device *dev = crtc->dev; 11823 struct drm_device *dev = crtc->dev;
11521 struct drm_i915_private *dev_priv = dev->dev_private; 11824 struct drm_i915_private *dev_priv = dev->dev_private;
11522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11523 struct intel_plane *intel_plane = to_intel_plane(plane);
11524 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 11826 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11525 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); 11827 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11526 struct drm_rect dest = { 11828 struct drm_rect dest = {
@@ -11542,6 +11844,21 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11542 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, 11844 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11543 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, 11845 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11544 }; 11846 };
11847 const struct {
11848 int crtc_x, crtc_y;
11849 unsigned int crtc_w, crtc_h;
11850 uint32_t src_x, src_y, src_w, src_h;
11851 } orig = {
11852 .crtc_x = crtc_x,
11853 .crtc_y = crtc_y,
11854 .crtc_w = crtc_w,
11855 .crtc_h = crtc_h,
11856 .src_x = src_x,
11857 .src_y = src_y,
11858 .src_w = src_w,
11859 .src_h = src_h,
11860 };
11861 struct intel_plane *intel_plane = to_intel_plane(plane);
11545 bool visible; 11862 bool visible;
11546 int ret; 11863 int ret;
11547 11864
@@ -11607,9 +11924,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11607 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); 11924 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11608 11925
11609 if (intel_crtc->primary_enabled) 11926 if (intel_crtc->primary_enabled)
11610 intel_disable_primary_hw_plane(dev_priv, 11927 intel_disable_primary_hw_plane(plane, crtc);
11611 intel_plane->plane,
11612 intel_plane->pipe);
11613 11928
11614 11929
11615 if (plane->fb != fb) 11930 if (plane->fb != fb)
@@ -11618,16 +11933,42 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11618 11933
11619 mutex_unlock(&dev->struct_mutex); 11934 mutex_unlock(&dev->struct_mutex);
11620 11935
11621 return 0; 11936 } else {
11622 } 11937 if (intel_crtc && intel_crtc->active &&
11938 intel_crtc->primary_enabled) {
11939 /*
11940 * FBC does not work on some platforms for rotated
11941 * planes, so disable it when rotation is not 0 and
11942 * update it when rotation is set back to 0.
11943 *
11944 * FIXME: This is redundant with the fbc update done in
11945 * the primary plane enable function except that that
11946 * one is done too late. We eventually need to unify
11947 * this.
11948 */
11949 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11950 dev_priv->fbc.plane == intel_crtc->plane &&
11951 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11952 intel_disable_fbc(dev);
11953 }
11954 }
11955 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11956 if (ret)
11957 return ret;
11623 11958
11624 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); 11959 if (!intel_crtc->primary_enabled)
11625 if (ret) 11960 intel_enable_primary_hw_plane(plane, crtc);
11626 return ret; 11961 }
11627 11962
11628 if (!intel_crtc->primary_enabled) 11963 intel_plane->crtc_x = orig.crtc_x;
11629 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, 11964 intel_plane->crtc_y = orig.crtc_y;
11630 intel_crtc->pipe); 11965 intel_plane->crtc_w = orig.crtc_w;
11966 intel_plane->crtc_h = orig.crtc_h;
11967 intel_plane->src_x = orig.src_x;
11968 intel_plane->src_y = orig.src_y;
11969 intel_plane->src_w = orig.src_w;
11970 intel_plane->src_h = orig.src_h;
11971 intel_plane->obj = obj;
11631 11972
11632 return 0; 11973 return 0;
11633} 11974}
@@ -11644,6 +11985,7 @@ static const struct drm_plane_funcs intel_primary_plane_funcs = {
11644 .update_plane = intel_primary_plane_setplane, 11985 .update_plane = intel_primary_plane_setplane,
11645 .disable_plane = intel_primary_plane_disable, 11986 .disable_plane = intel_primary_plane_disable,
11646 .destroy = intel_plane_destroy, 11987 .destroy = intel_plane_destroy,
11988 .set_property = intel_plane_set_property
11647}; 11989};
11648 11990
11649static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, 11991static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
@@ -11661,6 +12003,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11661 primary->max_downscale = 1; 12003 primary->max_downscale = 1;
11662 primary->pipe = pipe; 12004 primary->pipe = pipe;
11663 primary->plane = pipe; 12005 primary->plane = pipe;
12006 primary->rotation = BIT(DRM_ROTATE_0);
11664 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) 12007 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11665 primary->plane = !pipe; 12008 primary->plane = !pipe;
11666 12009
@@ -11676,6 +12019,19 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11676 &intel_primary_plane_funcs, 12019 &intel_primary_plane_funcs,
11677 intel_primary_formats, num_formats, 12020 intel_primary_formats, num_formats,
11678 DRM_PLANE_TYPE_PRIMARY); 12021 DRM_PLANE_TYPE_PRIMARY);
12022
12023 if (INTEL_INFO(dev)->gen >= 4) {
12024 if (!dev->mode_config.rotation_property)
12025 dev->mode_config.rotation_property =
12026 drm_mode_create_rotation_property(dev,
12027 BIT(DRM_ROTATE_0) |
12028 BIT(DRM_ROTATE_180));
12029 if (dev->mode_config.rotation_property)
12030 drm_object_attach_property(&primary->base.base,
12031 dev->mode_config.rotation_property,
12032 primary->rotation);
12033 }
12034
11679 return &primary->base; 12035 return &primary->base;
11680} 12036}
11681 12037
@@ -11736,6 +12092,10 @@ intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11736 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); 12092 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11737 } else { 12093 } else {
11738 intel_crtc_update_cursor(crtc, visible); 12094 intel_crtc_update_cursor(crtc, visible);
12095
12096 intel_frontbuffer_flip(crtc->dev,
12097 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12098
11739 return 0; 12099 return 0;
11740 } 12100 }
11741} 12101}
@@ -11812,8 +12172,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
11812 12172
11813 intel_crtc->cursor_base = ~0; 12173 intel_crtc->cursor_base = ~0;
11814 intel_crtc->cursor_cntl = ~0; 12174 intel_crtc->cursor_cntl = ~0;
11815 12175 intel_crtc->cursor_size = ~0;
11816 init_waitqueue_head(&intel_crtc->vbl_wait);
11817 12176
11818 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 12177 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11819 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); 12178 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
@@ -11876,8 +12235,7 @@ static int intel_encoder_clones(struct intel_encoder *encoder)
11876 int index_mask = 0; 12235 int index_mask = 0;
11877 int entry = 0; 12236 int entry = 0;
11878 12237
11879 list_for_each_entry(source_encoder, 12238 for_each_intel_encoder(dev, source_encoder) {
11880 &dev->mode_config.encoder_list, base.head) {
11881 if (encoders_cloneable(encoder, source_encoder)) 12239 if (encoders_cloneable(encoder, source_encoder))
11882 index_mask |= (1 << entry); 12240 index_mask |= (1 << entry);
11883 12241
@@ -12066,7 +12424,7 @@ static void intel_setup_outputs(struct drm_device *dev)
12066 12424
12067 intel_edp_psr_init(dev); 12425 intel_edp_psr_init(dev);
12068 12426
12069 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 12427 for_each_intel_encoder(dev, encoder) {
12070 encoder->base.possible_crtcs = encoder->crtc_mask; 12428 encoder->base.possible_crtcs = encoder->crtc_mask;
12071 encoder->base.possible_clones = 12429 encoder->base.possible_clones =
12072 intel_encoder_clones(encoder); 12430 intel_encoder_clones(encoder);
@@ -12332,29 +12690,27 @@ static void intel_init_display(struct drm_device *dev)
12332 dev_priv->display.get_display_clock_speed = 12690 dev_priv->display.get_display_clock_speed =
12333 i830_get_display_clock_speed; 12691 i830_get_display_clock_speed;
12334 12692
12335 if (HAS_PCH_SPLIT(dev)) { 12693 if (IS_G4X(dev)) {
12336 if (IS_GEN5(dev)) {
12337 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12338 dev_priv->display.write_eld = ironlake_write_eld;
12339 } else if (IS_GEN6(dev)) {
12340 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12341 dev_priv->display.write_eld = ironlake_write_eld;
12342 dev_priv->display.modeset_global_resources =
12343 snb_modeset_global_resources;
12344 } else if (IS_IVYBRIDGE(dev)) {
12345 /* FIXME: detect B0+ stepping and use auto training */
12346 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12347 dev_priv->display.write_eld = ironlake_write_eld;
12348 dev_priv->display.modeset_global_resources =
12349 ivb_modeset_global_resources;
12350 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12351 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12352 dev_priv->display.write_eld = haswell_write_eld;
12353 dev_priv->display.modeset_global_resources =
12354 haswell_modeset_global_resources;
12355 }
12356 } else if (IS_G4X(dev)) {
12357 dev_priv->display.write_eld = g4x_write_eld; 12694 dev_priv->display.write_eld = g4x_write_eld;
12695 } else if (IS_GEN5(dev)) {
12696 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12697 dev_priv->display.write_eld = ironlake_write_eld;
12698 } else if (IS_GEN6(dev)) {
12699 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12700 dev_priv->display.write_eld = ironlake_write_eld;
12701 dev_priv->display.modeset_global_resources =
12702 snb_modeset_global_resources;
12703 } else if (IS_IVYBRIDGE(dev)) {
12704 /* FIXME: detect B0+ stepping and use auto training */
12705 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12706 dev_priv->display.write_eld = ironlake_write_eld;
12707 dev_priv->display.modeset_global_resources =
12708 ivb_modeset_global_resources;
12709 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12710 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12711 dev_priv->display.write_eld = haswell_write_eld;
12712 dev_priv->display.modeset_global_resources =
12713 haswell_modeset_global_resources;
12358 } else if (IS_VALLEYVIEW(dev)) { 12714 } else if (IS_VALLEYVIEW(dev)) {
12359 dev_priv->display.modeset_global_resources = 12715 dev_priv->display.modeset_global_resources =
12360 valleyview_modeset_global_resources; 12716 valleyview_modeset_global_resources;
@@ -12388,6 +12744,8 @@ static void intel_init_display(struct drm_device *dev)
12388 } 12744 }
12389 12745
12390 intel_panel_init_backlight_funcs(dev); 12746 intel_panel_init_backlight_funcs(dev);
12747
12748 mutex_init(&dev_priv->pps_mutex);
12391} 12749}
12392 12750
12393/* 12751/*
@@ -12403,6 +12761,14 @@ static void quirk_pipea_force(struct drm_device *dev)
12403 DRM_INFO("applying pipe a force quirk\n"); 12761 DRM_INFO("applying pipe a force quirk\n");
12404} 12762}
12405 12763
12764static void quirk_pipeb_force(struct drm_device *dev)
12765{
12766 struct drm_i915_private *dev_priv = dev->dev_private;
12767
12768 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12769 DRM_INFO("applying pipe b force quirk\n");
12770}
12771
12406/* 12772/*
12407 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 12773 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12408 */ 12774 */
@@ -12477,6 +12843,12 @@ static struct intel_quirk intel_quirks[] = {
12477 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 12843 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12478 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, 12844 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12479 12845
12846 /* 830 needs to leave pipe A & dpll A up */
12847 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12848
12849 /* 830 needs to leave pipe B & dpll B up */
12850 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12851
12480 /* Lenovo U160 cannot use SSC on LVDS */ 12852 /* Lenovo U160 cannot use SSC on LVDS */
12481 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 12853 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12482 12854
@@ -12550,7 +12922,11 @@ static void i915_disable_vga(struct drm_device *dev)
12550 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 12922 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12551 udelay(300); 12923 udelay(300);
12552 12924
12553 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 12925 /*
12926 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12927 * from S3 without preserving (some of?) the other bits.
12928 */
12929 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12554 POSTING_READ(vga_reg); 12930 POSTING_READ(vga_reg);
12555} 12931}
12556 12932
@@ -12563,8 +12939,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
12563 12939
12564 intel_init_clock_gating(dev); 12940 intel_init_clock_gating(dev);
12565 12941
12566 intel_reset_dpio(dev);
12567
12568 intel_enable_gt_powersave(dev); 12942 intel_enable_gt_powersave(dev);
12569} 12943}
12570 12944
@@ -12610,7 +12984,10 @@ void intel_modeset_init(struct drm_device *dev)
12610 dev->mode_config.max_height = 8192; 12984 dev->mode_config.max_height = 8192;
12611 } 12985 }
12612 12986
12613 if (IS_GEN2(dev)) { 12987 if (IS_845G(dev) || IS_I865G(dev)) {
12988 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12989 dev->mode_config.cursor_height = 1023;
12990 } else if (IS_GEN2(dev)) {
12614 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; 12991 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12615 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; 12992 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12616 } else { 12993 } else {
@@ -12624,7 +13001,7 @@ void intel_modeset_init(struct drm_device *dev)
12624 INTEL_INFO(dev)->num_pipes, 13001 INTEL_INFO(dev)->num_pipes,
12625 INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); 13002 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12626 13003
12627 for_each_pipe(pipe) { 13004 for_each_pipe(dev_priv, pipe) {
12628 intel_crtc_init(dev, pipe); 13005 intel_crtc_init(dev, pipe);
12629 for_each_sprite(pipe, sprite) { 13006 for_each_sprite(pipe, sprite) {
12630 ret = intel_plane_init(dev, pipe, sprite); 13007 ret = intel_plane_init(dev, pipe, sprite);
@@ -12635,10 +13012,11 @@ void intel_modeset_init(struct drm_device *dev)
12635 } 13012 }
12636 13013
12637 intel_init_dpio(dev); 13014 intel_init_dpio(dev);
12638 intel_reset_dpio(dev);
12639 13015
12640 intel_shared_dpll_init(dev); 13016 intel_shared_dpll_init(dev);
12641 13017
13018 /* save the BIOS value before clobbering it */
13019 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12642 /* Just disable it once at startup */ 13020 /* Just disable it once at startup */
12643 i915_disable_vga(dev); 13021 i915_disable_vga(dev);
12644 intel_setup_outputs(dev); 13022 intel_setup_outputs(dev);
@@ -12730,9 +13108,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
12730 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 13108 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12731 13109
12732 /* restore vblank interrupts to correct state */ 13110 /* restore vblank interrupts to correct state */
12733 if (crtc->active) 13111 if (crtc->active) {
13112 update_scanline_offset(crtc);
12734 drm_vblank_on(dev, crtc->pipe); 13113 drm_vblank_on(dev, crtc->pipe);
12735 else 13114 } else
12736 drm_vblank_off(dev, crtc->pipe); 13115 drm_vblank_off(dev, crtc->pipe);
12737 13116
12738 /* We need to sanitize the plane -> pipe mapping first because this will 13117 /* We need to sanitize the plane -> pipe mapping first because this will
@@ -12815,7 +13194,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
12815 } 13194 }
12816 } 13195 }
12817 13196
12818 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { 13197 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
12819 /* 13198 /*
12820 * We start out with underrun reporting disabled to avoid races. 13199 * We start out with underrun reporting disabled to avoid races.
12821 * For correct bookkeeping mark this on active crtcs. 13200 * For correct bookkeeping mark this on active crtcs.
@@ -12831,8 +13210,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
12831 */ 13210 */
12832 crtc->cpu_fifo_underrun_disabled = true; 13211 crtc->cpu_fifo_underrun_disabled = true;
12833 crtc->pch_fifo_underrun_disabled = true; 13212 crtc->pch_fifo_underrun_disabled = true;
12834
12835 update_scanline_offset(crtc);
12836 } 13213 }
12837} 13214}
12838 13215
@@ -12964,8 +13341,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
12964 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); 13341 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12965 } 13342 }
12966 13343
12967 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 13344 for_each_intel_encoder(dev, encoder) {
12968 base.head) {
12969 pipe = 0; 13345 pipe = 0;
12970 13346
12971 if (encoder->get_hw_state(encoder, &pipe)) { 13347 if (encoder->get_hw_state(encoder, &pipe)) {
@@ -13029,12 +13405,11 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
13029 } 13405 }
13030 13406
13031 /* HW state is read out, now we need to sanitize this mess. */ 13407 /* HW state is read out, now we need to sanitize this mess. */
13032 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 13408 for_each_intel_encoder(dev, encoder) {
13033 base.head) {
13034 intel_sanitize_encoder(encoder); 13409 intel_sanitize_encoder(encoder);
13035 } 13410 }
13036 13411
13037 for_each_pipe(pipe) { 13412 for_each_pipe(dev_priv, pipe) {
13038 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 13413 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13039 intel_sanitize_crtc(crtc); 13414 intel_sanitize_crtc(crtc);
13040 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); 13415 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
@@ -13062,7 +13437,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
13062 * We need to use raw interfaces for restoring state to avoid 13437 * We need to use raw interfaces for restoring state to avoid
13063 * checking (bogus) intermediate states. 13438 * checking (bogus) intermediate states.
13064 */ 13439 */
13065 for_each_pipe(pipe) { 13440 for_each_pipe(dev_priv, pipe) {
13066 struct drm_crtc *crtc = 13441 struct drm_crtc *crtc =
13067 dev_priv->pipe_to_crtc_mapping[pipe]; 13442 dev_priv->pipe_to_crtc_mapping[pipe];
13068 13443
@@ -13283,7 +13658,7 @@ intel_display_capture_error_state(struct drm_device *dev)
13283 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 13658 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13284 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); 13659 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13285 13660
13286 for_each_pipe(i) { 13661 for_each_pipe(dev_priv, i) {
13287 error->pipe[i].power_domain_on = 13662 error->pipe[i].power_domain_on =
13288 intel_display_power_enabled_unlocked(dev_priv, 13663 intel_display_power_enabled_unlocked(dev_priv,
13289 POWER_DOMAIN_PIPE(i)); 13664 POWER_DOMAIN_PIPE(i));
@@ -13347,6 +13722,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13347 struct drm_device *dev, 13722 struct drm_device *dev,
13348 struct intel_display_error_state *error) 13723 struct intel_display_error_state *error)
13349{ 13724{
13725 struct drm_i915_private *dev_priv = dev->dev_private;
13350 int i; 13726 int i;
13351 13727
13352 if (!error) 13728 if (!error)
@@ -13356,7 +13732,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13356 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 13732 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13357 err_printf(m, "PWR_WELL_CTL2: %08x\n", 13733 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13358 error->power_well_driver); 13734 error->power_well_driver);
13359 for_each_pipe(i) { 13735 for_each_pipe(dev_priv, i) {
13360 err_printf(m, "Pipe [%d]:\n", i); 13736 err_printf(m, "Pipe [%d]:\n", i);
13361 err_printf(m, " Power: %s\n", 13737 err_printf(m, " Power: %s\n",
13362 error->pipe[i].power_domain_on ? "on" : "off"); 13738 error->pipe[i].power_domain_on ? "on" : "off");
@@ -13397,3 +13773,25 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13397 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); 13773 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13398 } 13774 }
13399} 13775}
13776
13777void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13778{
13779 struct intel_crtc *crtc;
13780
13781 for_each_intel_crtc(dev, crtc) {
13782 struct intel_unpin_work *work;
13783 unsigned long irqflags;
13784
13785 spin_lock_irqsave(&dev->event_lock, irqflags);
13786
13787 work = crtc->unpin_work;
13788
13789 if (work && work->event &&
13790 work->event->base.file_priv == file) {
13791 kfree(work->event);
13792 work->event = NULL;
13793 }
13794
13795 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13796 }
13797}
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-21 22:04:11 -0400