1 files changed, 5 insertions, 55 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index be19b6d1ca52..2705da329ddf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -472,61 +472,14 @@ static void vlv_init_dpio(struct drm_device *dev)
         POSTING_READ(DPIO_CTL);
 }
 
-static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
-{
-        DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
-        return 1;
-}
-
-static const struct dmi_system_id intel_dual_link_lvds[] = {
-        {
-                .callback = intel_dual_link_lvds_callback,
-                .ident = "Apple MacBook Pro (Core i5/i7 Series)",
-                .matches = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
-                },
-        },
-        { }     /* terminating entry */
-};
-
-static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
-                              unsigned int reg)
-{
-        unsigned int val;
-
-        /* use the module option value if specified */
-        if (i915_lvds_channel_mode > 0)
-                return i915_lvds_channel_mode == 2;
-
-        if (dmi_check_system(intel_dual_link_lvds))
-                return true;
-
-        if (dev_priv->lvds_val)
-                val = dev_priv->lvds_val;
-        else {
-                /* BIOS should set the proper LVDS register value at boot, but
-                 * in reality, it doesn't set the value when the lid is closed;
-                 * we need to check "the value to be set" in VBT when LVDS
-                 * register is uninitialized.
-                 */
-                val = I915_READ(reg);
-                if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
-                        val = dev_priv->bios_lvds_val;
-                dev_priv->lvds_val = val;
-        }
-        return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
-}
-
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
                                                 int refclk)
 {
         struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
         const intel_limit_t *limit;
 
         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-                if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
+                if (intel_is_dual_link_lvds(dev)) {
                         /* LVDS dual channel */
                         if (refclk == 100000)
                                 limit = &intel_limits_ironlake_dual_lvds_100m;
@@ -550,11 +503,10 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 {
         struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
         const intel_limit_t *limit;
 
         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-                if (is_dual_link_lvds(dev_priv, LVDS))
+                if (intel_is_dual_link_lvds(dev))
                         /* LVDS with dual channel */
                         limit = &intel_limits_g4x_dual_channel_lvds;
                 else
@@ -686,7 +638,6 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 
 {
         struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
         intel_clock_t clock;
         int err = target;
 
@@ -696,7 +647,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                  * We haven't figured out how to reliably set up different
                  * single/dual channel state, if we even can.
                  */
-                if (is_dual_link_lvds(dev_priv, LVDS))
+                if (intel_is_dual_link_lvds(dev))
                         clock.p2 = limit->p2.p2_fast;
                 else
                         clock.p2 = limit->p2.p2_slow;
@@ -749,7 +700,6 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                         intel_clock_t *best_clock)
 {
         struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
         intel_clock_t clock;
         int max_n;
         bool found;
@@ -764,7 +714,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                         lvds_reg = PCH_LVDS;
                 else
                         lvds_reg = LVDS;
-                if (is_dual_link_lvds(dev_priv, lvds_reg))
+                if (intel_is_dual_link_lvds(dev))
                         clock.p2 = limit->p2.p2_fast;
                 else
                         clock.p2 = limit->p2.p2_slow;
@@ -5356,7 +5306,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
         if (is_lvds) {
                 if ((intel_panel_use_ssc(dev_priv) &&
                      dev_priv->lvds_ssc_freq == 100) ||
-                    is_dual_link_lvds(dev_priv, PCH_LVDS))
+                    intel_is_dual_link_lvds(dev))
                         factor = 25;
         } else if (is_sdvo && is_tv)
                 factor = 20;