1 files changed, 1097 insertions, 604 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d78d33f9337d..3cddd508d110 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -41,14 +41,13 @@
 #include <drm/drm_crtc_helper.h>
 #include <linux/dma_remapping.h>
-bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
 static void intel_increase_pllclock(struct drm_crtc *crtc);
 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                                struct intel_crtc_config *pipe_config);
-static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
+static void ironlake_pch_clock_get(struct intel_crtc *crtc,
-                                    struct intel_crtc_config *pipe_config);
+                                   struct intel_crtc_config *pipe_config);
 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
                          int x, int y, struct drm_framebuffer *old_fb);
@@ -69,9 +68,6 @@ struct intel_limit {
        intel_p2_t          p2;
 };
-/* FDI */
-#define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 int
 intel_pch_rawclk(struct drm_device *dev)
 {
@@ -313,44 +309,44 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
                .p2_slow = 7, .p2_fast = 7 },
 };
-static const intel_limit_t intel_limits_vlv_dac = {
+static const intel_limit_t intel_limits_vlv = {
-        .dot = { .min = 25000, .max = 270000 },
+         /*
-        .vco = { .min = 4000000, .max = 6000000 },
+          * These are the data rate limits (measured in fast clocks)
-        .n = { .min = 1, .max = 7 },
+          * since those are the strictest limits we have. The fast
-        .m = { .min = 22, .max = 450 }, /* guess */
+          * clock and actual rate limits are more relaxed, so checking
-        .m1 = { .min = 2, .max = 3 },
+          * them would make no difference.
-        .m2 = { .min = 11, .max = 156 },
+          */
-        .p = { .min = 10, .max = 30 },
+        .dot = { .min = 25000 * 5, .max = 270000 * 5 },
-        .p1 = { .min = 1, .max = 3 },
-        .p2 = { .dot_limit = 270000,
-                .p2_slow = 2, .p2_fast = 20 },
-};
-static const intel_limit_t intel_limits_vlv_hdmi = {
-        .dot = { .min = 25000, .max = 270000 },
        .vco = { .min = 4000000, .max = 6000000 },
        .n = { .min = 1, .max = 7 },
-        .m = { .min = 60, .max = 300 }, /* guess */
        .m1 = { .min = 2, .max = 3 },
        .m2 = { .min = 11, .max = 156 },
-        .p = { .min = 10, .max = 30 },
        .p1 = { .min = 2, .max = 3 },
-        .p2 = { .dot_limit = 270000,
+        .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
-                .p2_slow = 2, .p2_fast = 20 },
 };
-static const intel_limit_t intel_limits_vlv_dp = {
+static void vlv_clock(int refclk, intel_clock_t *clock)
-        .dot = { .min = 25000, .max = 270000 },
+{
-        .vco = { .min = 4000000, .max = 6000000 },
+        clock->m = clock->m1 * clock->m2;
-        .n = { .min = 1, .max = 7 },
+        clock->p = clock->p1 * clock->p2;
-        .m = { .min = 22, .max = 450 },
+        clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
-        .m1 = { .min = 2, .max = 3 },
+        clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
-        .m2 = { .min = 11, .max = 156 },
+}
-        .p = { .min = 10, .max = 30 },
-        .p1 = { .min = 1, .max = 3 },
+/**
-        .p2 = { .dot_limit = 270000,
+ * Returns whether any output on the specified pipe is of the specified type
-                .p2_slow = 2, .p2_fast = 20 },
+ */
-};
+static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
+{
+        struct drm_device *dev = crtc->dev;
+        struct intel_encoder *encoder;
+        for_each_encoder_on_crtc(dev, crtc, encoder)
+                if (encoder->type == type)
+                        return true;
+        return false;
+}
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
                                                int refclk)
@@ -412,12 +408,7 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
                else
                        limit = &intel_limits_pineview_sdvo;
        } else if (IS_VALLEYVIEW(dev)) {
-                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
+                limit = &intel_limits_vlv;
-                        limit = &intel_limits_vlv_dac;
-                else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
-                        limit = &intel_limits_vlv_hdmi;
-                else
-                        limit = &intel_limits_vlv_dp;
        } else if (!IS_GEN2(dev)) {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
                        limit = &intel_limits_i9xx_lvds;
@@ -439,8 +430,8 @@ static void pineview_clock(int refclk, intel_clock_t *clock)
 {
        clock->m = clock->m2 + 2;
        clock->p = clock->p1 * clock->p2;
-        clock->vco = refclk * clock->m / clock->n;
+        clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
-        clock->dot = clock->vco / clock->p;
+        clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 }
 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
@@ -452,23 +443,8 @@ static void i9xx_clock(int refclk, intel_clock_t *clock)
 {
        clock->m = i9xx_dpll_compute_m(clock);
        clock->p = clock->p1 * clock->p2;
-        clock->vco = refclk * clock->m / (clock->n + 2);
+        clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
-        clock->dot = clock->vco / clock->p;
+        clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
-}
-/**
- * Returns whether any output on the specified pipe is of the specified type
- */
-bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
-{
-        struct drm_device *dev = crtc->dev;
-        struct intel_encoder *encoder;
-        for_each_encoder_on_crtc(dev, crtc, encoder)
-                if (encoder->type == type)
-                        return true;
-        return false;
 }
 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
@@ -481,20 +457,26 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
                               const intel_limit_t *limit,
                               const intel_clock_t *clock)
 {
+        if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
+                INTELPllInvalid("n out of range\n");
        if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
                INTELPllInvalid("p1 out of range\n");
-        if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
-                INTELPllInvalid("p out of range\n");
        if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
                INTELPllInvalid("m2 out of range\n");
        if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
                INTELPllInvalid("m1 out of range\n");
-        if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
-                INTELPllInvalid("m1 <= m2\n");
+        if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
-        if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
+                if (clock->m1 <= clock->m2)
-                INTELPllInvalid("m out of range\n");
+                        INTELPllInvalid("m1 <= m2\n");
-        if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
-                INTELPllInvalid("n out of range\n");
+        if (!IS_VALLEYVIEW(dev)) {
+                if (clock->p < limit->p.min || limit->p.max < clock->p)
+                        INTELPllInvalid("p out of range\n");
+                if (clock->m < limit->m.min || limit->m.max < clock->m)
+                        INTELPllInvalid("m out of range\n");
+        }
        if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
                INTELPllInvalid("vco out of range\n");
        /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
@@ -688,67 +670,73 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
                   int target, int refclk, intel_clock_t *match_clock,
                   intel_clock_t *best_clock)
 {
-        u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
+        struct drm_device *dev = crtc->dev;
-        u32 m, n, fastclk;
+        intel_clock_t clock;
-        u32 updrate, minupdate, p;
+        unsigned int bestppm = 1000000;
-        unsigned long bestppm, ppm, absppm;
+        /* min update 19.2 MHz */
-        int dotclk, flag;
+        int max_n = min(limit->n.max, refclk / 19200);
+        bool found = false;
-        flag = 0;
-        dotclk = target * 1000;
+        target *= 5; /* fast clock */
-        bestppm = 1000000;
-        ppm = absppm = 0;
+        memset(best_clock, 0, sizeof(*best_clock));
-        fastclk = dotclk / (2*100);
-        updrate = 0;
-        minupdate = 19200;
-        n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
-        bestm1 = bestm2 = bestp1 = bestp2 = 0;
        /* based on hardware requirement, prefer smaller n to precision */
-        for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
+        for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
-                updrate = refclk / n;
+                for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
-                for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
+                        for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
-                        for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
+                             clock.p2 -= clock.p2 > 10 ? 2 : 1) {
-                                if (p2 > 10)
+                                clock.p = clock.p1 * clock.p2;
-                                        p2 = p2 - 1;
-                                p = p1 * p2;
                                /* based on hardware requirement, prefer bigger m1,m2 values */
-                                for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
+                                for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
-                                        m2 = (((2*(fastclk * p * n / m1 )) +
+                                        unsigned int ppm, diff;
-                                               refclk) / (2*refclk));
-                                        m = m1 * m2;
+                                        clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
-                                        vco = updrate * m;
+                                                                     refclk * clock.m1);
-                                        if (vco >= limit->vco.min && vco < limit->vco.max) {
-                                                ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
+                                        vlv_clock(refclk, &clock);
-                                                absppm = (ppm > 0) ? ppm : (-ppm);
-                                                if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
+                                        if (!intel_PLL_is_valid(dev, limit,
-                                                        bestppm = 0;
+                                                                &clock))
-                                                        flag = 1;
+                                                continue;
-                                                }
-                                                if (absppm < bestppm - 10) {
+                                        diff = abs(clock.dot - target);
-                                                        bestppm = absppm;
+                                        ppm = div_u64(1000000ULL * diff, target);
-                                                        flag = 1;
-                                                }
+                                        if (ppm < 100 && clock.p > best_clock->p) {
-                                                if (flag) {
+                                                bestppm = 0;
-                                                        bestn = n;
+                                                *best_clock = clock;
-                                                        bestm1 = m1;
+                                                found = true;
-                                                        bestm2 = m2;
+                                        }
-                                                        bestp1 = p1;
-                                                        bestp2 = p2;
+                                        if (bestppm >= 10 && ppm < bestppm - 10) {
-                                                        flag = 0;
+                                                bestppm = ppm;
-                                                }
+                                                *best_clock = clock;
+                                                found = true;
                                        }
                                }
                        }
                }
        }
-        best_clock->n = bestn;
-        best_clock->m1 = bestm1;
-        best_clock->m2 = bestm2;
-        best_clock->p1 = bestp1;
-        best_clock->p2 = bestp2;
-        return true;
+        return found;
+}
+bool intel_crtc_active(struct drm_crtc *crtc)
+{
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        /* Be paranoid as we can arrive here with only partial
+         * state retrieved from the hardware during setup.
+         *
+         * We can ditch the adjusted_mode.crtc_clock check as soon
+         * as Haswell has gained clock readout/fastboot support.
+         *
+         * We can ditch the crtc->fb check as soon as we can
+         * properly reconstruct framebuffers.
+         */
+        return intel_crtc->active && crtc->fb &&
+                intel_crtc->config.adjusted_mode.crtc_clock;
 }
 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
@@ -812,6 +800,25 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
                DRM_DEBUG_KMS("vblank wait timed out\n");
 }
+static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 reg = PIPEDSL(pipe);
+        u32 line1, line2;
+        u32 line_mask;
+        if (IS_GEN2(dev))
+                line_mask = DSL_LINEMASK_GEN2;
+        else
+                line_mask = DSL_LINEMASK_GEN3;
+        line1 = I915_READ(reg) & line_mask;
+        mdelay(5);
+        line2 = I915_READ(reg) & line_mask;
+        return line1 == line2;
+}
 /*
 * intel_wait_for_pipe_off - wait for pipe to turn off
 * @dev: drm device
@@ -843,22 +850,8 @@ void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
                             100))
                        WARN(1, "pipe_off wait timed out\n");
        } else {
-                u32 last_line, line_mask;
-                int reg = PIPEDSL(pipe);
-                unsigned long timeout = jiffies + msecs_to_jiffies(100);
-                if (IS_GEN2(dev))
-                        line_mask = DSL_LINEMASK_GEN2;
-                else
-                        line_mask = DSL_LINEMASK_GEN3;
                /* Wait for the display line to settle */
-                do {
+                if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
-                        last_line = I915_READ(reg) & line_mask;
-                        mdelay(5);
-                } while (((I915_READ(reg) & line_mask) != last_line) &&
-                         time_after(timeout, jiffies));
-                if (time_after(jiffies, timeout))
                        WARN(1, "pipe_off wait timed out\n");
        }
 }
@@ -929,6 +922,24 @@ void assert_pll(struct drm_i915_private *dev_priv,
             state_string(state), state_string(cur_state));
 }
+/* XXX: the dsi pll is shared between MIPI DSI ports */
+static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
+{
+        u32 val;
+        bool cur_state;
+        mutex_lock(&dev_priv->dpio_lock);
+        val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
+        mutex_unlock(&dev_priv->dpio_lock);
+        cur_state = val & DSI_PLL_VCO_EN;
+        WARN(cur_state != state,
+             "DSI PLL state assertion failure (expected %s, current %s)\n",
+             state_string(state), state_string(cur_state));
+}
+#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
+#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 struct intel_shared_dpll *
 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 {
@@ -1069,6 +1080,26 @@ static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
             pipe_name(pipe));
 }
+static void assert_cursor(struct drm_i915_private *dev_priv,
+                          enum pipe pipe, bool state)
+{
+        struct drm_device *dev = dev_priv->dev;
+        bool cur_state;
+        if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+                cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
+        else if (IS_845G(dev) || IS_I865G(dev))
+                cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
+        else
+                cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
+        WARN(cur_state != state,
+             "cursor on pipe %c assertion failure (expected %s, current %s)\n",
+             pipe_name(pipe), state_string(state), state_string(cur_state));
+}
+#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
+#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
 void assert_pipe(struct drm_i915_private *dev_priv,
                 enum pipe pipe, bool state)
 {
@@ -1323,6 +1354,26 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
        assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
 }
+static void intel_init_dpio(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        if (!IS_VALLEYVIEW(dev))
+                return;
+        /*
+         * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
+         *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
+         *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
+         *   b. The other bits such as sfr settings / modesel may all be set
+         *      to 0.
+         *
+         * This should only be done on init and resume from S3 with both
+         * PLLs disabled, or we risk losing DPIO and PLL synchronization.
+         */
+        I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
+}
 static void vlv_enable_pll(struct intel_crtc *crtc)
 {
        struct drm_device *dev = crtc->base.dev;
@@ -1429,6 +1480,20 @@ static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
        POSTING_READ(DPLL(pipe));
 }
+static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
+        u32 val = 0;
+        /* Make sure the pipe isn't still relying on us */
+        assert_pipe_disabled(dev_priv, pipe);
+        /* Leave integrated clock source enabled */
+        if (pipe == PIPE_B)
+                val = DPLL_INTEGRATED_CRI_CLK_VLV;
+        I915_WRITE(DPLL(pipe), val);
+        POSTING_READ(DPLL(pipe));
+}
 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
 {
        u32 port_mask;
@@ -1661,7 +1726,7 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
 * returning.
 */
 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
-                              bool pch_port)
+                              bool pch_port, bool dsi)
 {
        enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
                                                                      pipe);
@@ -1670,6 +1735,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
        u32 val;
        assert_planes_disabled(dev_priv, pipe);
+        assert_cursor_disabled(dev_priv, pipe);
        assert_sprites_disabled(dev_priv, pipe);
        if (HAS_PCH_LPT(dev_priv->dev))
@@ -1683,7 +1749,10 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
         * need the check.
         */
        if (!HAS_PCH_SPLIT(dev_priv->dev))
-                assert_pll_enabled(dev_priv, pipe);
+                if (dsi)
+                        assert_dsi_pll_enabled(dev_priv);
+                else
+                        assert_pll_enabled(dev_priv, pipe);
        else {
                if (pch_port) {
                        /* if driving the PCH, we need FDI enabled */
@@ -1728,6 +1797,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
         * or we might hang the display.
         */
        assert_planes_disabled(dev_priv, pipe);
+        assert_cursor_disabled(dev_priv, pipe);
        assert_sprites_disabled(dev_priv, pipe);
        /* Don't disable pipe A or pipe A PLLs if needed */
@@ -1747,63 +1817,75 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 * Plane regs are double buffered, going from enabled->disabled needs a
 * trigger in order to latch.  The display address reg provides this.
 */
-void intel_flush_display_plane(struct drm_i915_private *dev_priv,
+void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
-                                      enum plane plane)
+                               enum plane plane)
 {
-        if (dev_priv->info->gen >= 4)
+        u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
-                I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
-        else
+        I915_WRITE(reg, I915_READ(reg));
-                I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
+        POSTING_READ(reg);
 }
 /**
- * intel_enable_plane - enable a display plane on a given pipe
+ * intel_enable_primary_plane - enable the primary plane on a given pipe
 * @dev_priv: i915 private structure
 * @plane: plane to enable
 * @pipe: pipe being fed
 *
 * Enable @plane on @pipe, making sure that @pipe is running first.
 */
-static void intel_enable_plane(struct drm_i915_private *dev_priv,
+static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
-                               enum plane plane, enum pipe pipe)
+                                       enum plane plane, enum pipe pipe)
 {
+        struct intel_crtc *intel_crtc =
+                to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
        int reg;
        u32 val;
        /* If the pipe isn't enabled, we can't pump pixels and may hang */
        assert_pipe_enabled(dev_priv, pipe);
+        WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
+        intel_crtc->primary_enabled = true;
        reg = DSPCNTR(plane);
        val = I915_READ(reg);
        if (val & DISPLAY_PLANE_ENABLE)
                return;
        I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
-        intel_flush_display_plane(dev_priv, plane);
+        intel_flush_primary_plane(dev_priv, plane);
        intel_wait_for_vblank(dev_priv->dev, pipe);
 }
 /**
- * intel_disable_plane - disable a display plane
+ * intel_disable_primary_plane - disable the primary plane
 * @dev_priv: i915 private structure
 * @plane: plane to disable
 * @pipe: pipe consuming the data
 *
 * Disable @plane; should be an independent operation.
 */
-static void intel_disable_plane(struct drm_i915_private *dev_priv,
+static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
-                                enum plane plane, enum pipe pipe)
+                                        enum plane plane, enum pipe pipe)
 {
+        struct intel_crtc *intel_crtc =
+                to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
        int reg;
        u32 val;
+        WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
+        intel_crtc->primary_enabled = false;
        reg = DSPCNTR(plane);
        val = I915_READ(reg);
        if ((val & DISPLAY_PLANE_ENABLE) == 0)
                return;
        I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
-        intel_flush_display_plane(dev_priv, plane);
+        intel_flush_primary_plane(dev_priv, plane);
        intel_wait_for_vblank(dev_priv->dev, pipe);
 }
@@ -1839,10 +1921,7 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
                alignment = 0;
                break;
        case I915_TILING_Y:
-                /* Despite that we check this in framebuffer_init userspace can
+                WARN(1, "Y tiled bo slipped through, driver bug!\n");
-                 * screw us over and change the tiling after the fact. Only
-                 * pinned buffers can't change their tiling. */
-                DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
                return -EINVAL;
        default:
                BUG();
@@ -2077,7 +2156,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
        else
                dspcntr &= ~DISPPLANE_TILED;
-        if (IS_HASWELL(dev))
+        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
                dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
        else
                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
@@ -2097,7 +2176,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
        I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
        I915_MODIFY_DISPBASE(DSPSURF(plane),
                             i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
-        if (IS_HASWELL(dev)) {
+        if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
                I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
        } else {
                I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
@@ -2244,11 +2323,26 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                return ret;
        }
-        /* Update pipe size and adjust fitter if needed */
+        /*
+         * Update pipe size and adjust fitter if needed: the reason for this is
+         * that in compute_mode_changes we check the native mode (not the pfit
+         * mode) to see if we can flip rather than do a full mode set. In the
+         * fastboot case, we'll flip, but if we don't update the pipesrc and
+         * pfit state, we'll end up with a big fb scanned out into the wrong
+         * sized surface.
+         *
+         * To fix this properly, we need to hoist the checks up into
+         * compute_mode_changes (or above), check the actual pfit state and
+         * whether the platform allows pfit disable with pipe active, and only
+         * then update the pipesrc and pfit state, even on the flip path.
+         */
        if (i915_fastboot) {
+                const struct drm_display_mode *adjusted_mode =
+                        &intel_crtc->config.adjusted_mode;
                I915_WRITE(PIPESRC(intel_crtc->pipe),
-                           ((crtc->mode.hdisplay - 1) << 16) |
+                           ((adjusted_mode->crtc_hdisplay - 1) << 16) |
-                           (crtc->mode.vdisplay - 1));
+                           (adjusted_mode->crtc_vdisplay - 1));
                if (!intel_crtc->config.pch_pfit.enabled &&
                    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
                     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
@@ -2873,6 +2967,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
 {
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
+        int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
        u32 divsel, phaseinc, auxdiv, phasedir = 0;
        u32 temp;
@@ -2890,14 +2985,14 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
                        SBI_ICLK);
        /* 20MHz is a corner case which is out of range for the 7-bit divisor */
-        if (crtc->mode.clock == 20000) {
+        if (clock == 20000) {
                auxdiv = 1;
                divsel = 0x41;
                phaseinc = 0x20;
        } else {
                /* The iCLK virtual clock root frequency is in MHz,
-                 * but the crtc->mode.clock in in KHz. To get the divisors,
+                 * but the adjusted_mode->crtc_clock in in KHz. To get the
-                 * it is necessary to divide one by another, so we
+                 * divisors, it is necessary to divide one by another, so we
                 * convert the virtual clock precision to KHz here for higher
                 * precision.
                 */
@@ -2905,7 +3000,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
                u32 iclk_pi_range = 64;
                u32 desired_divisor, msb_divisor_value, pi_value;
-                desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
+                desired_divisor = (iclk_virtual_root_freq / clock);
                msb_divisor_value = desired_divisor / iclk_pi_range;
                pi_value = desired_divisor % iclk_pi_range;
@@ -2921,7 +3016,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
                ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
        DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
-                        crtc->mode.clock,
+                        clock,
                        auxdiv,
                        divsel,
                        phasedir,
@@ -3286,6 +3381,108 @@ static void intel_disable_planes(struct drm_crtc *crtc)
                        intel_plane_disable(&intel_plane->base);
 }
+void hsw_enable_ips(struct intel_crtc *crtc)
+{
+        struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+        if (!crtc->config.ips_enabled)
+                return;
+        /* We can only enable IPS after we enable a plane and wait for a vblank.
+         * We guarantee that the plane is enabled by calling intel_enable_ips
+         * only after intel_enable_plane. And intel_enable_plane already waits
+         * for a vblank, so all we need to do here is to enable the IPS bit. */
+        assert_plane_enabled(dev_priv, crtc->plane);
+        if (IS_BROADWELL(crtc->base.dev)) {
+                mutex_lock(&dev_priv->rps.hw_lock);
+                WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
+                mutex_unlock(&dev_priv->rps.hw_lock);
+                /* Quoting Art Runyan: "its not safe to expect any particular
+                 * value in IPS_CTL bit 31 after enabling IPS through the
+                 * mailbox." Therefore we need to defer waiting on the state
+                 * change.
+                 * TODO: need to fix this for state checker
+                 */
+        } else {
+                I915_WRITE(IPS_CTL, IPS_ENABLE);
+                /* The bit only becomes 1 in the next vblank, so this wait here
+                 * is essentially intel_wait_for_vblank. If we don't have this
+                 * and don't wait for vblanks until the end of crtc_enable, then
+                 * the HW state readout code will complain that the expected
+                 * IPS_CTL value is not the one we read. */
+                if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
+                        DRM_ERROR("Timed out waiting for IPS enable\n");
+        }
+}
+void hsw_disable_ips(struct intel_crtc *crtc)
+{
+        struct drm_device *dev = crtc->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        if (!crtc->config.ips_enabled)
+                return;
+        assert_plane_enabled(dev_priv, crtc->plane);
+        if (IS_BROADWELL(crtc->base.dev)) {
+                mutex_lock(&dev_priv->rps.hw_lock);
+                WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
+                mutex_unlock(&dev_priv->rps.hw_lock);
+        } else
+                I915_WRITE(IPS_CTL, 0);
+        POSTING_READ(IPS_CTL);
+        /* We need to wait for a vblank before we can disable the plane. */
+        intel_wait_for_vblank(dev, crtc->pipe);
+}
+/** Loads the palette/gamma unit for the CRTC with the prepared values */
+static void intel_crtc_load_lut(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        enum pipe pipe = intel_crtc->pipe;
+        int palreg = PALETTE(pipe);
+        int i;
+        bool reenable_ips = false;
+        /* The clocks have to be on to load the palette. */
+        if (!crtc->enabled || !intel_crtc->active)
+                return;
+        if (!HAS_PCH_SPLIT(dev_priv->dev)) {
+                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
+                        assert_dsi_pll_enabled(dev_priv);
+                else
+                        assert_pll_enabled(dev_priv, pipe);
+        }
+        /* use legacy palette for Ironlake */
+        if (HAS_PCH_SPLIT(dev))
+                palreg = LGC_PALETTE(pipe);
+        /* Workaround : Do not read or write the pipe palette/gamma data while
+         * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
+         */
+        if (intel_crtc->config.ips_enabled &&
+            ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
+             GAMMA_MODE_MODE_SPLIT)) {
+                hsw_disable_ips(intel_crtc);
+                reenable_ips = true;
+        }
+        for (i = 0; i < 256; i++) {
+                I915_WRITE(palreg + 4 * i,
+                           (intel_crtc->lut_r[i] << 16) |
+                           (intel_crtc->lut_g[i] << 8) |
+                           intel_crtc->lut_b[i]);
+        }
+        if (reenable_ips)
+                hsw_enable_ips(intel_crtc);
+}
 static void ironlake_crtc_enable(struct drm_crtc *crtc)
 {
        struct drm_device *dev = crtc->dev;
@@ -3305,8 +3502,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
        intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
        intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
-        intel_update_watermarks(dev);
        for_each_encoder_on_crtc(dev, crtc, encoder)
                if (encoder->pre_enable)
                        encoder->pre_enable(encoder);
@@ -3329,9 +3524,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
         */
        intel_crtc_load_lut(crtc);
+        intel_update_watermarks(crtc);
        intel_enable_pipe(dev_priv, pipe,
-                          intel_crtc->config.has_pch_encoder);
+                          intel_crtc->config.has_pch_encoder, false);
-        intel_enable_plane(dev_priv, plane, pipe);
+        intel_enable_primary_plane(dev_priv, plane, pipe);
        intel_enable_planes(crtc);
        intel_crtc_update_cursor(crtc, true);
@@ -3365,34 +3561,74 @@ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
        return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
 }
-static void hsw_enable_ips(struct intel_crtc *crtc)
+static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
 {
-        struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+        struct drm_device *dev = crtc->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        int pipe = intel_crtc->pipe;
+        int plane = intel_crtc->plane;
-        if (!crtc->config.ips_enabled)
+        intel_enable_primary_plane(dev_priv, plane, pipe);
-                return;
+        intel_enable_planes(crtc);
+        intel_crtc_update_cursor(crtc, true);
-        /* We can only enable IPS after we enable a plane and wait for a vblank.
+        hsw_enable_ips(intel_crtc);
-         * We guarantee that the plane is enabled by calling intel_enable_ips
-         * only after intel_enable_plane. And intel_enable_plane already waits
+        mutex_lock(&dev->struct_mutex);
-         * for a vblank, so all we need to do here is to enable the IPS bit. */
+        intel_update_fbc(dev);
-        assert_plane_enabled(dev_priv, crtc->plane);
+        mutex_unlock(&dev->struct_mutex);
-        I915_WRITE(IPS_CTL, IPS_ENABLE);
 }
-static void hsw_disable_ips(struct intel_crtc *crtc)
+static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
 {
-        struct drm_device *dev = crtc->base.dev;
+        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        int pipe = intel_crtc->pipe;
+        int plane = intel_crtc->plane;
-        if (!crtc->config.ips_enabled)
+        intel_crtc_wait_for_pending_flips(crtc);
-                return;
+        drm_vblank_off(dev, pipe);
-        assert_plane_enabled(dev_priv, crtc->plane);
+        /* FBC must be disabled before disabling the plane on HSW. */
-        I915_WRITE(IPS_CTL, 0);
+        if (dev_priv->fbc.plane == plane)
+                intel_disable_fbc(dev);
-        /* We need to wait for a vblank before we can disable the plane. */
+        hsw_disable_ips(intel_crtc);
-        intel_wait_for_vblank(dev, crtc->pipe);
+        intel_crtc_update_cursor(crtc, false);
+        intel_disable_planes(crtc);
+        intel_disable_primary_plane(dev_priv, plane, pipe);
+}
+/*
+ * This implements the workaround described in the "notes" section of the mode
+ * set sequence documentation. When going from no pipes or single pipe to
+ * multiple pipes, and planes are enabled after the pipe, we need to wait at
+ * least 2 vblanks on the first pipe before enabling planes on the second pipe.
+ */
+static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
+{
+        struct drm_device *dev = crtc->base.dev;
+        struct intel_crtc *crtc_it, *other_active_crtc = NULL;
+        /* We want to get the other_active_crtc only if there's only 1 other
+         * active crtc. */
+        list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
+                if (!crtc_it->active || crtc_it == crtc)
+                        continue;
+                if (other_active_crtc)
+                        return;
+                other_active_crtc = crtc_it;
+        }
+        if (!other_active_crtc)
+                return;
+        intel_wait_for_vblank(dev, other_active_crtc->pipe);
+        intel_wait_for_vblank(dev, other_active_crtc->pipe);
 }
 static void haswell_crtc_enable(struct drm_crtc *crtc)
@@ -3402,7 +3638,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        struct intel_encoder *encoder;
        int pipe = intel_crtc->pipe;
-        int plane = intel_crtc->plane;
        WARN_ON(!crtc->enabled);
@@ -3415,8 +3650,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
        if (intel_crtc->config.has_pch_encoder)
                intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
-        intel_update_watermarks(dev);
        if (intel_crtc->config.has_pch_encoder)
                dev_priv->display.fdi_link_train(crtc);
@@ -3437,23 +3670,22 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
        intel_ddi_set_pipe_settings(crtc);
        intel_ddi_enable_transcoder_func(crtc);
+        intel_update_watermarks(crtc);
        intel_enable_pipe(dev_priv, pipe,
-                          intel_crtc->config.has_pch_encoder);
+                          intel_crtc->config.has_pch_encoder, false);
-        intel_enable_plane(dev_priv, plane, pipe);
-        intel_enable_planes(crtc);
-        intel_crtc_update_cursor(crtc, true);
-        hsw_enable_ips(intel_crtc);
        if (intel_crtc->config.has_pch_encoder)
                lpt_pch_enable(crtc);
-        mutex_lock(&dev->struct_mutex);
+        for_each_encoder_on_crtc(dev, crtc, encoder) {
-        intel_update_fbc(dev);
-        mutex_unlock(&dev->struct_mutex);
-        for_each_encoder_on_crtc(dev, crtc, encoder)
                encoder->enable(encoder);
+                intel_opregion_notify_encoder(encoder, true);
+        }
+        /* If we change the relative order between pipe/planes enabling, we need
+         * to change the workaround. */
+        haswell_mode_set_planes_workaround(intel_crtc);
+        haswell_crtc_enable_planes(crtc);
        /*
         * There seems to be a race in PCH platform hw (at least on some
@@ -3506,7 +3738,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
        intel_crtc_update_cursor(crtc, false);
        intel_disable_planes(crtc);
-        intel_disable_plane(dev_priv, plane, pipe);
+        intel_disable_primary_plane(dev_priv, plane, pipe);
        if (intel_crtc->config.has_pch_encoder)
                intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
@@ -3547,7 +3779,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
        }
        intel_crtc->active = false;
-        intel_update_watermarks(dev);
+        intel_update_watermarks(crtc);
        mutex_lock(&dev->struct_mutex);
        intel_update_fbc(dev);
@@ -3561,27 +3793,17 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        struct intel_encoder *encoder;
        int pipe = intel_crtc->pipe;
-        int plane = intel_crtc->plane;
        enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
        if (!intel_crtc->active)
                return;
-        for_each_encoder_on_crtc(dev, crtc, encoder)
+        haswell_crtc_disable_planes(crtc);
-                encoder->disable(encoder);
-        intel_crtc_wait_for_pending_flips(crtc);
-        drm_vblank_off(dev, pipe);
-        /* FBC must be disabled before disabling the plane on HSW. */
+        for_each_encoder_on_crtc(dev, crtc, encoder) {
-        if (dev_priv->fbc.plane == plane)
+                intel_opregion_notify_encoder(encoder, false);
-                intel_disable_fbc(dev);
+                encoder->disable(encoder);
+        }
-        hsw_disable_ips(intel_crtc);
-        intel_crtc_update_cursor(crtc, false);
-        intel_disable_planes(crtc);
-        intel_disable_plane(dev_priv, plane, pipe);
        if (intel_crtc->config.has_pch_encoder)
                intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
@@ -3604,7 +3826,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
        }
        intel_crtc->active = false;
-        intel_update_watermarks(dev);
+        intel_update_watermarks(crtc);
        mutex_lock(&dev->struct_mutex);
        intel_update_fbc(dev);
@@ -3696,6 +3918,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
        struct intel_encoder *encoder;
        int pipe = intel_crtc->pipe;
        int plane = intel_crtc->plane;
+        bool is_dsi;
        WARN_ON(!crtc->enabled);
@@ -3703,13 +3926,15 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
                return;
        intel_crtc->active = true;
-        intel_update_watermarks(dev);
        for_each_encoder_on_crtc(dev, crtc, encoder)
                if (encoder->pre_pll_enable)
                        encoder->pre_pll_enable(encoder);
-        vlv_enable_pll(intel_crtc);
+        is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
+        if (!is_dsi)
+                vlv_enable_pll(intel_crtc);
        for_each_encoder_on_crtc(dev, crtc, encoder)
                if (encoder->pre_enable)
@@ -3719,8 +3944,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
        intel_crtc_load_lut(crtc);
-        intel_enable_pipe(dev_priv, pipe, false);
+        intel_update_watermarks(crtc);
-        intel_enable_plane(dev_priv, plane, pipe);
+        intel_enable_pipe(dev_priv, pipe, false, is_dsi);
+        intel_enable_primary_plane(dev_priv, plane, pipe);
        intel_enable_planes(crtc);
        intel_crtc_update_cursor(crtc, true);
@@ -3745,7 +3971,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
                return;
        intel_crtc->active = true;
-        intel_update_watermarks(dev);
        for_each_encoder_on_crtc(dev, crtc, encoder)
                if (encoder->pre_enable)
@@ -3757,8 +3982,9 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
        intel_crtc_load_lut(crtc);
-        intel_enable_pipe(dev_priv, pipe, false);
+        intel_update_watermarks(crtc);
-        intel_enable_plane(dev_priv, plane, pipe);
+        intel_enable_pipe(dev_priv, pipe, false, false);
+        intel_enable_primary_plane(dev_priv, plane, pipe);
        intel_enable_planes(crtc);
        /* The fixup needs to happen before cursor is enabled */
        if (IS_G4X(dev))
@@ -3814,7 +4040,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
        intel_crtc_dpms_overlay(intel_crtc, false);
        intel_crtc_update_cursor(crtc, false);
        intel_disable_planes(crtc);
-        intel_disable_plane(dev_priv, plane, pipe);
+        intel_disable_primary_plane(dev_priv, plane, pipe);
        intel_disable_pipe(dev_priv, pipe);
@@ -3824,11 +4050,15 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
                if (encoder->post_disable)
                        encoder->post_disable(encoder);
-        i9xx_disable_pll(dev_priv, pipe);
+        if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
+                vlv_disable_pll(dev_priv, pipe);
+        else if (!IS_VALLEYVIEW(dev))
+                i9xx_disable_pll(dev_priv, pipe);
        intel_crtc->active = false;
+        intel_update_watermarks(crtc);
        intel_update_fbc(dev);
-        intel_update_watermarks(dev);
 }
 static void i9xx_crtc_off(struct drm_crtc *crtc)
@@ -3902,6 +4132,7 @@ static void intel_crtc_disable(struct drm_crtc *crtc)
        dev_priv->display.off(crtc);
        assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
+        assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
        assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
        if (crtc->fb) {
@@ -4029,7 +4260,7 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
                return false;
        }
-        if (IS_HASWELL(dev)) {
+        if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
                if (pipe_config->fdi_lanes > 2) {
                        DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
                                      pipe_config->fdi_lanes);
@@ -4091,8 +4322,7 @@ retry:
         */
        link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
-        fdi_dotclock = adjusted_mode->clock;
+        fdi_dotclock = adjusted_mode->crtc_clock;
-        fdi_dotclock /= pipe_config->pixel_multiplier;
        lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
                                           pipe_config->pipe_bpp);
@@ -4134,13 +4364,39 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
        struct drm_device *dev = crtc->base.dev;
        struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
-        if (HAS_PCH_SPLIT(dev)) {
+        /* FIXME should check pixel clock limits on all platforms */
-                /* FDI link clock is fixed at 2.7G */
+        if (INTEL_INFO(dev)->gen < 4) {
-                if (pipe_config->requested_mode.clock * 3
+                struct drm_i915_private *dev_priv = dev->dev_private;
-                    > IRONLAKE_FDI_FREQ * 4)
+                int clock_limit =
+                        dev_priv->display.get_display_clock_speed(dev);
+                /*
+                 * Enable pixel doubling when the dot clock
+                 * is > 90% of the (display) core speed.
+                 *
+                 * GDG double wide on either pipe,
+                 * otherwise pipe A only.
+                 */
+                if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
+                    adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
+                        clock_limit *= 2;
+                        pipe_config->double_wide = true;
+                }
+                if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
                        return -EINVAL;
        }
+        /*
+         * Pipe horizontal size must be even in:
+         * - DVO ganged mode
+         * - LVDS dual channel mode
+         * - Double wide pipe
+         */
+        if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
+             intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
+                pipe_config->pipe_src_w &= ~1;
        /* Cantiga+ cannot handle modes with a hsync front porch of 0.
         * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
         */
@@ -4304,28 +4560,6 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
                && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
 }
-static int vlv_get_refclk(struct drm_crtc *crtc)
-{
-        struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        int refclk = 27000; /* for DP & HDMI */
-        return 100000; /* only one validated so far */
-        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
-                refclk = 96000;
-        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-                if (intel_panel_use_ssc(dev_priv))
-                        refclk = 100000;
-                else
-                        refclk = 96000;
-        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
-                refclk = 100000;
-        }
-        return refclk;
-}
 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
 {
        struct drm_device *dev = crtc->dev;
@@ -4333,7 +4567,7 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
        int refclk;
        if (IS_VALLEYVIEW(dev)) {
-                refclk = vlv_get_refclk(crtc);
+                refclk = 100000;
        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
            intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
                refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
@@ -4391,7 +4625,8 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
        }
 }
-static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
+static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
+                pipe)
 {
        u32 reg_val;
@@ -4399,24 +4634,24 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
         * PLLB opamp always calibrates to max value of 0x3f, force enable it
         * and set it to a reasonable value instead.
         */
-        reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
+        reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
        reg_val &= 0xffffff00;
        reg_val |= 0x00000030;
-        vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
-        reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
+        reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
        reg_val &= 0x8cffffff;
        reg_val = 0x8c000000;
-        vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
-        reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
+        reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
        reg_val &= 0xffffff00;
-        vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
-        reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
+        reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
        reg_val &= 0x00ffffff;
        reg_val |= 0xb0000000;
-        vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
 }
 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
@@ -4482,18 +4717,18 @@ static void vlv_update_pll(struct intel_crtc *crtc)
        /* PLL B needs special handling */
        if (pipe)
-                vlv_pllb_recal_opamp(dev_priv);
+                vlv_pllb_recal_opamp(dev_priv, pipe);
        /* Set up Tx target for periodic Rcomp update */
-        vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
+        vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
        /* Disable target IRef on PLL */
-        reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
+        reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
        reg_val &= 0x00ffffff;
-        vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
        /* Disable fast lock */
-        vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
+        vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
        /* Set idtafcrecal before PLL is enabled */
        mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
@@ -4507,55 +4742,55 @@ static void vlv_update_pll(struct intel_crtc *crtc)
         * Note: don't use the DAC post divider as it seems unstable.
         */
        mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
-        vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
+        vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
        mdiv |= DPIO_ENABLE_CALIBRATION;
-        vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
+        vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
        /* Set HBR and RBR LPF coefficients */
        if (crtc->config.port_clock == 162000 ||
            intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
            intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
-                vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
+                vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
                                 0x009f0003);
        else
-                vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
+                vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
                                 0x00d0000f);
        if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
            intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
                /* Use SSC source */
                if (!pipe)
-                        vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                        vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
                                         0x0df40000);
                else
-                        vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                        vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
                                         0x0df70000);
        } else { /* HDMI or VGA */
                /* Use bend source */
                if (!pipe)
-                        vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                        vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
                                         0x0df70000);
                else
-                        vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                        vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
                                         0x0df40000);
        }
-        coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
+        coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
        coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
        if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
            intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
                coreclk |= 0x01000000;
-        vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
+        vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
-        vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
        /* Enable DPIO clock input */
        dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
                DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
-        if (pipe)
+        /* We should never disable this, set it here for state tracking */
+        if (pipe == PIPE_B)
                dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
        dpll |= DPLL_VCO_ENABLE;
        crtc->config.dpll_hw_state.dpll = dpll;
@@ -4693,7 +4928,6 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
        enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
        struct drm_display_mode *adjusted_mode =
                &intel_crtc->config.adjusted_mode;
-        struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
        uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
        /* We need to be careful not to changed the adjusted mode, for otherwise
@@ -4746,7 +4980,8 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
         * always be the user's requested size.
         */
        I915_WRITE(PIPESRC(pipe),
-                   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
+                   ((intel_crtc->config.pipe_src_w - 1) << 16) |
+                   (intel_crtc->config.pipe_src_h - 1));
 }
 static void intel_get_pipe_timings(struct intel_crtc *crtc,
@@ -4784,8 +5019,11 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
        }
        tmp = I915_READ(PIPESRC(crtc->pipe));
-        pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
+        pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
-        pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
+        pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
+        pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
+        pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
 }
 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
@@ -4805,7 +5043,7 @@ static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
        crtc->mode.flags = pipe_config->adjusted_mode.flags;
-        crtc->mode.clock = pipe_config->adjusted_mode.clock;
+        crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
        crtc->mode.flags |= pipe_config->adjusted_mode.flags;
 }
@@ -4821,17 +5059,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
            I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
                pipeconf |= PIPECONF_ENABLE;
-        if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
+        if (intel_crtc->config.double_wide)
-                /* Enable pixel doubling when the dot clock is > 90% of the (display)
+                pipeconf |= PIPECONF_DOUBLE_WIDE;
-                 * core speed.
-                 *
-                 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
-                 * pipe == 0 check?
-                 */
-                if (intel_crtc->config.requested_mode.clock >
-                    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
-                        pipeconf |= PIPECONF_DOUBLE_WIDE;
-        }
        /* only g4x and later have fancy bpc/dither controls */
        if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
@@ -4885,14 +5114,13 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
        int pipe = intel_crtc->pipe;
        int plane = intel_crtc->plane;
        int refclk, num_connectors = 0;
        intel_clock_t clock, reduced_clock;
        u32 dspcntr;
        bool ok, has_reduced_clock = false;
-        bool is_lvds = false;
+        bool is_lvds = false, is_dsi = false;
        struct intel_encoder *encoder;
        const intel_limit_t *limit;
        int ret;
@@ -4902,42 +5130,49 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
                case INTEL_OUTPUT_LVDS:
                        is_lvds = true;
                        break;
+                case INTEL_OUTPUT_DSI:
+                        is_dsi = true;
+                        break;
                }
                num_connectors++;
        }
-        refclk = i9xx_get_refclk(crtc, num_connectors);
+        if (is_dsi)
+                goto skip_dpll;
-        /*
+        if (!intel_crtc->config.clock_set) {
-         * Returns a set of divisors for the desired target clock with the given
+                refclk = i9xx_get_refclk(crtc, num_connectors);
-         * refclk, or FALSE.  The returned values represent the clock equation:
-         * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
-         */
-        limit = intel_limit(crtc, refclk);
-        ok = dev_priv->display.find_dpll(limit, crtc,
-                                         intel_crtc->config.port_clock,
-                                         refclk, NULL, &clock);
-        if (!ok && !intel_crtc->config.clock_set) {
-                DRM_ERROR("Couldn't find PLL settings for mode!\n");
-                return -EINVAL;
-        }
-        if (is_lvds && dev_priv->lvds_downclock_avail) {
                /*
-                 * Ensure we match the reduced clock's P to the target clock.
+                 * Returns a set of divisors for the desired target clock with
-                 * If the clocks don't match, we can't switch the display clock
+                 * the given refclk, or FALSE.  The returned values represent
-                 * by using the FP0/FP1. In such case we will disable the LVDS
+                 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
-                 * downclock feature.
+                 * 2) / p1 / p2.
-                */
+                 */
-                has_reduced_clock =
+                limit = intel_limit(crtc, refclk);
-                        dev_priv->display.find_dpll(limit, crtc,
+                ok = dev_priv->display.find_dpll(limit, crtc,
-                                                    dev_priv->lvds_downclock,
+                                                 intel_crtc->config.port_clock,
-                                                    refclk, &clock,
+                                                 refclk, NULL, &clock);
-                                                    &reduced_clock);
+                if (!ok) {
-        }
+                        DRM_ERROR("Couldn't find PLL settings for mode!\n");
-        /* Compat-code for transition, will disappear. */
+                        return -EINVAL;
-        if (!intel_crtc->config.clock_set) {
+                }
+                if (is_lvds && dev_priv->lvds_downclock_avail) {
+                        /*
+                         * Ensure we match the reduced clock's P to the target
+                         * clock.  If the clocks don't match, we can't switch
+                         * the display clock by using the FP0/FP1. In such case
+                         * we will disable the LVDS downclock feature.
+                         */
+                        has_reduced_clock =
+                                dev_priv->display.find_dpll(limit, crtc,
+                                                            dev_priv->lvds_downclock,
+                                                            refclk, &clock,
+                                                            &reduced_clock);
+                }
+                /* Compat-code for transition, will disappear. */
                intel_crtc->config.dpll.n = clock.n;
                intel_crtc->config.dpll.m1 = clock.m1;
                intel_crtc->config.dpll.m2 = clock.m2;
@@ -4945,17 +5180,19 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
                intel_crtc->config.dpll.p2 = clock.p2;
        }
-        if (IS_GEN2(dev))
+        if (IS_GEN2(dev)) {
                i8xx_update_pll(intel_crtc,
                                has_reduced_clock ? &reduced_clock : NULL,
                                num_connectors);
-        else if (IS_VALLEYVIEW(dev))
+        } else if (IS_VALLEYVIEW(dev)) {
                vlv_update_pll(intel_crtc);
-        else
+        } else {
                i9xx_update_pll(intel_crtc,
                                has_reduced_clock ? &reduced_clock : NULL,
                                num_connectors);
+        }
+skip_dpll:
        /* Set up the display plane register */
        dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4972,8 +5209,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
         * which should always be the user's requested size.
         */
        I915_WRITE(DSPSIZE(plane),
-                   ((mode->vdisplay - 1) << 16) |
+                   ((intel_crtc->config.pipe_src_h - 1) << 16) |
-                   (mode->hdisplay - 1));
+                   (intel_crtc->config.pipe_src_w - 1));
        I915_WRITE(DSPPOS(plane), 0);
        i9xx_set_pipeconf(intel_crtc);
@@ -4983,8 +5220,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
        ret = intel_pipe_set_base(crtc, x, y, fb);
-        intel_update_watermarks(dev);
        return ret;
 }
@@ -5015,6 +5250,32 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
                        I915_READ(LVDS) & LVDS_BORDER_ENABLE;
 }
+static void vlv_crtc_clock_get(struct intel_crtc *crtc,
+                               struct intel_crtc_config *pipe_config)
+{
+        struct drm_device *dev = crtc->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        int pipe = pipe_config->cpu_transcoder;
+        intel_clock_t clock;
+        u32 mdiv;
+        int refclk = 100000;
+        mutex_lock(&dev_priv->dpio_lock);
+        mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
+        mutex_unlock(&dev_priv->dpio_lock);
+        clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
+        clock.m2 = mdiv & DPIO_M2DIV_MASK;
+        clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
+        clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
+        clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
+        vlv_clock(refclk, &clock);
+        /* clock.dot is the fast clock */
+        pipe_config->port_clock = clock.dot / 5;
+}
 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
                                 struct intel_crtc_config *pipe_config)
 {
@@ -5045,6 +5306,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
                }
        }
+        if (INTEL_INFO(dev)->gen < 4)
+                pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
        intel_get_pipe_timings(crtc, pipe_config);
        i9xx_get_pfit_config(crtc, pipe_config);
@@ -5077,6 +5341,11 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
                                                     DPLL_PORTB_READY_MASK);
        }
+        if (IS_VALLEYVIEW(dev))
+                vlv_crtc_clock_get(crtc, pipe_config);
+        else
+                i9xx_crtc_clock_get(crtc, pipe_config);
        return true;
 }
@@ -5565,14 +5834,16 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
 static void haswell_set_pipeconf(struct drm_crtc *crtc)
 {
-        struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+        struct drm_device *dev = crtc->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        enum pipe pipe = intel_crtc->pipe;
        enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
        uint32_t val;
        val = 0;
-        if (intel_crtc->config.dither)
+        if (IS_HASWELL(dev) && intel_crtc->config.dither)
                val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
        if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
@@ -5585,6 +5856,33 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
        I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
        POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
+        if (IS_BROADWELL(dev)) {
+                val = 0;
+                switch (intel_crtc->config.pipe_bpp) {
+                case 18:
+                        val |= PIPEMISC_DITHER_6_BPC;
+                        break;
+                case 24:
+                        val |= PIPEMISC_DITHER_8_BPC;
+                        break;
+                case 30:
+                        val |= PIPEMISC_DITHER_10_BPC;
+                        break;
+                case 36:
+                        val |= PIPEMISC_DITHER_12_BPC;
+                        break;
+                default:
+                        /* Case prevented by pipe_config_set_bpp. */
+                        BUG();
+                }
+                if (intel_crtc->config.dither)
+                        val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
+                I915_WRITE(PIPEMISC(pipe), val);
+        }
 }
 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
@@ -5819,11 +6117,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
        else
                intel_crtc->lowfreq_avail = false;
-        if (intel_crtc->config.has_pch_encoder) {
-                pll = intel_crtc_to_shared_dpll(intel_crtc);
-        }
        intel_set_pipe_timings(intel_crtc);
        if (intel_crtc->config.has_pch_encoder) {
@@ -5839,25 +6132,67 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
        ret = intel_pipe_set_base(crtc, x, y, fb);
-        intel_update_watermarks(dev);
        return ret;
 }
-static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
+static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
-                                        struct intel_crtc_config *pipe_config)
+                                         struct intel_link_m_n *m_n)
 {
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
-        enum transcoder transcoder = pipe_config->cpu_transcoder;
+        enum pipe pipe = crtc->pipe;
-        pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
+        m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
-        pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
+        m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
-        pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
+        m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
-                                        & ~TU_SIZE_MASK;
+                & ~TU_SIZE_MASK;
-        pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
+        m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
-        pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
+        m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
-                                   & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+}
+static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
+                                         enum transcoder transcoder,
+                                         struct intel_link_m_n *m_n)
+{
+        struct drm_device *dev = crtc->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        enum pipe pipe = crtc->pipe;
+        if (INTEL_INFO(dev)->gen >= 5) {
+                m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
+                m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
+                m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
+                        & ~TU_SIZE_MASK;
+                m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
+                m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
+                            & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+        } else {
+                m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
+                m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
+                m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
+                        & ~TU_SIZE_MASK;
+                m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
+                m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
+                            & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+        }
+}
+void intel_dp_get_m_n(struct intel_crtc *crtc,
+                      struct intel_crtc_config *pipe_config)
+{
+        if (crtc->config.has_pch_encoder)
+                intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
+        else
+                intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
+                                             &pipe_config->dp_m_n);
+}
+static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
+                                        struct intel_crtc_config *pipe_config)
+{
+        intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
+                                     &pipe_config->fdi_m_n);
 }
 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
@@ -5946,6 +6281,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
                pipe_config->pixel_multiplier =
                        ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
                         >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
+                ironlake_pch_clock_get(crtc, pipe_config);
        } else {
                pipe_config->pixel_multiplier = 1;
        }
@@ -6002,8 +6339,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
 * register. Callers should take care of disabling all the display engine
 * functions, doing the mode unset, fixing interrupts, etc.
 */
-void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
+static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
-                       bool switch_to_fclk, bool allow_power_down)
+                              bool switch_to_fclk, bool allow_power_down)
 {
        uint32_t val;
@@ -6031,7 +6368,10 @@ void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
        val = I915_READ(D_COMP);
        val |= D_COMP_COMP_DISABLE;
-        I915_WRITE(D_COMP, val);
+        mutex_lock(&dev_priv->rps.hw_lock);
+        if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
+                DRM_ERROR("Failed to disable D_COMP\n");
+        mutex_unlock(&dev_priv->rps.hw_lock);
        POSTING_READ(D_COMP);
        ndelay(100);
@@ -6050,7 +6390,7 @@ void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
 * source.
 */
-void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
+static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
 {
        uint32_t val;
@@ -6073,7 +6413,10 @@ void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
        val = I915_READ(D_COMP);
        val |= D_COMP_COMP_FORCE;
        val &= ~D_COMP_COMP_DISABLE;
-        I915_WRITE(D_COMP, val);
+        mutex_lock(&dev_priv->rps.hw_lock);
+        if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
+                DRM_ERROR("Failed to enable D_COMP\n");
+        mutex_unlock(&dev_priv->rps.hw_lock);
        POSTING_READ(D_COMP);
        val = I915_READ(LCPLL_CTL);
@@ -6256,22 +6599,79 @@ static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
        }
 }
-static void haswell_modeset_global_resources(struct drm_device *dev)
+#define for_each_power_domain(domain, mask)                             \
+        for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
+                if ((1 << (domain)) & (mask))
+static unsigned long get_pipe_power_domains(struct drm_device *dev,
+                                            enum pipe pipe, bool pfit_enabled)
 {
-        bool enable = false;
+        unsigned long mask;
+        enum transcoder transcoder;
+        transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
+        mask = BIT(POWER_DOMAIN_PIPE(pipe));
+        mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
+        if (pfit_enabled)
+                mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
+        return mask;
+}
+void intel_display_set_init_power(struct drm_device *dev, bool enable)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        if (dev_priv->power_domains.init_power_on == enable)
+                return;
+        if (enable)
+                intel_display_power_get(dev, POWER_DOMAIN_INIT);
+        else
+                intel_display_power_put(dev, POWER_DOMAIN_INIT);
+        dev_priv->power_domains.init_power_on = enable;
+}
+static void modeset_update_power_wells(struct drm_device *dev)
+{
+        unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
        struct intel_crtc *crtc;
+        /*
+         * First get all needed power domains, then put all unneeded, to avoid
+         * any unnecessary toggling of the power wells.
+         */
        list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
+                enum intel_display_power_domain domain;
                if (!crtc->base.enabled)
                        continue;
-                if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
+                pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
-                    crtc->config.cpu_transcoder != TRANSCODER_EDP)
+                                                crtc->pipe,
-                        enable = true;
+                                                crtc->config.pch_pfit.enabled);
+                for_each_power_domain(domain, pipe_domains[crtc->pipe])
+                        intel_display_power_get(dev, domain);
        }
-        intel_set_power_well(dev, enable);
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
+                enum intel_display_power_domain domain;
+                for_each_power_domain(domain, crtc->enabled_power_domains)
+                        intel_display_power_put(dev, domain);
+                crtc->enabled_power_domains = pipe_domains[crtc->pipe];
+        }
+        intel_display_set_init_power(dev, false);
+}
+static void haswell_modeset_global_resources(struct drm_device *dev)
+{
+        modeset_update_power_wells(dev);
        hsw_update_package_c8(dev);
 }
@@ -6310,8 +6710,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
        ret = intel_pipe_set_base(crtc, x, y, fb);
-        intel_update_watermarks(dev);
        return ret;
 }
@@ -6419,6 +6817,44 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        return 0;
 }
+static struct {
+        int clock;
+        u32 config;
+} hdmi_audio_clock[] = {
+        { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
+        { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
+        { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
+        { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
+        { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
+        { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
+        { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
+        { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
+        { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
+        { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
+};
+/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
+static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
+                if (mode->clock == hdmi_audio_clock[i].clock)
+                        break;
+        }
+        if (i == ARRAY_SIZE(hdmi_audio_clock)) {
+                DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
+                i = 1;
+        }
+        DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
+                      hdmi_audio_clock[i].clock,
+                      hdmi_audio_clock[i].config);
+        return hdmi_audio_clock[i].config;
+}
 static bool intel_eld_uptodate(struct drm_connector *connector,
                               int reg_eldv, uint32_t bits_eldv,
                               int reg_elda, uint32_t bits_elda,
@@ -6449,7 +6885,8 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
 }
 static void g4x_write_eld(struct drm_connector *connector,
-                          struct drm_crtc *crtc)
+                          struct drm_crtc *crtc,
+                          struct drm_display_mode *mode)
 {
        struct drm_i915_private *dev_priv = connector->dev->dev_private;
        uint8_t *eld = connector->eld;
@@ -6489,7 +6926,8 @@ static void g4x_write_eld(struct drm_connector *connector,
 }
 static void haswell_write_eld(struct drm_connector *connector,
-                                     struct drm_crtc *crtc)
+                              struct drm_crtc *crtc,
+                              struct drm_display_mode *mode)
 {
        struct drm_i915_private *dev_priv = connector->dev->dev_private;
        uint8_t *eld = connector->eld;
@@ -6542,8 +6980,9 @@ static void haswell_write_eld(struct drm_connector *connector,
                DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
                eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
                I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
-        } else
+        } else {
-                I915_WRITE(aud_config, 0);
+                I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
+        }
        if (intel_eld_uptodate(connector,
                               aud_cntrl_st2, eldv,
@@ -6576,7 +7015,8 @@ static void haswell_write_eld(struct drm_connector *connector,
 }
 static void ironlake_write_eld(struct drm_connector *connector,
-                                     struct drm_crtc *crtc)
+                               struct drm_crtc *crtc,
+                               struct drm_display_mode *mode)
 {
        struct drm_i915_private *dev_priv = connector->dev->dev_private;
        uint8_t *eld = connector->eld;
@@ -6594,6 +7034,11 @@ static void ironlake_write_eld(struct drm_connector *connector,
                aud_config = IBX_AUD_CFG(pipe);
                aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
                aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
+        } else if (IS_VALLEYVIEW(connector->dev)) {
+                hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
+                aud_config = VLV_AUD_CFG(pipe);
+                aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
+                aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
        } else {
                hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
                aud_config = CPT_AUD_CFG(pipe);
@@ -6603,8 +7048,19 @@ static void ironlake_write_eld(struct drm_connector *connector,
        DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
-        i = I915_READ(aud_cntl_st);
+        if (IS_VALLEYVIEW(connector->dev))  {
-        i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
+                struct intel_encoder *intel_encoder;
+                struct intel_digital_port *intel_dig_port;
+                intel_encoder = intel_attached_encoder(connector);
+                intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+                i = intel_dig_port->port;
+        } else {
+                i = I915_READ(aud_cntl_st);
+                i = (i >> 29) & DIP_PORT_SEL_MASK;
+                /* DIP_Port_Select, 0x1 = PortB */
+        }
        if (!i) {
                DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
                /* operate blindly on all ports */
@@ -6620,8 +7076,9 @@ static void ironlake_write_eld(struct drm_connector *connector,
                DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
                eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
                I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
-        } else
+        } else {
-                I915_WRITE(aud_config, 0);
+                I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
+        }
        if (intel_eld_uptodate(connector,
                               aud_cntrl_st2, eldv,
@@ -6671,50 +7128,7 @@ void intel_write_eld(struct drm_encoder *encoder,
        connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
        if (dev_priv->display.write_eld)
-                dev_priv->display.write_eld(connector, crtc);
+                dev_priv->display.write_eld(connector, crtc, mode);
-}
-/** Loads the palette/gamma unit for the CRTC with the prepared values */
-void intel_crtc_load_lut(struct drm_crtc *crtc)
-{
-        struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        enum pipe pipe = intel_crtc->pipe;
-        int palreg = PALETTE(pipe);
-        int i;
-        bool reenable_ips = false;
-        /* The clocks have to be on to load the palette. */
-        if (!crtc->enabled || !intel_crtc->active)
-                return;
-        if (!HAS_PCH_SPLIT(dev_priv->dev))
-                assert_pll_enabled(dev_priv, pipe);
-        /* use legacy palette for Ironlake */
-        if (HAS_PCH_SPLIT(dev))
-                palreg = LGC_PALETTE(pipe);
-        /* Workaround : Do not read or write the pipe palette/gamma data while
-         * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
-         */
-        if (intel_crtc->config.ips_enabled &&
-            ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
-             GAMMA_MODE_MODE_SPLIT)) {
-                hsw_disable_ips(intel_crtc);
-                reenable_ips = true;
-        }
-        for (i = 0; i < 256; i++) {
-                I915_WRITE(palreg + 4 * i,
-                           (intel_crtc->lut_r[i] << 16) |
-                           (intel_crtc->lut_g[i] << 8) |
-                           intel_crtc->lut_b[i]);
-        }
-        if (reenable_ips)
-                hsw_enable_ips(intel_crtc);
 }
 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
@@ -6790,7 +7204,7 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
                        cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
                        cntl |= CURSOR_MODE_DISABLE;
                }
-                if (IS_HASWELL(dev)) {
+                if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
                        cntl |= CURSOR_PIPE_CSC_ENABLE;
                        cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
                }
@@ -6812,23 +7226,20 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
        int pipe = intel_crtc->pipe;
        int x = intel_crtc->cursor_x;
        int y = intel_crtc->cursor_y;
-        u32 base, pos;
+        u32 base = 0, pos = 0;
        bool visible;
-        pos = 0;
+        if (on)
-        if (on && crtc->enabled && crtc->fb) {
                base = intel_crtc->cursor_addr;
-                if (x > (int) crtc->fb->width)
-                        base = 0;
-                if (y > (int) crtc->fb->height)
+        if (x >= intel_crtc->config.pipe_src_w)
-                        base = 0;
+                base = 0;
-        } else
+        if (y >= intel_crtc->config.pipe_src_h)
                base = 0;
        if (x < 0) {
-                if (x + intel_crtc->cursor_width < 0)
+                if (x + intel_crtc->cursor_width <= 0)
                        base = 0;
                pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
@@ -6837,7 +7248,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
        pos |= x << CURSOR_X_SHIFT;
        if (y < 0) {
-                if (y + intel_crtc->cursor_height < 0)
+                if (y + intel_crtc->cursor_height <= 0)
                        base = 0;
                pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
@@ -6849,7 +7260,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
        if (!visible && !intel_crtc->cursor_visible)
                return;
-        if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
+        if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
                I915_WRITE(CURPOS_IVB(pipe), pos);
                ivb_update_cursor(crtc, base);
        } else {
@@ -6980,8 +7391,8 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 {
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        intel_crtc->cursor_x = x;
+        intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
-        intel_crtc->cursor_y = y;
+        intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
        if (intel_crtc->active)
                intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
@@ -6989,27 +7400,6 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
        return 0;
 }
-/** Sets the color ramps on behalf of RandR */
-void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
-                                 u16 blue, int regno)
-{
-        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        intel_crtc->lut_r[regno] = red >> 8;
-        intel_crtc->lut_g[regno] = green >> 8;
-        intel_crtc->lut_b[regno] = blue >> 8;
-}
-void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
-                             u16 *blue, int regno)
-{
-        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        *red = intel_crtc->lut_r[regno] << 8;
-        *green = intel_crtc->lut_g[regno] << 8;
-        *blue = intel_crtc->lut_b[regno] << 8;
-}
 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
                                 u16 *blue, uint32_t start, uint32_t size)
 {
@@ -7045,14 +7435,21 @@ intel_framebuffer_create(struct drm_device *dev,
                return ERR_PTR(-ENOMEM);
        }
+        ret = i915_mutex_lock_interruptible(dev);
+        if (ret)
+                goto err;
        ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
-        if (ret) {
+        mutex_unlock(&dev->struct_mutex);
-                drm_gem_object_unreference_unlocked(&obj->base);
+        if (ret)
-                kfree(intel_fb);
+                goto err;
-                return ERR_PTR(ret);
-        }
        return &intel_fb->base;
+err:
+        drm_gem_object_unreference_unlocked(&obj->base);
+        kfree(intel_fb);
+        return ERR_PTR(ret);
 }
 static u32
@@ -7095,6 +7492,7 @@ static struct drm_framebuffer *
 mode_fits_in_fbdev(struct drm_device *dev,
                   struct drm_display_mode *mode)
 {
+#ifdef CONFIG_DRM_I915_FBDEV
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_i915_gem_object *obj;
        struct drm_framebuffer *fb;
@@ -7115,6 +7513,9 @@ mode_fits_in_fbdev(struct drm_device *dev,
                return NULL;
        return fb;
+#else
+        return NULL;
+#endif
 }
 bool intel_get_load_detect_pipe(struct drm_connector *connector,
@@ -7258,6 +7659,22 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
        mutex_unlock(&crtc->mutex);
 }
+static int i9xx_pll_refclk(struct drm_device *dev,
+                           const struct intel_crtc_config *pipe_config)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 dpll = pipe_config->dpll_hw_state.dpll;
+        if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
+                return dev_priv->vbt.lvds_ssc_freq * 1000;
+        else if (HAS_PCH_SPLIT(dev))
+                return 120000;
+        else if (!IS_GEN2(dev))
+                return 96000;
+        else
+                return 48000;
+}
 /* Returns the clock of the currently programmed mode of the given pipe. */
 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                                struct intel_crtc_config *pipe_config)
@@ -7265,14 +7682,15 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int pipe = pipe_config->cpu_transcoder;
-        u32 dpll = I915_READ(DPLL(pipe));
+        u32 dpll = pipe_config->dpll_hw_state.dpll;
        u32 fp;
        intel_clock_t clock;
+        int refclk = i9xx_pll_refclk(dev, pipe_config);
        if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
-                fp = I915_READ(FP0(pipe));
+                fp = pipe_config->dpll_hw_state.fp0;
        else
-                fp = I915_READ(FP1(pipe));
+                fp = pipe_config->dpll_hw_state.fp1;
        clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
        if (IS_PINEVIEW(dev)) {
@@ -7303,14 +7721,13 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                default:
                        DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
                                  "mode\n", (int)(dpll & DPLL_MODE_MASK));
-                        pipe_config->adjusted_mode.clock = 0;
                        return;
                }
                if (IS_PINEVIEW(dev))
-                        pineview_clock(96000, &clock);
+                        pineview_clock(refclk, &clock);
                else
-                        i9xx_clock(96000, &clock);
+                        i9xx_clock(refclk, &clock);
        } else {
                bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
@@ -7318,13 +7735,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                        clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
                                       DPLL_FPA01_P1_POST_DIV_SHIFT);
                        clock.p2 = 14;
-                        if ((dpll & PLL_REF_INPUT_MASK) ==
-                            PLLB_REF_INPUT_SPREADSPECTRUMIN) {
-                                /* XXX: might not be 66MHz */
-                                i9xx_clock(66000, &clock);
-                        } else
-                                i9xx_clock(48000, &clock);
                } else {
                        if (dpll & PLL_P1_DIVIDE_BY_TWO)
                                clock.p1 = 2;
@@ -7336,59 +7746,55 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                                clock.p2 = 4;
                        else
                                clock.p2 = 2;
-                        i9xx_clock(48000, &clock);
                }
+                i9xx_clock(refclk, &clock);
        }
-        pipe_config->adjusted_mode.clock = clock.dot;
+        /*
+         * This value includes pixel_multiplier. We will use
+         * port_clock to compute adjusted_mode.crtc_clock in the
+         * encoder's get_config() function.
+         */
+        pipe_config->port_clock = clock.dot;
 }
-static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
+int intel_dotclock_calculate(int link_freq,
-                                    struct intel_crtc_config *pipe_config)
+                             const struct intel_link_m_n *m_n)
 {
-        struct drm_device *dev = crtc->base.dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
-        int link_freq, repeat;
-        u64 clock;
-        u32 link_m, link_n;
-        repeat = pipe_config->pixel_multiplier;
        /*
         * The calculation for the data clock is:
-         * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
+         * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
         * But we want to avoid losing precison if possible, so:
-         * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
+         * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
         *
         * and the link clock is simpler:
-         * link_clock = (m * link_clock * repeat) / n
+         * link_clock = (m * link_clock) / n
         */
-        /*
+        if (!m_n->link_n)
-         * We need to get the FDI or DP link clock here to derive
+                return 0;
-         * the M/N dividers.
-         *
-         * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
-         * For DP, it's either 1.62GHz or 2.7GHz.
-         * We do our calculations in 10*MHz since we don't need much precison.
-         */
-        if (pipe_config->has_pch_encoder)
-                link_freq = intel_fdi_link_freq(dev) * 10000;
-        else
-                link_freq = pipe_config->port_clock;
-        link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
+        return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
-        link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
+}
-        if (!link_m || !link_n)
+static void ironlake_pch_clock_get(struct intel_crtc *crtc,
-                return;
+                                   struct intel_crtc_config *pipe_config)
+{
+        struct drm_device *dev = crtc->base.dev;
-        clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
+        /* read out port_clock from the DPLL */
-        do_div(clock, link_n);
+        i9xx_crtc_clock_get(crtc, pipe_config);
-        pipe_config->adjusted_mode.clock = clock;
+        /*
+         * This value does not include pixel_multiplier.
+         * We will check that port_clock and adjusted_mode.crtc_clock
+         * agree once we know their relationship in the encoder's
+         * get_config() function.
+         */
+        pipe_config->adjusted_mode.crtc_clock =
+                intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
+                                         &pipe_config->fdi_m_n);
 }
 /** Returns the currently programmed mode of the given pipe. */
@@ -7404,6 +7810,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
        int hsync = I915_READ(HSYNC(cpu_transcoder));
        int vtot = I915_READ(VTOTAL(cpu_transcoder));
        int vsync = I915_READ(VSYNC(cpu_transcoder));
+        enum pipe pipe = intel_crtc->pipe;
        mode = kzalloc(sizeof(*mode), GFP_KERNEL);
        if (!mode)
@@ -7416,11 +7823,14 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
         * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
         * to use a real value here instead.
         */
-        pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
+        pipe_config.cpu_transcoder = (enum transcoder) pipe;
        pipe_config.pixel_multiplier = 1;
+        pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
+        pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
+        pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
        i9xx_crtc_clock_get(intel_crtc, &pipe_config);
-        mode->clock = pipe_config.adjusted_mode.clock;
+        mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
        mode->hdisplay = (htot & 0xffff) + 1;
        mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
        mode->hsync_start = (hsync & 0xffff) + 1;
@@ -7526,6 +7936,9 @@ void intel_mark_idle(struct drm_device *dev)
                intel_decrease_pllclock(crtc);
        }
+        if (dev_priv->info->gen >= 6)
+                gen6_rps_idle(dev->dev_private);
 }
 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
@@ -7714,7 +8127,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
        intel_ring_emit(ring, 0); /* aux display base address, unused */
        intel_mark_page_flip_active(intel_crtc);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
        return 0;
 err_unpin:
@@ -7756,7 +8169,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
        intel_ring_emit(ring, MI_NOOP);
        intel_mark_page_flip_active(intel_crtc);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
        return 0;
 err_unpin:
@@ -7805,7 +8218,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
        intel_ring_emit(ring, pf | pipesrc);
        intel_mark_page_flip_active(intel_crtc);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
        return 0;
 err_unpin:
@@ -7850,7 +8263,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
        intel_ring_emit(ring, pf | pipesrc);
        intel_mark_page_flip_active(intel_crtc);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
        return 0;
 err_unpin:
@@ -7929,7 +8342,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
        intel_ring_emit(ring, (MI_NOOP));
        intel_mark_page_flip_active(intel_crtc);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
        return 0;
 err_unpin:
@@ -7974,7 +8387,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
             fb->pitches[0] != crtc->fb->pitches[0]))
                return -EINVAL;
-        work = kzalloc(sizeof *work, GFP_KERNEL);
+        work = kzalloc(sizeof(*work), GFP_KERNEL);
        if (work == NULL)
                return -ENOMEM;
@@ -8209,6 +8622,17 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
        return bpp;
 }
+static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
+{
+        DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
+                        "type: 0x%x flags: 0x%x\n",
+                mode->crtc_clock,
+                mode->crtc_hdisplay, mode->crtc_hsync_start,
+                mode->crtc_hsync_end, mode->crtc_htotal,
+                mode->crtc_vdisplay, mode->crtc_vsync_start,
+                mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
+}
 static void intel_dump_pipe_config(struct intel_crtc *crtc,
                                   struct intel_crtc_config *pipe_config,
                                   const char *context)
@@ -8225,10 +8649,19 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
                      pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
                      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
                      pipe_config->fdi_m_n.tu);
+        DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+                      pipe_config->has_dp_encoder,
+                      pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
+                      pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
+                      pipe_config->dp_m_n.tu);
        DRM_DEBUG_KMS("requested mode:\n");
        drm_mode_debug_printmodeline(&pipe_config->requested_mode);
        DRM_DEBUG_KMS("adjusted mode:\n");
        drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
+        intel_dump_crtc_timings(&pipe_config->adjusted_mode);
+        DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
+        DRM_DEBUG_KMS("pipe src size: %dx%d\n",
+                      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
        DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
                      pipe_config->gmch_pfit.control,
                      pipe_config->gmch_pfit.pgm_ratios,
@@ -8238,6 +8671,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
                      pipe_config->pch_pfit.size,
                      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
        DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
+        DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
 }
 static bool check_encoder_cloning(struct drm_crtc *crtc)
@@ -8281,6 +8715,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
        drm_mode_copy(&pipe_config->adjusted_mode, mode);
        drm_mode_copy(&pipe_config->requested_mode, mode);
        pipe_config->cpu_transcoder =
                (enum transcoder) to_intel_crtc(crtc)->pipe;
        pipe_config->shared_dpll = DPLL_ID_PRIVATE;
@@ -8307,13 +8742,25 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
        if (plane_bpp < 0)
                goto fail;
+        /*
+         * Determine the real pipe dimensions. Note that stereo modes can
+         * increase the actual pipe size due to the frame doubling and
+         * insertion of additional space for blanks between the frame. This
+         * is stored in the crtc timings. We use the requested mode to do this
+         * computation to clearly distinguish it from the adjusted mode, which
+         * can be changed by the connectors in the below retry loop.
+         */
+        drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
+        pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
+        pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
 encoder_retry:
        /* Ensure the port clock defaults are reset when retrying. */
        pipe_config->port_clock = 0;
        pipe_config->pixel_multiplier = 1;
        /* Fill in default crtc timings, allow encoders to overwrite them. */
-        drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
+        drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
        /* Pass our mode to the connectors and the CRTC to give them a chance to
         * adjust it according to limitations or connector properties, and also
@@ -8334,7 +8781,8 @@ encoder_retry:
        /* Set default port clock if not overwritten by the encoder. Needs to be
         * done afterwards in case the encoder adjusts the mode. */
        if (!pipe_config->port_clock)
-                pipe_config->port_clock = pipe_config->adjusted_mode.clock;
+                pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
+                        * pipe_config->pixel_multiplier;
        ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
        if (ret < 0) {
@@ -8521,13 +8969,9 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
 }
-static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
+static bool intel_fuzzy_clock_check(int clock1, int clock2)
-                                    struct intel_crtc_config *new)
 {
-        int clock1, clock2, diff;
+        int diff;
-        clock1 = cur->adjusted_mode.clock;
-        clock2 = new->adjusted_mode.clock;
        if (clock1 == clock2)
                return true;
@@ -8581,6 +9025,15 @@ intel_pipe_config_compare(struct drm_device *dev,
                return false; \
        }
+#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
+        if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
+                DRM_ERROR("mismatch in " #name " " \
+                          "(expected %i, found %i)\n", \
+                          current_config->name, \
+                          pipe_config->name); \
+                return false; \
+        }
 #define PIPE_CONF_QUIRK(quirk)  \
        ((current_config->quirks | pipe_config->quirks) & (quirk))
@@ -8594,6 +9047,13 @@ intel_pipe_config_compare(struct drm_device *dev,
        PIPE_CONF_CHECK_I(fdi_m_n.link_n);
        PIPE_CONF_CHECK_I(fdi_m_n.tu);
+        PIPE_CONF_CHECK_I(has_dp_encoder);
+        PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
+        PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
+        PIPE_CONF_CHECK_I(dp_m_n.link_m);
+        PIPE_CONF_CHECK_I(dp_m_n.link_n);
+        PIPE_CONF_CHECK_I(dp_m_n.tu);
        PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
        PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
        PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
@@ -8624,8 +9084,8 @@ intel_pipe_config_compare(struct drm_device *dev,
                                      DRM_MODE_FLAG_NVSYNC);
        }
-        PIPE_CONF_CHECK_I(requested_mode.hdisplay);
+        PIPE_CONF_CHECK_I(pipe_src_w);
-        PIPE_CONF_CHECK_I(requested_mode.vdisplay);
+        PIPE_CONF_CHECK_I(pipe_src_h);
        PIPE_CONF_CHECK_I(gmch_pfit.control);
        /* pfit ratios are autocomputed by the hw on gen4+ */
@@ -8640,6 +9100,8 @@ intel_pipe_config_compare(struct drm_device *dev,
        PIPE_CONF_CHECK_I(ips_enabled);
+        PIPE_CONF_CHECK_I(double_wide);
        PIPE_CONF_CHECK_I(shared_dpll);
        PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
        PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
@@ -8649,20 +9111,17 @@ intel_pipe_config_compare(struct drm_device *dev,
        if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
                PIPE_CONF_CHECK_I(pipe_bpp);
+        if (!IS_HASWELL(dev)) {
+                PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
+                PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
+        }
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_FLAGS
+#undef PIPE_CONF_CHECK_CLOCK_FUZZY
 #undef PIPE_CONF_QUIRK
-        if (!IS_HASWELL(dev)) {
-                if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
-                        DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
-                                  current_config->adjusted_mode.clock,
-                                  pipe_config->adjusted_mode.clock);
-                        return false;
-                }
-        }
        return true;
 }
@@ -8794,9 +9253,6 @@ check_crtc_state(struct drm_device *dev)
                                encoder->get_config(encoder, &pipe_config);
                }
-                if (dev_priv->display.get_clock)
-                        dev_priv->display.get_clock(crtc, &pipe_config);
                WARN(crtc->active != active,
                     "crtc active state doesn't match with hw state "
                     "(expected %i, found %i)\n", crtc->active, active);
@@ -8871,6 +9327,18 @@ intel_modeset_check_state(struct drm_device *dev)
        check_shared_dpll_state(dev);
 }
+void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
+                                     int dotclock)
+{
+        /*
+         * FDI already provided one idea for the dotclock.
+         * Yell if the encoder disagrees.
+         */
+        WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
+             "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
+             pipe_config->adjusted_mode.crtc_clock, dotclock);
+}
 static int __intel_set_mode(struct drm_crtc *crtc,
                            struct drm_display_mode *mode,
                            int x, int y, struct drm_framebuffer *fb)
@@ -8883,7 +9351,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
        unsigned disable_pipes, prepare_pipes, modeset_pipes;
        int ret = 0;
-        saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
+        saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
        if (!saved_mode)
                return -ENOMEM;
        saved_hwmode = saved_mode + 1;
@@ -9422,7 +9890,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
        struct intel_crtc *intel_crtc;
        int i;
-        intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
+        intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
        if (intel_crtc == NULL)
                return;
@@ -9451,6 +9919,18 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
        drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
 }
+enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
+{
+        struct drm_encoder *encoder = connector->base.encoder;
+        WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
+        if (!encoder)
+                return INVALID_PIPE;
+        return to_intel_crtc(encoder->crtc)->pipe;
+}
 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
                                struct drm_file *file)
 {
@@ -9466,7 +9946,7 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
        if (!drmmode_obj) {
                DRM_ERROR("no such CRTC id\n");
-                return -EINVAL;
+                return -ENOENT;
        }
        crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
@@ -9573,7 +10053,13 @@ static void intel_setup_outputs(struct drm_device *dev)
                if (I915_READ(PCH_DP_D) & DP_DETECTED)
                        intel_dp_init(dev, PCH_DP_D, PORT_D);
        } else if (IS_VALLEYVIEW(dev)) {
-                /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
+                if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
+                        intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
+                                        PORT_B);
+                        if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
+                                intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
+                }
                if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
                        intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
                                        PORT_C);
@@ -9582,12 +10068,7 @@ static void intel_setup_outputs(struct drm_device *dev)
                                              PORT_C);
                }
-                if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
+                intel_dsi_init(dev);
-                        intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
-                                        PORT_B);
-                        if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
-                                intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
-                }
        } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
                bool found = false;
@@ -9643,6 +10124,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 void intel_framebuffer_fini(struct intel_framebuffer *fb)
 {
        drm_framebuffer_cleanup(&fb->base);
+        WARN_ON(!fb->obj->framebuffer_references--);
        drm_gem_object_unreference_unlocked(&fb->obj->base);
 }
@@ -9674,9 +10156,12 @@ int intel_framebuffer_init(struct drm_device *dev,
                           struct drm_mode_fb_cmd2 *mode_cmd,
                           struct drm_i915_gem_object *obj)
 {
+        int aligned_height, tile_height;
        int pitch_limit;
        int ret;
+        WARN_ON(!mutex_is_locked(&dev->struct_mutex));
        if (obj->tiling_mode == I915_TILING_Y) {
                DRM_DEBUG("hardware does not support tiling Y\n");
                return -EINVAL;
@@ -9765,8 +10250,16 @@ int intel_framebuffer_init(struct drm_device *dev,
        if (mode_cmd->offsets[0] != 0)
                return -EINVAL;
+        tile_height = IS_GEN2(dev) ? 16 : 8;
+        aligned_height = ALIGN(mode_cmd->height,
+                               obj->tiling_mode ? tile_height : 1);
+        /* FIXME drm helper for size checks (especially planar formats)? */
+        if (obj->base.size < aligned_height * mode_cmd->pitches[0])
+                return -EINVAL;
        drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
        intel_fb->obj = obj;
+        intel_fb->obj->framebuffer_references++;
        ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
        if (ret) {
@@ -9792,9 +10285,15 @@ intel_user_framebuffer_create(struct drm_device *dev,
        return intel_framebuffer_create(dev, mode_cmd, obj);
 }
+#ifndef CONFIG_DRM_I915_FBDEV
+static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
+{
+}
+#endif
 static const struct drm_mode_config_funcs intel_mode_funcs = {
        .fb_create = intel_user_framebuffer_create,
-        .output_poll_changed = intel_fb_output_poll_changed,
+        .output_poll_changed = intel_fbdev_output_poll_changed,
 };
 /* Set up chip specific display functions */
@@ -9820,7 +10319,6 @@ static void intel_init_display(struct drm_device *dev)
                dev_priv->display.update_plane = ironlake_update_plane;
        } else if (HAS_PCH_SPLIT(dev)) {
                dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
-                dev_priv->display.get_clock = ironlake_crtc_clock_get;
                dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
                dev_priv->display.crtc_enable = ironlake_crtc_enable;
                dev_priv->display.crtc_disable = ironlake_crtc_disable;
@@ -9828,7 +10326,6 @@ static void intel_init_display(struct drm_device *dev)
                dev_priv->display.update_plane = ironlake_update_plane;
        } else if (IS_VALLEYVIEW(dev)) {
                dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
-                dev_priv->display.get_clock = i9xx_crtc_clock_get;
                dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
                dev_priv->display.crtc_enable = valleyview_crtc_enable;
                dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -9836,7 +10333,6 @@ static void intel_init_display(struct drm_device *dev)
                dev_priv->display.update_plane = i9xx_update_plane;
        } else {
                dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
-                dev_priv->display.get_clock = i9xx_crtc_clock_get;
                dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
                dev_priv->display.crtc_enable = i9xx_crtc_enable;
                dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -9886,7 +10382,7 @@ static void intel_init_display(struct drm_device *dev)
                        dev_priv->display.write_eld = ironlake_write_eld;
                        dev_priv->display.modeset_global_resources =
                                ivb_modeset_global_resources;
-                } else if (IS_HASWELL(dev)) {
+                } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
                        dev_priv->display.fdi_link_train = hsw_fdi_link_train;
                        dev_priv->display.write_eld = haswell_write_eld;
                        dev_priv->display.modeset_global_resources =
@@ -9894,7 +10390,8 @@ static void intel_init_display(struct drm_device *dev)
                }
        } else if (IS_G4X(dev)) {
                dev_priv->display.write_eld = g4x_write_eld;
-        }
+        } else if (IS_VALLEYVIEW(dev))
+                dev_priv->display.write_eld = ironlake_write_eld;
        /* Default just returns -ENODEV to indicate unsupported */
        dev_priv->display.queue_flip = intel_default_queue_flip;
@@ -9917,6 +10414,7 @@ static void intel_init_display(struct drm_device *dev)
                dev_priv->display.queue_flip = intel_gen6_queue_flip;
                break;
        case 7:
+        case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
                dev_priv->display.queue_flip = intel_gen7_queue_flip;
                break;
        }
@@ -10012,8 +10510,7 @@ static struct intel_quirk intel_quirks[] = {
        /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
        { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
-        /* 830/845 need to leave pipe A & dpll A up */
+        /* 830 needs to leave pipe A & dpll A up */
-        { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
        { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
        /* Lenovo U160 cannot use SSC on LVDS */
@@ -10022,20 +10519,11 @@ static struct intel_quirk intel_quirks[] = {
        /* Sony Vaio Y cannot use SSC on LVDS */
        { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
-        /* Acer Aspire 5734Z must invert backlight brightness */
+        /*
-        { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
+         * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
+         * seem to use inverted backlight PWM.
-        /* Acer/eMachines G725 */
+         */
-        { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
+        { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
-        /* Acer/eMachines e725 */
-        { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
-        /* Acer/Packard Bell NCL20 */
-        { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
-        /* Acer Aspire 4736Z */
-        { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
        /* Dell XPS13 HD Sandy Bridge */
        { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
@@ -10084,12 +10572,19 @@ static void i915_disable_vga(struct drm_device *dev)
 void intel_modeset_init_hw(struct drm_device *dev)
 {
-        intel_init_power_well(dev);
+        struct drm_i915_private *dev_priv = dev->dev_private;
        intel_prepare_ddi(dev);
        intel_init_clock_gating(dev);
+        /* Enable the CRI clock source so we can get at the display */
+        if (IS_VALLEYVIEW(dev))
+                I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+                           DPLL_INTEGRATED_CRI_CLK_VLV);
+        intel_init_dpio(dev);
        mutex_lock(&dev->struct_mutex);
        intel_enable_gt_powersave(dev);
        mutex_unlock(&dev->struct_mutex);
@@ -10357,7 +10852,7 @@ void i915_redisable_vga(struct drm_device *dev)
            (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
                return;
-        if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
+        if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
                DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
                i915_disable_vga(dev);
        }
@@ -10380,6 +10875,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
                                                                 &crtc->config);
                crtc->base.enabled = crtc->active;
+                crtc->primary_enabled = crtc->active;
                DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
                              crtc->base.base.id,
@@ -10420,20 +10916,11 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
                }
                encoder->connectors_active = false;
-                DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
+                DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
                              encoder->base.base.id,
                              drm_get_encoder_name(&encoder->base),
                              encoder->base.crtc ? "enabled" : "disabled",
-                              pipe);
+                              pipe_name(pipe));
-        }
-        list_for_each_entry(crtc, &dev->mode_config.crtc_list,
-                            base.head) {
-                if (!crtc->active)
-                        continue;
-                if (dev_priv->display.get_clock)
-                        dev_priv->display.get_clock(crtc,
-                                                    &crtc->config);
        }
        list_for_each_entry(connector, &dev->mode_config.connector_list,
@@ -10460,7 +10947,6 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum pipe pipe;
-        struct drm_plane *plane;
        struct intel_crtc *crtc;
        struct intel_encoder *encoder;
        int i;
@@ -10507,7 +10993,12 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
                pll->on = false;
        }
+        if (IS_HASWELL(dev))
+                ilk_wm_get_hw_state(dev);
        if (force_restore) {
+                i915_redisable_vga(dev);
                /*
                 * We need to use raw interfaces for restoring state to avoid
                 * checking (bogus) intermediate states.
@@ -10519,10 +11010,6 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
                        __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
                                         crtc->fb);
                }
-                list_for_each_entry(plane, &dev->mode_config.plane_list, head)
-                        intel_plane_restore(plane);
-                i915_redisable_vga(dev);
        } else {
                intel_modeset_update_staged_output_state(dev);
        }
@@ -10545,6 +11032,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_crtc *crtc;
+        struct drm_connector *connector;
        /*
         * Interrupts and polling as the first thing to avoid creating havoc.
@@ -10585,6 +11073,10 @@ void intel_modeset_cleanup(struct drm_device *dev)
        /* destroy backlight, if any, before the connectors */
        intel_panel_destroy_backlight(dev);
+        /* destroy the sysfs files before encoders/connectors */
+        list_for_each_entry(connector, &dev->mode_config.connector_list, head)
+                drm_sysfs_connector_remove(connector);
        drm_mode_config_cleanup(dev);
        intel_cleanup_overlay(dev);
@@ -10680,7 +11172,7 @@ intel_display_capture_error_state(struct drm_device *dev)
        if (INTEL_INFO(dev)->num_pipes == 0)
                return NULL;
-        error = kmalloc(sizeof(*error), GFP_ATOMIC);
+        error = kzalloc(sizeof(*error), GFP_ATOMIC);
        if (error == NULL)
                return NULL;
@@ -10688,6 +11180,9 @@ intel_display_capture_error_state(struct drm_device *dev)
                error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
        for_each_pipe(i) {
+                if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i)))
+                        continue;
                if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
                        error->cursor[i].control = I915_READ(CURCNTR(i));
                        error->cursor[i].position = I915_READ(CURPOS(i));
@@ -10721,6 +11216,10 @@ intel_display_capture_error_state(struct drm_device *dev)
        for (i = 0; i < error->num_transcoders; i++) {
                enum transcoder cpu_transcoder = transcoders[i];
+                if (!intel_display_power_enabled(dev,
+                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
+                        continue;
                error->transcoder[i].cpu_transcoder = cpu_transcoder;
                error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
@@ -10732,12 +11231,6 @@ intel_display_capture_error_state(struct drm_device *dev)
                error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
        }
-        /* In the code above we read the registers without checking if the power
-         * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
-         * prevent the next I915_WRITE from detecting it and printing an error
-         * message. */
-        intel_uncore_clear_errors(dev);
        return error;
 }
@@ -10782,7 +11275,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
        }
        for (i = 0; i < error->num_transcoders; i++) {
-                err_printf(m, "  CPU transcoder: %c\n",
+                err_printf(m, "CPU transcoder: %c\n",
                           transcoder_name(error->transcoder[i].cpu_transcoder));
                err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
                err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);